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Integrated Circuit Design ICD Integrated Circuit Design Assessment Informal Coursework LEdit Gate Layout Integrated Circuit Design Examination Books Digital Integrated Circuits Iain McNally Jan Rabaey PrenticeHall lectures Principles of CMOS VLSI Design ACircuits and Systems Perspective Koushik Maharatna Neil Weste David Harris AddisonWesley lectures Notes Resources httpusersecssotonacukbimnotesicd History Integrated Circuit Design Iain McNally First Transistor John Bardeen Walter Brattain and William Shockley Bell Labs Content Integrated Circuits Proposed Introduction Geoffrey Dummer Royal Radar Establishment prototype failed Overview of Technologies Layout First Integrated Circuit Design Rules and Abstraction Jack Kilby Texas Instruments Coinventor Cell Design and Euler Paths First Planar Integrated Circuit System Design using StandardCells Robert Noyce Fairchild Coinventor Pass Transistor Circuits First Commercial ICs Storage Simple logic functions from TI and Fairchild PLAs Moores Law Gordon Moore Fairchild observes the trends in integration Wider View History History Moores Law Moores Law a Selffullling Prophesy Predicts exponential growth in the number of components per chip The whole industry uses the Moores Law curve to plan new fabrication facilities Doubling Every Year In Gordon Moore observed that the number of components per chip had Slower wasted investment doubled every year since and predicted that the trend would continue through to Must keep up with the Joneses Moore describes his initial growth predictions as ridiculously precise Doubling Every Two Years Faster too costly In Moorerevised growth predictions to doubling every two years Growth would now depend only on process improvements rather than on more Cost of capital equipment to build ICs doubles approximately ev efcient packing of components ery years In he predicted that the growth would continue at the same rate for an other years before slowing due to physical limits or the Intels History Moores Law at Intel Dual Core Itantium 2 1,000,000,000 Itantium 2 Itantium 100,000,000 Pentium 4 Pentium III 10,000,000 Pentium II Pentium 1,000,000 486 DX 286 386 100,000 8086 10,000 4004 8080 8008 1,000 1970 1980 1990 2000 2010 Intel was founded by Gordon Moore and Robert Noyce from Fairchild Overview of Technologies Overview of Technologies Components for Logic All functions can be realized with a single NOR base gate Diode PN Bipolar Transistors N P P N N P MOS Transistors Enhancement Depletion Silicon Oxide Insulator G G N-Channel S D S N P N D SUB P-Channel SUB Field induced N-channel NAND gates could be used instead Overview of Technologies Overview of Technologies Other Bipolar Technologies TTL NAND Gate ECL OR/NOR Gate A A Z Z B B Z RTL Inverter and NOR gate VCC VCC Z VCC A VCC A A Z Z Z Z B B AB Z Z A AB VEE TTL gives faster switching than RTL at the expense of greater complexity The characteristic multiemitter transistor reduces the overall component count ECL is a very high speed high power nonsaturating technology Most TTL families are more complex than the basic version shown here Overview of Technologies Digital CMOS Circuits Alternative representations for CMOS transistors NMOS a VLSI technology VDD VDD A A Z Z B B VDD P-Channel Z Z A N-Channel AB B Various shorthands are used for simplifying CMOS circuit diagrams Circuit function determined by seriesparallel combination of devices In general substrate connections are not drawn where they connect to Vdd PMOS and Gnd NMOS Depletion transistor acts as nonlinear load resistor All CMOS devices are enhancement mode Resistance increases as the enhancement device turns on thus reducing power consumption Transistors act as simple digitally controlled switches The low output voltage is determined by the size ratio of the devices Overview of Technologies Digital CMOS Circuits CMOS logic Static CMOS complementary gates CMOS state of the art VLSI VDD A A A Z B Z B Z B C C V DD AZA Z An active PMOS device complements the NMOS device giving rail to rail output swing For any set of inputs there will exist either a path to Vdd or a path to Gnd negligible static power consumption Digital CMOS Circuits Compound Gates A A B B Z C D Z C E F All compound gates are inverting Realisable functions are arbitrary ANDOR expressions with inverted output Digital CMOS Circuits Compound Gate Example VDD Pull Up Network , , , Symbol A B Z C D Pull Down Network , , , GND Components for Digital IC Design Components for Digital IC Design Diodes and Bipolar Transistors MOS Transistors Simple NMOS Transistor Diode Thin Oxide Polysilicon Thick Oxide G P N P G G SD N N N S D SDN PN P-substrate SUB SUB SUB P N G Polysilicon Mask Ideal structureD Real structureD S D Active Area Mask Depth controlled implants Components for Digital IC Design Components for Digital IC Design Diodes and Bipolar Transistors Simple NMOS Transistor NPN Transistor Active Area mask denes extent of Thick Oxide EBC Polysilicon mask also controls extent of Thin Oxide alias Gate Oxide N PN N Ntype implant has no extra mask P N It is blocked by thick oxide and by polysilicon The implant is Self Aligned Substrate connection is to bottom of wafer EBC All substrates to ground NPN Gate connection not above transistor area Design Rule Two ntype implants CMOS Process Components for Digital IC Design CMOS Inverter MOS Transistors NMOS Transistor G SUB S D N P P ++N N + P well P N G P N P well mask N-well Active Area P+ implant mask N implant N SUB SD P implant P Polysilicon Contact Window Metal N+ implant mask CMOS Process Components for Digital IC Design CMOS Inverter NMOS Transistor Where it is not suitable for substrate connections to be shared a more complex process is used Five masks must be used to dene the transistor The process described hereisanNWell process since it has only an N Well PWell and Twin Tub processes also exist PWell Active Area Note that the PN junction between chip substrate and N Well will remain re verse biased Polysilicon Thus the transistors remain isolated N implant P implant N implant denes NMOS sourcedrain and PMOS substrate contact PWell for isolation P implant denes PMOS sourcedrain and NMOS substrate contact Top substrate connection PN implants produce good ohmic contacts N-well P N Active Area defines Thick Oxide P N Polysilicon defines Thin Oxide P N N implant NN N aligned to AA and Poly PN P implant PN N P P N aligned to AA and Poly PN Contact Window PN N P PN P N Metal P NN PPN PN Photolithography Design Rules Toprevent chip failure designs must conform to design rules Photoresist Exposure UV Light Single layer rules Contact/Proximity Mask Glass Mask Mask Pattern (chrome) Silicon Wafer Photoresist Development Oxide Growth Oxide Etch Multilayer rules SiO 2 Photoresist Deposition Photoresist Photoresist Strip (positive) Mask Making Derivation of Design Rules Reticle written by scanning Pattern reproduced on wafer (or contact/proximity mask) electron beam by step and repeat with optical reduction Isotropic Etching Mask Misalignment Optical Focus over 3D terrain UV Light Reticle Mask Reticle Mask Lens Lateral Diffusion Misalignment can be Cumulative N NN is aligned to NN is aligned to Optical reduction allows narrower line widths Design Rules Abstraction Stick Diagrams m CMOS inverter Stick diagrams give us many of the benets of abstraction N-well Much easierfaster than full mask specication Active Area Process independent valid for any CMOS process P implant = NOT{ N implant } Easy to change Polysilicon while avoiding some of the problems Contact Window Optimized layout may be generated much more easily from a stick diagram than from transistor or gate level designs Metal note that all IC designs must end at the mask level Abstraction Digital CMOS Design Levels of Abstraction Stick Diagrams Mask Level Design Laborious TechnologyProcess dependent Metal Polysilicon Design rules may change during a design N+ P+ Transistor Level Design Contact Process independent Technology dependent Tap Combined contact Gate Level Design & tap ProcessTechnology independent Digital CMOS Design Sticks and CAD Symbolic Capture Stick Diagrams L=0.5 W=2.2 L=0.5 W=1.1 Transistors are placed and explicitly sized components are joined with zero width wires contacts are automatically selected as required A semiautomatic compaction process will create DRC correct layout Digital CMOS Design Sticks and CAD Magic Stick Diagrams Explore your Design Space Implications of crossovers Number of contacts Arrangement of devices and connections Process independent layout Log style design sticks with width DRC errors are agged immediately again contacts are automatically selected as required Easy to expand to a full layout for a particular process Online DRC leads to rapid generation of correct designs symbolic capture style compaction is available if desired Digital CMOS Design Digital CMOS Design A logical approach to gate layout Finding an Euler Path Computer Algorithms All complementary gates may be designed using a single row of ntransistors above or It is relatively easy for a computer to consider all possible arrangements of below a single row of ptransistors aligned at common gate connections transistors in search of a suitable Euler path This is not so easy for the human designer One Human Algorithm Find a path which passes through all ntransistors exactly once Express the path in terms of the gate connections Is it possible
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