DOCSLIB.ORG

EDN Magazine, December 17, 2004 (.Pdf)

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
EDN Magazine, December 17, 2004 (.Pdf) ᮋ HE BEST 100 PRODUCTS OF 2004 encompass a range of architectures and technologies Tand a plethora of categories—from analog ICs to multimedia to test-and-measurement tools. All are innovative, but, of the thousands that manufacturers announce each year and the hundreds that EDN reports on, only about 100 hot products make our readers re- ally sit up and take notice. Here are the picks from this year's crop. We present the basic info here. To get the whole scoop and find out why these products are so compelling, go to the Web version of this article on our Web site at www.edn.com. There, you'll find links to the full text of the articles that cover these products' dazzling features. ANALOG ICs Power Integrations COMMUNICATIONS NetLogic Microsystems Analog Devices LNK306P Atheros Communications NSE5512GLQ network AD1954 audio DAC switching power converter AR5005 Wi-Fi chip sets search engine www.analog.com www.powerint.com www.atheros.com www.netlogicmicro.com D2Audio Texas Instruments Fulcrum Microsystems Parama Networks XR125 seven-channel VCA8613 FM1010 six-port SPI-4,2 PNI8040 add-drop module eight-channel VGA switch chip multiplexer www.d2audio.com www.ti.com www.fulcrummicro.com www.paramanet.com International Rectifier Wolfson Microelectronics Motia PMC-Sierra IR2520D CFL ballast WM8740 audio DAC Javelin smart-antenna IC MSP2015, 2020, 4000, and power controller www.wolfsonmicro.com www.motia.com 5000 VoIP gateway chips www.irf.com www.pmc-sierra.com www.edn.com December 17, 2004 | edn 29 100 Texas Instruments Intel DISCRETE SEMICONDUCTORS EMBEDDED TOOLS TCS3500 EDGE handset NetStructure MPCBL0001 Advanced Linear Devices EEMBC chip set single-board computer ALD1121E and ALD1123E Digital-entertainment www.ti.com www.intel.com matched MOSFETs security benchmarks www.aldinc.com www.eembc.org Zarlink Gumstix TDM-over-IP packet Gumstix single-board Vishay Intertechnology Enea Embedded Technology processor computer SSA23L through SSC54 Orchestra Development Suite www.zarlink.com www.gumstix.com Schottky-rectifier family Linux/OSE development www.vishay.com platform COMPONENTS General Micro Systems www.ose.com AVX/Kyocera P60x single-board computer EDA KNA21series EMI filter www.gms4sbc.com Cadence Fluent in chip form Allegro Package Designer IcePak thermal-analysis www.avxcorp.com Micro/sys for pc-board package and software SBC4495 single-board interconnect design www.fluent.com Coto Technology computer www.cadence.com B41 BGA quad reed relay www.embeddedsys.com Green Hills Software www.cotorelay.com Coventor CAN Development Kit appli- Parvus CoventorWare MEMS- cation-development tool GrafTech International MPEG104 PC/104 encoder design tool www.ghs.com Spreadershield anisotropic www.parvus.com www.coventor.com heat spreader National Instruments www.graftech.com Radiotronix Denali Software CompactRIO custom Wi.232 transceiver/controller PureSuite interface-verifica- embedded hardware Hermetic Switch www.radiotronix.com tion suite for PCI Express www.ni.com HSR-003 reed relay compliance www.hermeticswitch.com DIGITAL AND PROGRAMMABLE ICs www.denali.com Open Source Altera TinyOS embedded-sensor OS LEDtronics Max II high-density CPLDs Flomerics www.tinyos.net Concave-lens LED family www.altera.com Flo/PCB electrical-and www.ledtronics.com mechanical-collaboration Swell Software Altera software Portable Embedded GUI Murata Electronics Stratix II FPGA family www.flomerics.com software North America www.altera.com www.swellsoftware.com NFM18PS low-ESL capacitor Jasper Design Automation www.murata.com Lattice JasperGold formal- TimeSys EC and ECP conventional verification tool TimeStorm IDE development NVE Corp and DSP-enhanced FPGA www.jasper-da.com and testing environment IL6xx family GMR digital families www.timesys.com couplers www.latticesemi.com Mentor www.nve.com Catapult C algorithm- MULTIMEDIA Leopard Logic synthesis tool Analog Devices Vishay Intertechnology Gladiator CLDs standard- www.mentor.com ADSP-21365 and ADSP- SSA23L series Schottky cell-ASICs with embedded 21364 audio DSPs rectifiers FPGA cores Novas www.analog.com www.vishay.com www.leopardlogic.com Reusner Design Knowledge Publisher design-reuse tool Cirrus Logic COMPUTERS, BOARDS, AND BUSES Renesas www.novas.com CS49500, CS49510, and Digi International 4-Gbit AG (assist gate)-AND CS49520 audio DSPs Digi Connect Wi-ME/EM flash memory for data/file- PowerEscape www.cirrus.com 802.11b modules storage applications PowerEscape Analyzer+Cache www.digi.com www.renesas.com software algorithm analyzer LSI Logic tools DMN-8602 and DMN-8652 Inova Computers Xilinx www.powerescape.com DVD-recorder chips ICP-PM single-board Virtex-4 FX, LX and SX next- www.lsilogic.com computer generation high-end FPGAs www.inova-computers.com www.xilinx.com 30 edn | December 17, 2004 www.edn.com 100 National Semiconductor Creative Labs 3DLabs Freescale Ansoft LM2501and LM2502 Mobile subsidiary MSC812x Family quad-core ePhysics software for thermal, Pixel Link transmitter/ Realizm 100, 200, and 800 DSP stress analysis receivers graphics boards www.freescale.com www.ansoft.com www.national.com www.creativelabs.com Royal Philips Electronics The MathWorks Nvidia Nvidia LPC2130 32-bit ARM7 Matlab 7; Simulink 6 math, GoForce 3D 4500 graphics GeForce 6800 graphics- microcontroller simulation tools and imaging processor processor family www.semiconductors.philips. www.mathworks.com www.nvidia.com www.nvidia.com com The MathWorks Silicon Image Seagate Technology Stretch Video and Image Processing SiI 9030 HDMI transmitter Savvio 2.5-in. hard-disk drives S5000 Family of software- Blockset C-code model and SiI 9021 and SiI 9031 www.seagate.com configurable processors development receivers www.stretchinc.com www.mathworks.com www.siimage.com POWER Artesyn Technologies Tensilica National Instruments Texas Instruments VRM10 series nonisolated Xtensa LX flexible-length SignalExpress virtual- TMS320DM320 imaging point-of-load converter instruction-extension instrumentation software processor www.artesyn.com processor architecture www.ni.com www.ti.com www.tensilica.com E-T-A Circuit Breakers TEST AND MEASUREMENT ViXS ESS60-T electronic, Texas Instruments Agilent XCode II multimedia controllable circuit breaker C6414/15/16 90-nm, DSO80000 series 10- to 13- processors www.e-t-a.com 1-GHz DSPs GHz-bandwidth, real-time- www.vixs.com www.ti.com sampling DSOs Evans Capacitor www.agilent.com NETWORK PROCESSORS Button Cell Hybrid super- RF LINKS AMCC capacitor in button cell Microtune Agilent Mission Access multiservice www.evanscap.com MT212 150- to 1000-MHz B4655A FPGA dynamic-probe network processor tuner logic-analysis application www.amcc.com Power Integrations www.microtune.com www.agilent.com LinkSwitch-TN family Cavium Networks switcher-core IC OKW Electronics LeCroy Corp Octeon NSP network-services www.powerint.com 110 Series KEELOQ AM WaveSurfer series small-foot- processors keyfob encoders print, large-screen DSOs www.cavium.com Vicor Corp www.okwelectronics.com www.lecroy.com VIC-in-a-Brick IBC series Mindspeed Technologies bus-converter modules Peregrine Semiconductor Strategic Test TSP3 family programmable www.vicr.com PE4261 and PE4263 RF switch UF7221 32-channel, 40-MHz traffic-management processors www.peregrine-semi.com pulse-pattern generator www.mindspeed.com V-Infinity LLC www.strategic-test.com VPHV12 series high-voltage Vishay Intertechnology PERIPHERALS supplies TSDF12830YS VHF/UHF Tektronix ATI Technologies www.v-infinity.com amplifier and switch TDS8200 series 70-GHz- X800 graphics-processor www.vishay.com bandwidth sequential-equiva- family PROCESSORS lent-time-sampling DSOs www.ati.com Atmel Zarlink Semiconductor www.tek.com AT572D740 Diopsis dual- ZL10038 set-top-box/ ATI Technologies core DSP/RISC processor DTV tuner VeriWave Radeon Xpress 200 core-logic www.atmel.com www.zarlink.com WaveTest IEEE 802.11 chip-set series protocol-test system www.ati.com Dallas Semiconductor SOFTWARE www.veriwave.com MAXQ2000 low-power, low- Agilent Technologies Broadcom noise 16-bit processor VEE Pro 7.0 software for T&M BCM4780 NASoC www.maxim-ic.com application development processor chip www.agilent.com www.broadcom.com 32 edn | December 17, 2004 www.edn.com.
Load more

Recommended publications
  • Wind River Vxworks Platforms 3.8
    Wind River VxWorks Platforms 3.8 The market for secure, intelligent, Table of Contents Build System ................................ 24 connected devices is constantly expand- Command-Line Project Platforms Available in ing. Embedded devices are becoming and Build System .......................... 24 VxWorks Edition .................................2 more complex to meet market demands. Workbench Debugger .................. 24 New in VxWorks Platforms 3.8 ............2 Internet connectivity allows new levels of VxWorks Simulator ....................... 24 remote management but also calls for VxWorks Platforms Features ...............3 Workbench VxWorks Source increased levels of security. VxWorks Real-Time Operating Build Configuration ...................... 25 System ...........................................3 More powerful processors are being VxWorks 6.x Kernel Compatibility .............................3 considered to drive intelligence and Configurator ................................. 25 higher functionality into devices. Because State-of-the-Art Memory Host Shell ..................................... 25 Protection ..................................3 real-time and performance requirements Kernel Shell .................................. 25 are nonnegotiable, manufacturers are VxBus Framework ......................4 Run-Time Analysis Tools ............... 26 cautious about incorporating new Core Dump File Generation technologies into proven systems. To and Analysis ...............................4 System Viewer ........................
    [Show full text]
  • Reviving the Development of Openchrome
    Reviving the Development of OpenChrome Kevin Brace OpenChrome Project Maintainer / Developer XDC2017 September 21st, 2017 Outline ● About Me ● My Personal Story Behind OpenChrome ● Background on VIA Chrome Hardware ● The History of OpenChrome Project ● Past Releases ● Observations about Standby Resume ● Developmental Philosophy ● Developmental Challenges ● Strategies for Further Development ● Future Plans 09/21/2017 XDC2017 2 About Me ● EE (Electrical Engineering) background (B.S.E.E.) who specialized in digital design / computer architecture in college (pretty much the only undergraduate student “still” doing this stuff where I attended college) ● Graduated recently ● First time conference presenter ● Very experienced with Xilinx FPGA (Spartan-II through 7 Series FPGA) ● Fluent in Verilog / VHDL design and verification ● Interest / design experience with external communication interfaces (PCI / PCIe) and external memory interfaces (SDRAM / DDR3 SDRAM) ● Developed a simple DMA engine for PCI I/F validation w/Windows WDM (Windows Driver Model) kernel device driver ● Almost all the knowledge I have is self taught (university engineering classes were not very useful) 09/21/2017 XDC2017 3 Motivations Behind My Work ● General difficulty in obtaining meaningful employment in the digital hardware design field (too many students in the field, difficulty obtaining internship, etc.) ● Collects and repairs abandoned computer hardware (It’s like rescuing puppies!) ● Owns 100+ desktop computers and 20+ laptop computers (mostly abandoned old stuff I
    [Show full text]
  • GPU Developments 2018
    GPU Developments 2018 2018 GPU Developments 2018 © Copyright Jon Peddie Research 2019. All rights reserved. Reproduction in whole or in part is prohibited without written permission from Jon Peddie Research. This report is the property of Jon Peddie Research (JPR) and made available to a restricted number of clients only upon these terms and conditions. Agreement not to copy or disclose. This report and all future reports or other materials provided by JPR pursuant to this subscription (collectively, “Reports”) are protected by: (i) federal copyright, pursuant to the Copyright Act of 1976; and (ii) the nondisclosure provisions set forth immediately following. License, exclusive use, and agreement not to disclose. Reports are the trade secret property exclusively of JPR and are made available to a restricted number of clients, for their exclusive use and only upon the following terms and conditions. JPR grants site-wide license to read and utilize the information in the Reports, exclusively to the initial subscriber to the Reports, its subsidiaries, divisions, and employees (collectively, “Subscriber”). The Reports shall, at all times, be treated by Subscriber as proprietary and confidential documents, for internal use only. Subscriber agrees that it will not reproduce for or share any of the material in the Reports (“Material”) with any entity or individual other than Subscriber (“Shared Third Party”) (collectively, “Share” or “Sharing”), without the advance written permission of JPR. Subscriber shall be liable for any breach of this agreement and shall be subject to cancellation of its subscription to Reports. Without limiting this liability, Subscriber shall be liable for any damages suffered by JPR as a result of any Sharing of any Material, without advance written permission of JPR.
    [Show full text]
  • Intel Quartus Prime Pro Edition User Guide: Programmer Send Feedback
    Intel® Quartus® Prime Pro Edition User Guide Programmer Updated for Intel® Quartus® Prime Design Suite: 21.2 Subscribe UG-20134 | 2021.07.21 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Intel® Quartus® Prime Programmer User Guide..............................................................4 1.1. Generating Primary Device Programming Files........................................................... 5 1.2. Generating Secondary Programming Files................................................................. 6 1.2.1. Generating Secondary Programming Files (Programming File Generator)........... 7 1.2.2. Generating Secondary Programming Files (Convert Programming File Dialog Box)............................................................................................. 11 1.3. Enabling Bitstream Security for Intel Stratix 10 Devices............................................ 18 1.3.1. Enabling Bitstream Authentication (Programming File Generator)................... 19 1.3.2. Specifying Additional Physical Security Settings (Programming File Generator).............................................................................................. 21 1.3.3. Enabling Bitstream Encryption (Programming File Generator).........................22 1.4. Enabling Bitstream Encryption or Compression for Intel Arria 10 and Intel Cyclone 10 GX Devices.................................................................................................. 23 1.5. Generating Programming Files for Partial Reconfiguration.........................................
    [Show full text]
  • A Superscalar Out-Of-Order X86 Soft Processor for FPGA
    A Superscalar Out-of-Order x86 Soft Processor for FPGA Henry Wong University of Toronto, Intel [email protected] June 5, 2019 Stanford University EE380 1 Hi! ● CPU architect, Intel Hillsboro ● Ph.D., University of Toronto ● Today: x86 OoO processor for FPGA (Ph.D. work) – Motivation – High-level design and results – Microarchitecture details and some circuits 2 FPGA: Field-Programmable Gate Array ● Is a digital circuit (logic gates and wires) ● Is field-programmable (at power-on, not in the fab) ● Pre-fab everything you’ll ever need – 20x area, 20x delay cost – Circuit building blocks are somewhat bigger than logic gates 6-LUT6-LUT 6-LUT6-LUT 3 6-LUT 6-LUT FPGA: Field-Programmable Gate Array ● Is a digital circuit (logic gates and wires) ● Is field-programmable (at power-on, not in the fab) ● Pre-fab everything you’ll ever need – 20x area, 20x delay cost – Circuit building blocks are somewhat bigger than logic gates 6-LUT 6-LUT 6-LUT 6-LUT 4 6-LUT 6-LUT FPGA Soft Processors ● FPGA systems often have software components – Often running on a soft processor ● Need more performance? – Parallel code and hardware accelerators need effort – Less effort if soft processors got faster 5 FPGA Soft Processors ● FPGA systems often have software components – Often running on a soft processor ● Need more performance? – Parallel code and hardware accelerators need effort – Less effort if soft processors got faster 6 FPGA Soft Processors ● FPGA systems often have software components – Often running on a soft processor ● Need more performance? – Parallel
    [Show full text]
  • Introduction to Intel® FPGA IP Cores
    Introduction to Intel® FPGA IP Cores Updated for Intel® Quartus® Prime Design Suite: 20.3 Subscribe UG-01056 | 2020.11.09 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Introduction to Intel® FPGA IP Cores..............................................................................3 1.1. IP Catalog and Parameter Editor.............................................................................. 4 1.1.1. The Parameter Editor................................................................................. 5 1.2. Installing and Licensing Intel FPGA IP Cores.............................................................. 5 1.2.1. Intel FPGA IP Evaluation Mode.....................................................................6 1.2.2. Checking the IP License Status.................................................................... 8 1.2.3. Intel FPGA IP Versioning............................................................................. 9 1.2.4. Adding IP to IP Catalog...............................................................................9 1.3. Best Practices for Intel FPGA IP..............................................................................10 1.4. IP General Settings.............................................................................................. 11 1.5. Generating IP Cores (Intel Quartus Prime Pro Edition)...............................................12 1.5.1. IP Core Generation Output (Intel Quartus Prime Pro Edition)..........................13 1.5.2. Scripting IP Core Generation....................................................................
    [Show full text]
  • North American Company Profiles 8X8
    North American Company Profiles 8x8 8X8 8x8, Inc. 2445 Mission College Boulevard Santa Clara, California 95054 Telephone: (408) 727-1885 Fax: (408) 980-0432 Web Site: www.8x8.com Email: [email protected] Fabless IC Supplier Regional Headquarters/Representative Locations Europe: 8x8, Inc. • Bucks, England U.K. Telephone: (44) (1628) 402800 • Fax: (44) (1628) 402829 Financial History ($M), Fiscal Year Ends March 31 1992 1993 1994 1995 1996 1997 1998 Sales 36 31 34 20 29 19 50 Net Income 5 (1) (0.3) (6) (3) (14) 4 R&D Expenditures 7 7 7 8 8 11 12 Capital Expenditures — — — — 1 1 1 Employees 114 100 105 110 81 100 100 Ownership: Publicly held. NASDAQ: EGHT. Company Overview and Strategy 8x8, Inc. is a worldwide leader in the development, manufacture and deployment of an advanced Visual Information Architecture (VIA) encompassing A/V compression/decompression silicon, software, subsystems, and consumer appliances for video telephony, videoconferencing, and video multimedia applications. 8x8, Inc. was founded in 1987. The “8x8” refers to the company’s core technology, which is based upon Discrete Cosine Transform (DCT) image compression and decompression. In DCT, 8-pixel by 8-pixel blocks of image data form the fundamental processing unit. 2-1 8x8 North American Company Profiles Management Paul Voois Chairman and Chief Executive Officer Keith Barraclough President and Chief Operating Officer Bryan Martin Vice President, Engineering and Chief Technical Officer Sandra Abbott Vice President, Finance and Chief Financial Officer Chris McNiffe Vice President, Marketing and Sales Chris Peters Vice President, Sales Michael Noonen Vice President, Business Development Samuel Wang Vice President, Process Technology David Harper Vice President, European Operations Brett Byers Vice President, General Counsel and Investor Relations Products and Processes 8x8 has developed a Video Information Architecture (VIA) incorporating programmable integrated circuits (ICs) and compression/decompression algorithms (codecs) for audio/video communications.
    [Show full text]
  • Intel® Arria® 10 Device Overview
    Intel® Arria® 10 Device Overview Subscribe A10-OVERVIEW | 2020.10.20 Send Feedback Latest document on the web: PDF | HTML Contents Contents Intel® Arria® 10 Device Overview....................................................................................... 3 Key Advantages of Intel Arria 10 Devices........................................................................ 4 Summary of Intel Arria 10 Features................................................................................4 Intel Arria 10 Device Variants and Packages.....................................................................7 Intel Arria 10 GX.................................................................................................7 Intel Arria 10 GT............................................................................................... 11 Intel Arria 10 SX............................................................................................... 14 I/O Vertical Migration for Intel Arria 10 Devices.............................................................. 17 Adaptive Logic Module................................................................................................ 17 Variable-Precision DSP Block........................................................................................18 Embedded Memory Blocks........................................................................................... 20 Types of Embedded Memory............................................................................... 21 Embedded Memory Capacity in
    [Show full text]
  • Demystifying Internet of Things Security Successful Iot Device/Edge and Platform Security Deployment — Sunil Cheruvu Anil Kumar Ned Smith David M
    Demystifying Internet of Things Security Successful IoT Device/Edge and Platform Security Deployment — Sunil Cheruvu Anil Kumar Ned Smith David M. Wheeler Demystifying Internet of Things Security Successful IoT Device/Edge and Platform Security Deployment Sunil Cheruvu Anil Kumar Ned Smith David M. Wheeler Demystifying Internet of Things Security: Successful IoT Device/Edge and Platform Security Deployment Sunil Cheruvu Anil Kumar Chandler, AZ, USA Chandler, AZ, USA Ned Smith David M. Wheeler Beaverton, OR, USA Gilbert, AZ, USA ISBN-13 (pbk): 978-1-4842-2895-1 ISBN-13 (electronic): 978-1-4842-2896-8 https://doi.org/10.1007/978-1-4842-2896-8 Copyright © 2020 by The Editor(s) (if applicable) and The Author(s) This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. Open Access This book is licensed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made. The images or other third party material in this book are included in the book’s Creative Commons license, unless indicated otherwise in a credit line to the material.
    [Show full text]
  • Moore's Law Motivation
    Motivation: Moore’s Law • Every two years: – Double the number of transistors CprE 488 – Embedded Systems Design – Build higher performance general-purpose processors Lecture 8 – Hardware Acceleration • Make the transistors available to the masses • Increase performance (1.8×↑) Joseph Zambreno • Lower the cost of computing (1.8×↓) Electrical and Computer Engineering Iowa State University • Sounds great, what’s the catch? www.ece.iastate.edu/~zambreno rcl.ece.iastate.edu Gordon Moore First, solve the problem. Then, write the code. – John Johnson Zambreno, Spring 2017 © ISU CprE 488 (Hardware Acceleration) Lect-08.2 Motivation: Moore’s Law (cont.) Motivation: Dennard Scaling • The “catch” – powering the transistors without • As transistors get smaller their power density stays melting the chip! constant 10,000,000,000 2,200,000,000 Transistor: 2D Voltage-Controlled Switch 1,000,000,000 Chip Transistor Dimensions 100,000,000 Count Voltage 10,000,000 ×0.7 1,000,000 Doping Concentrations 100,000 Robert Dennard 10,000 2300 Area 0.5×↓ 1,000 130W 100 Capacitance 0.7×↓ 10 0.5W 1 Frequency 1.4×↑ 0 Power = Capacitance × Frequency × Voltage2 1970 1975 1980 1985 1990 1995 2000 2005 2010 2015 Power 0.5×↓ Zambreno, Spring 2017 © ISU CprE 488 (Hardware Acceleration) Lect-08.3 Zambreno, Spring 2017 © ISU CprE 488 (Hardware Acceleration) Lect-08.4 Motivation Dennard Scaling (cont.) Motivation: Dark Silicon • In mid 2000s, Dennard scaling “broke” • Dark silicon – the fraction of transistors that need to be powered off at all times (due to power + thermal
    [Show full text]
  • Program Review Department of Computer Science
    PROGRAM REVIEW DEPARTMENT OF COMPUTER SCIENCE UNIVERSITY OF NORTH CAROLINA AT CHAPEL HILL JANUARY 13-15, 2009 TABLE OF CONTENTS 1 Introduction............................................................................................................................. 1 2 Program Overview.................................................................................................................. 2 2.1 Mission........................................................................................................................... 2 2.2 Demand.......................................................................................................................... 3 2.3 Interdisciplinary activities and outreach ........................................................................ 5 2.4 Inter-institutional perspective ........................................................................................ 6 2.5 Previous evaluations ...................................................................................................... 6 3 Curricula ................................................................................................................................. 8 3.1 Undergraduate Curriculum ............................................................................................ 8 3.1.1 Bachelor of Science ................................................................................................. 10 3.1.2 Bachelor of Arts (proposed) ...................................................................................
    [Show full text]
  • Integrated Circuit Design
    ICD Integrated Circuit Design Assessment Informal Coursework LEdit Gate Layout Integrated Circuit Design Examination Books Digital Integrated Circuits Iain McNally Jan Rabaey PrenticeHall lectures Principles of CMOS VLSI Design ACircuits and Systems Perspective Koushik Maharatna Neil Weste David Harris AddisonWesley lectures Notes Resources httpusersecssotonacukbimnotesicd History Integrated Circuit Design Iain McNally First Transistor John Bardeen Walter Brattain and William Shockley Bell Labs Content Integrated Circuits Proposed Introduction Geoffrey Dummer Royal Radar Establishment prototype failed Overview of Technologies Layout First Integrated Circuit Design Rules and Abstraction Jack Kilby Texas Instruments Coinventor Cell Design and Euler Paths First Planar Integrated Circuit System Design using StandardCells Robert Noyce Fairchild Coinventor Pass Transistor Circuits First Commercial ICs Storage Simple logic functions from TI and Fairchild PLAs Moores Law Gordon Moore Fairchild observes the trends in integration Wider View History History Moores Law Moores Law a Selffullling Prophesy Predicts exponential growth in the number of components per chip The whole industry uses the Moores Law curve to plan new fabrication facilities Doubling Every Year In Gordon Moore observed that the number of components per chip had Slower wasted investment doubled every year since and predicted that the trend would continue through to Must keep up with the Joneses Moore describes his initial growth predictions
    [Show full text]