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IA-64 Application Instruction Set Architecture Guide Revision IA-64 Application Instruction Set Architecture Guide Revision 1.0 IA-64 Application ISA Guide 1.0 THIS DOCUMENT IS PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WAR- RANTY OF MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. Information in this document is provided in connection with Intel/Hewlett-Packard products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel/Hewlett-Packard's Terms and Conditions of Sale for such products, Intel/Hewlett-Packard assumes no liability what- soever, and Intel/Hewlett-Packard disclaims any express or implied warranty, relating to sale and/or use of Intel/Hewlett- Packard products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringe- ment of any patent, copyright or other intellectual property right. Intel/Hewlett-Packard products are not intended for use in medical, life saving, or life sustaining applications. Intel/Hewlett-Packard may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel/Hewlett-Packard reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. IA-64 processors may contain design defects or errors known as errata which may cause the product to deviate from pub- lished specifications. Current characterized errata are available on request. Copyright © Intel Corporation / Hewlett-Packard Company, 1999 *Third-party brands and names are the property of their respective owners. HP/Intel IA-64 Application ISA Guide 1.0 Table of Contents 1 About the IA-64 Application ISA Guide . 1-1 1.1 Overview of IA-64 Application Instruction Set Architecture (ISA) Guide. .1-1 1.2 Terminology. 1-1 2 Introduction to the IA-64 Processor Architecture . 2-1 2.1 IA-64 Operating Environments . 2-1 2.2 Instruction Set Transition Model Overview. 2-2 2.3 PA-RISC Compatibility . 2-2 2.4 IA-64 Instruction Set Features . 2-2 2.5 Instruction Level Parallelism . 2-3 2.6 Compiler to Processor Communication . 2-3 2.7 Speculation . 2-3 2.7.1 Control Speculation . 2-3 2.7.2 Data Speculation. 2-4 2.8 Predication. 2-4 2.9 Register Stack . 2-5 2.10 Branching . 2-5 2.11 Register Rotation . 2-5 2.12 Floating-point Architecture . 2-5 2.13 Multimedia Support . 2-6 3 IA-64 Execution Environment . 3-1 3.1 Application Register State. 3-1 3.1.1 Reserved and Ignored Registers . 3-1 3.1.2 General Registers . 3-3 3.1.3 Floating-Point Registers . 3-3 3.1.4 Predicate Registers . 3-3 3.1.5 Branch Registers. 3-3 3.1.6 Instruction Pointer . 3-3 3.1.7 Current Frame Marker. 3-4 3.1.8 Application Registers . 3-4 3.1.9 Performance Monitor Data Registers (PMD) . 3-8 3.1.10 User Mask (UM). 3-8 3.1.11 Processor Identification Registers . 3-8 3.2 Memory . 3-10 3.2.1 Application Memory Addressing Model . 3-10 3.2.2 Addressable Units and Alignment. 3-10 3.2.3 Byte Ordering . 3-10 3.3 Instruction Encoding Overview . 3-11 3.4 Instruction Sequencing . 3-12 4 IA-64 Application Programming Model . 4-1 4.1 Register Stack . 4-1 4.1.1 Register Stack Operation . 4-1 4.1.2 Register Stack Instructions . 4-3 4.2 Integer Computation Instructions . 4-3 4.2.1 Arithmetic Instructions . 4-3 4.2.2 Logical Instructions . 4-4 4.2.3 32-Bit Addresses and Integers. 4-4 4.2.4 Bit Field and Shift Instructions . 4-4 4.2.5 Large Constants . 4-5 4.3 Compare Instructions and Predication . 4-5 4.3.1 Predication. 4-6 4.3.2 Compare Instructions . 4-6 4.3.3 Compare Types . 4-6 4.3.4 Predicate Register Transfers. 4-8 4.4 Memory Access Instructions . 4-8 HP/Intel Table of Contents iii IA-64 Application ISA Guide 1.0 4.4.1 Load Instructions . 4-9 4.4.2 Store Instructions. 4-9 4.4.3 Semaphore Instructions . 4-10 4.4.4 Control Speculation . 4-10 4.4.5 Data Speculation . 4-12 4.4.6 Memory Hierarchy Control and Consistency . .4-16 4.4.7 Memory Access Ordering . 4-18 4.5 Branch Instructions. 4-19 4.5.1 Modulo-Scheduled Loop Support . 4-20 4.5.2 Branch Prediction Hints . 4-22 4.6 Multimedia Instructions . 4-23 4.6.1 Parallel Arithmetic . 4-23 4.6.2 Parallel Shifts. 4-24 4.6.3 Data Arrangement . 4-24 4.7 Register File Transfers . 4-24 4.8 Character Strings and Population Count . 4-25 4.8.1 Character Strings . 4-25 4.8.2 Population Count . 4-26 5 IA-64 Floating-point Programming Model . ..
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