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Computer Architecture Figure 4.1 Chapter 4 Computer Architecture Figure 4.1 Input Central Main Output device processing unit memory device Bus Data flow Control Figure 4.1 Figure 4.2 Central processing unit (CPU) .:6# Status bits (.:6#) Accumulator ( ! ) Index register ( 8 ) Program counter (0#) Stack pointer (30) Instruction register ()2) Figure 4.3 Main memory 0000 0001 0002 0003 0004 0005 0006 . FFFE FFFF Figure 4.4 Main memory 0000 0003 0004 0007 000A 000B 000D . 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 000B 000B 1 1 0 1 0 0 0 1Figure 4.5 1 1 0 1 0 0 0 1 000C 000C 0 0 0 0 0 0 1 0 (a) The content in binary. (a) The content in binary. 000B 1 1 0 1 0 0 0 1 02 D1 02 D1 000C 000B 000C 000B 000C (a) The content in binary. (b) The content in hexadecimal. (b) The content in hexadecimal. 02 D1 000B 02D1 000B 02D1 000B 000C (c) The content in a machine (b) The content in(c) hexadecimal. The contentlanguage in a machine listing. language listing. 000B 02D1 (c) The content in a machine language listing. Figure 4.6 Instruction Specifier Instruction 0000 0000 Stop execution 0000 0001 Return from trap 0000 0010 Move stack pointer (SP) to accumulator (A) 0000 0011 Move NZVC flags to accumulator (A) 0000 010a Branch unconditional 0000 011a Branch if less than or equal to 0000 100a Branch if less than 0000 101a Branch if equal to 0000 110a Branch if not equal to 0000 111a Branch if greater than or equal to 0001 000a Branch if greater than 0001 001a Branch if V 0001 010a Branch if C 0001 011a Call subroutine 0001 100r Bitwise invert register r 0001 101r Negate register r 0001 110r Arithmetic shift left register r 0001 111r Arithmetic shift right register r 0010 000r Rotate left register r 0010 001r Rotate right register r 0010 01n Unimplemented opcode, unary trap 0010 1aaa Unimplemented opcode, nonunary trap 0011 0aaa Unimplemented opcode, nonunary trap 0011 1aaa Unimplemented opcode, nonunary trap 0100 0aaa Unimplemented opcode, nonunary trap 0100 1aaa Character input 0101 0aaa Character output 0101 1nn Return from call with n local bytes 0110 0aaa Add to stack pointer (SP) 0110 1aaa Subtract from stack pointer (SP) 0111 raaa Add to register r 1000 raaa Subtract from register r 1001 raaa Bitwise AND to register r 1010 raaa Bitwise OR to register r 1011 raaa Compare register r 1100 raaa Load register r from memory 1101 raaa Load byte register r from memory 1110 raaa Store register r to memory 1111 raaa Store byte register r to memory Instruction Specifier Instruction 0000 0000 Stop execution 0000 0001 Return from trap 0000 0010 Move stack pointer (SP) to accumulator (A) 0000 0011 Move NZVC flags to accumulator (A) 0000 010a Branch unconditional 0000 011a Branch if less than or equal to 0000 100a Branch if less than 0000 101a Branch if equal to 0000 110a Branch if not equal to 0000 111a Branch if greater than or equal to 0001 000a Branch if greater than 0001 001a Branch if V Figure 4.6 0001 010a Branch if C (Continued) 0001 011a Call subroutine 0001 100r Bitwise invert register r 0001 101r Negate register r 0001 110r Arithmetic shift left register r 0001 111r Arithmetic shift right register r 0010 000r Rotate left register r 0010 001r Rotate right register r 0010 01n Unimplemented opcode, unary trap 0010 1aaa Unimplemented opcode, nonunary trap 0011 0aaa Unimplemented opcode, nonunary trap 0011 1aaa Unimplemented opcode, nonunary trap 0100 0aaa Unimplemented opcode, nonunary trap 0100 1aaa Character input 0101 0aaa Character output 0101 1nn Return from call with n local bytes 0110 0aaa Add to stack pointer (SP) 0110 1aaa Subtract from stack pointer (SP) 0111 raaa Add to register r 1000 raaa Subtract from register r 1001 raaa Bitwise AND to register r 1010 raaa Bitwise OR to register r 1011 raaa Compare register r 1100 raaa Load register r from memory 1101 raaa Load byte register r from memory 1110 raaa Store register r to memory 1111 raaa Store byte register r to memory Instruction Specifier Instruction 0000 0000 Stop execution 0000 0001 Return from trap 0000 0010 Move stack pointer (SP) to accumulator (A) 0000 0011 Move NZVC flags to accumulator (A) 0000 010a Branch unconditional 0000 011a Branch if less than or equal to 0000 100a Branch if less than 0000 101a Branch if equal to 0000 110a Branch if not equal to 0000 111a Branch if greater than or equal to 0001 000a Branch if greater than 0001 001a Branch if V 0001 010a Branch if C 0001 011a Call subroutine 0001 100r Bitwise invert register r 0001 101r Negate register r 0001 110r Arithmetic shift left register r 0001 111r Arithmetic shift right register r 0010 000r Rotate left register r 0010 001r Rotate right register r 0010 01n Unimplemented opcode, unary trap 0010 1aaa Unimplemented opcode, nonunary trap 0011 0aaa Unimplemented opcode, nonunary trap 0011 1aaa Unimplemented opcode, nonunary trap 0100 0aaa Unimplemented opcode, nonunary trap 0100 1aaa Character input Figure 4.6 0101 0aaa Character output (Continued) 0101 1nn Return from call with n local bytes 0110 0aaa Add to stack pointer (SP) 0110 1aaa Subtract from stack pointer (SP) 0111 raaa Add to register r 1000 raaa Subtract from register r 1001 raaa Bitwise AND to register r 1010 raaa Bitwise OR to register r 1011 raaa Compare register r 1100 raaa Load register r from memory 1101 raaa Load byte register r from memory 1110 raaa Store register r to memory 1111 raaa Store byte register r to memory Figure 4.7 Instruction specifier Operand specifier (a) The two parts of a nonunary instruction Instruction specifier (b) A unary instruction Figure 4.7 Figure 4.8 aaa Addressing mode a Addressing mode r Register 000 Immediate 0 Immediate 0 Accumulator, A 001 Direct 1 Indexed 1 Index register, X 010 Indirect 011 Stack-relative (b) The addressing-a field. (c) The register-r field. 100 Stack-relative deferred 101 Indexed 110 Stack-indexed 111 Stack-indexed deferred (a) The addressing-aaa field. Figure 4.8 Figure 4.8 (Continued) aaa Addressing mode a Addressing mode r Register 000 Immediate 0 Immediate 0 Accumulator, A 001 Direct 1 Indexed 1 Index register, X 010 Indirect 011 Stack-relative (b) The addressing-a field. (c) The register-r field. 100 Stack-relative deferred 101 Indexed 110 Stack-indexed 111 Stack-indexed deferred (a) The addressing-aaa field. Figure 4.8 Figure 4.9 Main memory 10001101 00000011 010011 10 01A3 01A4 01A5 00011 1 10 01A6 Figure 4.9 The stop instruction • Instruction specifier: 0000 0000 • Causes the computer to stop The load instruction • Instruction specifier: 1100 raaa • Loads one word (two bytes) from memory to register r r Oprnd ; N r < 0 , Z r = 0 ← ← ← Figure 4.10, 4.11 Instruction specifier Operand specifier Opcode r aaa 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 C 1 0 0 4 A CPU Mem CPU Mem NZ 92EF C1004A NZ 10 92EF 004A Load accumulator 004A A 036D A 92EF Figure 4.10 (a) Before (b) After Figure 4.11 The store instruction • Instruction specifier: 1110 raaa • Stores one word (two bytes) from register r to memory Oprnd r ← Figure 4.12, 4.13 Instruction specifier Operand specifier Opcode r aaa 1 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 E 9 0 0 4 A CPU Mem CPU Mem X 16BC F082 E9004A X 16BC 16BC 004A Store index register 004A Figure 4.12 (a) Before (b) After Figure 4.13 The add instruction • Instruction specifier: 0111 raaa • Adds one word (two bytes) from memory to register r r r + Oprnd ; N r < 0 , Z r = 0 , ← ← ← V overflow , C carry ←{ } ←{ } Figure 4.14, 4.15 Instruction specifier Operand specifier Opcode r aaa 0 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 7 9 0 0 4 A CPU Mem CPU Mem NZVC FFF9 79004A NZVC 1000 FFF9 004A Add index register 004A X 0005 X FFFE Figure 4.14 (a) Before (b) After Figure 4.15 The subtract instruction • Instruction specifier: 1000 raaa • Subtracts one word (two bytes) from memory from register r r r Oprnd ; N r < 0 , Z r = 0 , ← − ← ← V overflow , C carry ←{ } ←{ } Figure 4.16, 4.17 Instruction specifier Operand specifier Opcode r aaa 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 8 1 0 0 4 A CPU Mem CPU Mem NZVC 0009 81004A NZVC 1000 0009 004A Subtract accumulator 004A A 0003 A FFF4FFFA Figure 4.16 (a) Before (b) After Figure 4.17 The and instruction • Instruction specifier: 1001 raaa • ANDs one word (two bytes) from memory to register r r r Oprnd ; N r < 0 , Z r = 0 ← ∧ ← ← Figure 4.18, 4.19 Instruction specifier Operand specifier Opcode r aaa 1 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 9 9 0 0 4 A CPU Mem CPU Mem NZ 00FF 99004A NZ 00 00FF 004A AddAnd index register 004A X 5DC3 X 00C3 Figure 4.18 (a) Before (b) After The or instruction • Instruction specifier: 1010 raaa • ORs one word (two bytes) from memory to register r r r Oprnd ; N r < 0 , Z r = 0 ← ∨ ← ← Figure 4.20 CPU Mem CPU Mem NZ 00FF A9004A NZ 00 00FF 004A Or index register 004A X 5DC3 X 5DFF (a) Before (b) After Figure 4.20 The not instruction • Instruction specifier: 0001 100r • Bit-wise NOT operation on register r • Each 0 changed to 1, each 1 changed to 0 r r ; N r < 0 , Z r = 0 ←¬ ← ← Figure 4.21, 4.22 Instruction specifier Opcode r 0 0 0 1 1 0 0 0 1 8 CPU CPU NZ 18 NZ 10 Not accumulator AX 0003 XA FFFC (a) Before (b) After Figure 4.21 Figure 4.22 The negate instruction • Instruction specifier: 0001 101r • Negate (take two’s complement of) register r r r ; N r < 0 , Z r = 0 ←− ← ← Figure 4.23 CPU CPU NZ 1A NZ 10 Negate accumulator AX 0003 AX FFFD (a) Before (b) After Figure 4.23 The load byte instruction • Instruction specifier: 1101 raaa • Loads one byte from memory to the right half of register r r 8..15 byte Oprnd ; N r < 0 , Z r = 0 ! "← ← ← Figure 4.24, 4.25 Instruction specifier Operand specifier Opcode r aaa 1 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0
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