Computer Architecture Figure 4.1

Home , Character (computing), Index register

Chapter 4

Input Central Main Output device processing unit memory device

Bus

Data flow Control

Figure 4.1 Figure 4.2

Central processing unit (CPU)

.:6# Status bits (.:6#)

Accumulator ( ! )

Index register ( 8 )

Program counter (0#)

Stack pointer (30)

Instruction register ()2) Figure 4.3

Main memory

0000 0001 0002

0003

0004 0005 0006 . . .

FFFE FFFF Figure 4.4

Main memory 0000 0003 0004 0007 000A 000B 000D ...... 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 000B 000B 1 1 0 1 0 0 0 1Figure 4.5 1 1 0 1 0 0 0 1 000C 000C 0 0 0 0 0 0 1 0 (a) The content in binary. (a) The content in binary. 000B

1 1 0 1 0 0 0 1 02 D1 02 D1 000C 000B 000C 000B 000C (a) The content in binary. (b) The content in hexadecimal. (b) The content in hexadecimal.

02 D1 000B 02D1 000B 02D1 000B 000C (c) The content in a machine (b) The content in(c) hexadecimal. The contentlanguage in a machine listing. language listing.

000B 02D1

Instruction Specifier Instruction

0000 0000 Stop execution 0000 0001 Return from trap 0000 0010 Move stack pointer (SP) to accumulator (A) 0000 0011 Move NZVC flags to accumulator (A)

0000 010a Branch unconditional 0000 011a Branch if less than or equal to 0000 100a Branch if less than 0000 101a Branch if equal to 0000 110a Branch if not equal to 0000 111a Branch if greater than or equal to 0001 000a Branch if greater than 0001 001a Branch if V 0001 010a Branch if C 0001 011a Call subroutine

0001 100r Bitwise invert register r 0001 101r Negate register r 0001 110r Arithmetic shift left register r 0001 111r Arithmetic shift right register r 0010 000r Rotate left register r 0010 001r Rotate right register r

0010 01n Unimplemented opcode, unary trap 0010 1aaa Unimplemented opcode, nonunary trap

0011 0aaa Unimplemented opcode, nonunary trap 0011 1aaa Unimplemented opcode, nonunary trap 0100 0aaa Unimplemented opcode, nonunary trap 0100 1aaa Character input 0101 0aaa Character output

0101 1nn Return from call with n local bytes

0110 0aaa Add to stack pointer (SP) 0110 1aaa Subtract from stack pointer (SP)

0111 raaa Add to register r 1000 raaa Subtract from register r 1001 raaa Bitwise AND to register r 1010 raaa Bitwise OR to register r 1011 raaa Compare register r

1100 raaa Load register r from memory 1101 raaa Load byte register r from memory 1110 raaa Store register r to memory 1111 raaa Store byte register r to memory Instruction Specifier Instruction

0000 0000 Stop execution 0000 0001 Return from trap 0000 0010 Move stack pointer (SP) to accumulator (A) 0000 0011 Move NZVC flags to accumulator (A)

0010 01n Unimplemented opcode, unary trap 0010 1aaa Unimplemented opcode, nonunary trap

0011 0aaa Unimplemented opcode, nonunary trap 0011 1aaa Unimplemented opcode, nonunary trap 0100 0aaa Unimplemented opcode, nonunary trap 0100 1aaa Character input 0101 0aaa Character output

0101 1nn Return from call with n local bytes

0110 0aaa Add to stack pointer (SP) 0110 1aaa Subtract from stack pointer (SP)

0111 raaa Add to register r 1000 raaa Subtract from register r 1001 raaa Bitwise AND to register r 1010 raaa Bitwise OR to register r 1011 raaa Compare register r

1100 raaa Load register r from memory 1101 raaa Load byte register r from memory 1110 raaa Store register r to memory 1111 raaa Store byte register r to memory Instruction Specifier Instruction

0000 0000 Stop execution 0000 0001 Return from trap 0000 0010 Move stack pointer (SP) to accumulator (A) 0000 0011 Move NZVC flags to accumulator (A)

0010 01n Unimplemented opcode, unary trap 0010 1aaa Unimplemented opcode, nonunary trap

0011 0aaa Unimplemented opcode, nonunary trap 0011 1aaa Unimplemented opcode, nonunary trap 0100 0aaa Unimplemented opcode, nonunary trap 0100 1aaa Character input Figure 4.6 0101 0aaa Character output (Continued)

0101 1nn Return from call with n local bytes

0110 0aaa Add to stack pointer (SP) 0110 1aaa Subtract from stack pointer (SP)

0111 raaa Add to register r 1000 raaa Subtract from register r 1001 raaa Bitwise AND to register r 1010 raaa Bitwise OR to register r 1011 raaa Compare register r

1100 raaa Load register r from memory 1101 raaa Load byte register r from memory 1110 raaa Store register r to memory 1111 raaa Store byte register r to memory Figure 4.7

Instruction specifier

Operand specifier

(a) The two parts of a nonunary instruction

Instruction specifier

(b) A unary instruction

Figure 4.7 Figure 4.8

aaa Addressing mode a Addressing mode r Register

000 Immediate 0 Immediate 0 Accumulator, A 001 Direct 1 Indexed 1 Index register, X 010 Indirect 011 Stack-relative (b) The addressing-a field. (c) The register-r field. 100 Stack-relative deferred 101 Indexed 110 Stack-indexed 111 Stack-indexed deferred

(a) The addressing-aaa field.

Figure 4.8 Figure 4.8 (Continued)

aaa Addressing mode a Addressing mode r Register

(a) The addressing-aaa field.

Figure 4.8 Figure 4.9

Main memory

10001101 00000011 010011 10 01A3 01A4 01A5

00011 1 10 01A6

Figure 4.9 The stop instruction • Instruction speciﬁer: 0000 0000 • Causes the computer to stop The load instruction • Instruction speciﬁer: 1100 raaa • Loads one word (two bytes) from memory to register r

r Oprnd ; N r < 0 , Z r = 0 ← ← ← Figure 4.10, 4.11

Instruction specifier Operand specifier Opcode r aaa 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 C 1 0 0 4 A

CPU Mem CPU Mem

NZ 92EF C1004A NZ 10 92EF 004A Load accumulator 004A A 036D A 92EF

Figure 4.10

(a) Before (b) After

Figure 4.11 The store instruction • Instruction speciﬁer: 1110 raaa • Stores one word (two bytes) from register r to memory

Oprnd r ← Figure 4.12, 4.13

Instruction specifier Operand specifier Opcode r aaa 1 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 E 9 0 0 4 A

CPU Mem CPU Mem

X 16BC F082 E9004A X 16BC 16BC 004A Store index register 004A

Figure 4.12 (a) Before (b) After

Figure 4.13 The add instruction • Instruction speciﬁer: 0111 raaa • Adds one word (two bytes) from memory to register r r r + Oprnd ; N r < 0 , Z r = 0 , ← ← ← V overﬂow , C carry ←{ } ←{ } Figure 4.14, 4.15

Instruction specifier Operand specifier Opcode r aaa 0 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 7 9 0 0 4 A

CPU Mem CPU Mem

NZVC FFF9 79004A NZVC 1000 FFF9 004A Add index register 004A X 0005 X FFFE

Figure 4.14

(a) Before (b) After

Figure 4.15 The subtract instruction • Instruction speciﬁer: 1000 raaa • Subtracts one word (two bytes) from memory from register r r r Oprnd ; N r < 0 , Z r = 0 , ← − ← ← V overﬂow , C carry ←{ } ←{ } Figure 4.16, 4.17

Instruction specifier Operand specifier Opcode r aaa 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 8 1 0 0 4 A

CPU Mem CPU Mem

NZVC 0009 81004A NZVC 1000 0009 004A Subtract accumulator 004A A 0003 A FFF4FFFA

Figure 4.16

(a) Before (b) After

Figure 4.17 The and instruction • Instruction speciﬁer: 1001 raaa • ANDs one word (two bytes) from memory to register r r r Oprnd ; N r < 0 , Z r = 0 ← ∧ ← ← Figure 4.18, 4.19

Instruction specifier Operand specifier Opcode r aaa 1 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 9 9 0 0 4 A

CPU Mem CPU Mem

NZ 00FF 99004A NZ 00 00FF 004A AddAnd index register 004A X 5DC3 X 00C3

Figure 4.18

(a) Before (b) After The or instruction • Instruction speciﬁer: 1010 raaa • ORs one word (two bytes) from memory to register r r r Oprnd ; N r < 0 , Z r = 0 ← ∨ ← ← Figure 4.20

CPU Mem CPU Mem

NZ 00FF A9004A NZ 00 00FF 004A Or index register 004A X 5DC3 X 5DFF

(a) Before (b) After

Figure 4.20 The not instruction • Instruction speciﬁer: 0001 100r • Bit-wise NOT operation on register r • Each 0 changed to 1, each 1 changed to 0

r r ; N r < 0 , Z r = 0 ←¬ ← ← Figure 4.21, 4.22

Instruction specifier Opcode r 0 0 0 1 1 0 0 0 1 8

CPU CPU

NZ 18 NZ 10 Not accumulator AX 0003 XA FFFC

(a) Before (b) After Figure 4.21

Figure 4.22 The negate instruction • Instruction speciﬁer: 0001 101r • Negate (take two’s complement of) register r

r r ; N r < 0 , Z r = 0 ←− ← ← Figure 4.23

CPU CPU

NZ 1A NZ 10 Negate accumulator AX 0003 AX FFFD

(a) Before (b) After

Figure 4.23 The load byte instruction • Instruction speciﬁer: 1101 raaa • Loads one byte from memory to the right half of register r r 8..15 byte Oprnd ; N r < 0 , Z r = 0 ! "← ← ← Figure 4.24, 4.25

Instruction specifier Operand specifier Opcode r aaa 1 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 D 1 0 0 4 A

CPU Mem CPU Mem

NZ 92 D1004A NZ 00 92 004A Load byte 004A A 036D accumulator A 0392

Figure 4.24

(a) Before (b) After

Figure 4.25 The store byte instruction • Instruction speciﬁer: 1111 raaa • Stores one byte from the right half of register r to memory

byte Oprnd r 8..15 ← " # Figure 4.26

CPU Mem CPU Mem F1004A XA 036D 92 Store byte A 036D 6D 004A accumulator 004A

(a) Before (b) After

Figure 4.26 The character input instruction • Instruction speciﬁer: 0100 1aaa • Stores one ASCII byte from the input device to memory

byte Oprnd character input ←{ } Figure 4.27, 4.28

Instruction specifier Operand specifier Opcode aaa 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 4 9 0 0 4 A

Input CPU Mem Input CPU Mem

W 92 49004A W 57 004A Character input 004A

Figure 4.27 (a) Before (b) After

Figure 4.28 The character output instruction • Instruction speciﬁer: 0101 0aaa • Sends one ASCII byte from memory to the output device

character output byte Oprnd { }← Figure 4.29

CPU Mem Output CPU Mem Output

48 51004A 48 H Character output 004A 004A

(a) Before (b) After The von Neumann execution cycle • Fetch instruction from Mem[PC] • Decode the instruction fetched • Increment PC • Execute the instruction fetched • Repeat Figure 4.30

Load the machine language program Initialize PC and SP do { Fetch the next instruction Decode the instruction speciﬁer Increment PC Execute the instruction fetched } while (the stop instruction does not execute) Figure 4.31

Load the machine language program into memory starting at address 0000 PC ← 0000 SP ← Mem[FFF8] do { Fetch the instruction specifier at address in PC PC ← PC + 1 Decode the instruction specifier if (the instruction is not unary) { Fetch the operand specifier at address in PC PC ← PC + 2 } Execute the instruction fetched } while ((the stop instruction does not execute) && (the instruction is legal)) Figure 4.32

Address Machine Language (bin) 0000 0101 0001 0000 0000 0000 0111 0003 0101 0001 0000 0000 0000 1000 0006 0000 0000 0007 0100 1000 0008 0110 1001

Address Machine Language (hex) 0000 510007 ;Character output 0003 510008 ;Character output 0006 00 ;Stop 0007 48 ;ASCII H character 0008 69 ;ASCII i character

Output Hi Figure 4.33

Mem Mem 0000 ?????? 0000 510007 CPU 0003 ?????? CPU 0003 510008 0006 ?? 0006 00 PC ???? Output PC ???? Output 0007 ?? 0007 48 IR ?????? IR ?????? 0008 ?? 0008 69

(a) Initial state before loading. (b) Program loaded into main memory.

Mem Mem 0000 510007 0000 510007 CPU 0003 510008 CPU 0003 510008 0006 00 0006 00 PC 0000 Output PC 0000 Output 0007 48 0007 48 IR ?????? IR 510007 0008 69 0008 69

Mem Mem 0000 510007 0000 510007 CPU 0003 510008 CPU 0003 510008 0006 00 0006 00 PC 0003 Output PC 0003 Output 0007 48 0007 48 IR 510007 IR 510007 0008 69 0008 69 (

(e) Increment 0#. (f) Execute. Character ( sent to output device. Mem Mem 0000 ?????? 0000 510007 CPU 0003 ?????? CPU 0003 510008 0006 ?? 0006 00 PC ???? Output PC ???? Output 0007 ?? 0007 48 IR ?????? IR ?????? 0008 ?? 0008 69

(a) Initial state before loading. (b) Program loaded into main memory.

Mem Mem 0000 510007 0000 510007 CPU 0003 510008 CPU 0003 510008 0006 00 0006 00 PC 0000 Output PC 0000 Output 0007 48 0007 48 IR ?????? IR 510007 0008 69 0008 69

Figure 4.33 (c) 0# 0000(hex) (d) Fetch (Continued)

Mem Mem 0000 510007 0000 510007 CPU 0003 510008 CPU 0003 510008 0006 00 0006 00 PC 0003 Output PC 0003 Output 0007 48 0007 48 IR 510007 IR 510007 0008 69 0008 69 (

(e) Increment 0#. (f) Execute. Character ( sent to output device.

Mem Mem 0000 510007 0000 510007 CPU 0003 510008 CPU 0003 510008 0006 00 0006 00 PC 0003 Output PC 0006 Output 0007 48 0007 48 IR 510008 IR 510008 0008 69 0008 69

(g) Fetch. (h) Increment 0#.

Mem Mem 0000 510007 0000 510007 CPU 0003 510008 CPU 0003 510008 0006 00 0006 00 PC 0006 Output PC 0006 Output 0007 48 0007 48 IR 510008 IR 00???? 0008 69 I 0008 69

(i) Execute. Character I sent to output device. (j) Fetch

Mem Mem 0000 510007 0000 510007 CPU 0003 510008 CPU 0003 510008 0006 00 0006 00 PC 0007 Output PC 0007 Output 0007 48 0007 48 IR 00???? IR 00???? 0008 69 0008 69

(k) Increment PC. (l) Execute. The computer halts. Mem Mem 0000 510007 0000 510007 CPU 0003 510008 CPU 0003 510008 0006 00 0006 00 PC 0003 Output PC 0006 Output 0007 48 0007 48 IR 510008 IR 510008 0008 69 0008 69

Figure 4.33 (g) Fetch. (h) Increment (Continued)0#.

Mem Mem 0000 510007 0000 510007 CPU 0003 510008 CPU 0003 510008 0006 00 0006 00 PC 0006 Output PC 0006 Output 0007 48 0007 48 IR 510008 IR 00???? 0008 69 I 0008 69

(i) Execute. Character I sent to output device. (j) Fetch

Mem Mem 0000 510007 0000 510007 CPU 0003 510008 CPU 0003 510008 0006 00 0006 00 PC 0007 Output PC 0007 Output 0007 48 0007 48 IR 00???? IR 00???? 0008 69 0008 69

(k) Increment PC. (l) Execute. The computer halts. Figure 4.34

Address Machine Language (bin) 0000 0100 1001 0000 0000 0000 1101 0003 0100 1001 0000 0000 0000 1110 0006 0101 0001 0000 0000 0000 1110 0009 0101 0001 0000 0000 0000 1101 000C 0000 0000

Address Machine Language (hex) 0000 49000D ;Character input 0003 49000E ;Character input 0006 51000E ;Character output 0009 51000D ;Character output 000C 00 ;Stop

Input up

Output pu Figure 4.35

Address Machine Language (bin) 0000 1100 0001 0000 0000 0001 0001 0003 0111 0001 0000 0000 0001 0011 0006 1010 0001 0000 0000 0001 0101 0009 1111 0001 0000 0000 0001 0000 000C 0101 0001 0000 0000 0001 0000 000F 0000 0000 0010 0000 0000 0011 0000 0000 0000 0101 0013 0000 0000 0000 0011 0015 0000 0000 0011 0000

Address Machine Language (hex) 0000 C10011 ;A := first number 0003 710013 ;Add the two numbers 0006 A10015 ;Convert sum to character 0009 F10010 ;Store the character 000C 510010 ;Output the character 000F 00 ;Stop 0010 00 ;Character to output 0011 0005 ;Decimal 5 0013 0003 ;Decimal 3 0015 0030 ;Mask for ASCII char

Output 8 Figure 4.36

Address Machine Language (bin) 0000 1101 0001 0000 0000 0001 1101 0003 1111 0001 0000 0000 0000 1001 0006 1100 0001 0000 0000 0001 0111 0009 0111 0001 0000 0000 0001 1001 000C 1010 0001 0000 0000 0001 1011 000F 1111 0001 0000 0000 0001 0110 0012 0101 0001 0000 0000 0001 0110 0015 0000 0000 0016 0000 0000 0017 0000 0000 0000 0101 0019 0000 0000 0000 0011 001B 0000 0000 0011 0000 001D 1000 0001 Figure 4.36 (Continued)

Address Machine Language (hex) 0000 D1001D ;Load byte accumulator 0003 F10009 ;Store byte accumulator 0006 C10017 ;A := first number 0009 710019 ;Add the two numbers 000C A1001B ;Convert sum to character 000F F10016 ;Store the character 0012 510016 ;Output the character 0015 00 ;Stop 0016 00 ;Character to output 0017 0005 ;Decimal 5 0019 0003 ;Decimal 3 001B 0030 ;Mask for ASCII char 001D 81 ;Byte to modify instruction

Output 2 Figure 4.37

Mem 0000 Application program

FBCE FBCF Operating system

FFFF Memory devices • Read/Write memory ‣ Also called Random-Access Memory (RAM) ‣ Can load from RAM and store to RAM • Read-Only memory (ROM) ‣ Can load from ROM ‣ Cannot store to ROM • RAM and ROM are both random Figure 4.38

Mem 0000 Application program

FBCE RAM FBCF Operating system RAM FC56 FC57 Operating ROM system ROM

FFFF Figure 4.39

Mem 0000 Applications program

User stack

FBCF System stack

FC4F I/O buffer

FC57 Loader

FC9B Trap handler

FFF8 FBCF FFFA FC4F FFFC FC57 FFFE FC9B The load option • SP ← Mem[FFFA] • PC ← Mem[FFFC] • Start the von Neumann cycle CPU CPU Mem SP ???? FFFA 7C4F Mem PC ???? SP ???? FFFC 7C57 FFFA 7C4F PC ???? FFFC 7C57

(a) Initial state. (a) Initial state. Figure 4.40

CPU CPU CPU Mem SP FC4F Mem FFFA FC4F Mem SP ???? PC ???? SP FC4F FFFA 7C4F FFFC FC57 FFFA FC4F PC ???? PC ???? FFFC 7C57 FFFC FC57

(b) SP Mem[FFFA] (a) Initial state. (b) SP Mem[FFFA]

CPU CPU CPU Mem SP FC4F Mem FFFA FC4F Mem SP FC4F PC FC57 SP FC4F FFFA FC4F FFFC FC57 FFFA FC4F PC ???? PC FC57 FFFC FC57 FFFC FC57

CPU Mem SP FC4F FFFA FC4F PC FC57 FFFC FC57