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Gate Signal Jitter Elimination and Noise Shaping Modulation for High-SNR Class-D Power Amplifiers

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Gate Signal Jitter Elimination and Noise Shaping Modulation for High-SNR Class-D Power Amplifiers © 2016 IEEE Proceedings of the 31st Applied Power Electronics Conference and Exposition (APEC 2016), Long Beach, CA, USA, March 20-24, 2016 Gate Signal Jitter Elimination and Noise Shaping Modulation for High-SNR Class-D Power Amplifiers M. Mauerer A. Tüysüz J. W. Kolar This material is published in order to provide access to research results of the Power Electronic Systems Laboratory / D-ITET / ETH Zurich. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the copyright holder. By choosing to view this document, you agree to all provisions of the copyright laws protecting it. Gate Signal Jitter Elimination and Noise Shaping Modulation for High-SNR Class-D Power Amplifiers M. Mauerer, A. Tüysüz and J. W. Kolar Power Electronic Systems Laboratory, ETH Zürich, Switzerland Email: [email protected] Abstract—Two important aspects of switched-mode (Class-D) Digital control of such amplifiers is desired for the reasons amplifiers providing a high signal to noise ratio (SNR) for of development and maintainability. Accordingly, this paper mechatronic applications are investigated. Signal jitter is common deals with two main aspects that are required to enable digitally in digital systems and introduces noise, leading to a deterioration of the SNR. Hence, a jitter elimination technique for the transistor controlled low-noise power amplifiers: jitter, which deteriorates gate signals in power electronic converters is presented and the achievable SNR, and digital modulators, which, although verified. Jitter is reduced tenfold as compared to traditional operating with a coarse duty cycle resolution in order to achieve approaches to values of 25 ps at the output of the power stage. a given PWM switching frequency, are still capable of creating Additionally, digital modulators used for the generation of the gate signals with a high SNR. switch control signals can only achieve a limited resolution (and hence, limited SNR) due to timing constraints in digital circuits. The SNR relates the power of a desired signal p(s1) to the Consequently, a specialized modulator structure based on noise power of unwanted signals p(n), such as noise, in a given fre- shaping is presented and optimized which enables the creation quency range. The desired signal can be, e.g., the fundamental of high-resolution switch control signals. This, together with the frequency component of an amplifier output voltage- or current jitter reduction circuit, enables half-bridge output voltage SNR values of more than 100 dB in an open-loop system. signal, which can also contain low-order harmonics and noise. Fig. 1 exemplarily illustrates the spectrum of a periodic signal I. INTRODUCTION that contains the desired fundamental with amplitude s1, some integer harmonics sx, and wideband noise. The signal’s SNR Low-noise switched-mode amplifiers are required in different is defined as: industry applications, amongst them integrated circuit man- ufacturing, where such amplifiers are used to drive various kinds of actuators of high-precision motion systems [1]. These p(s1) SNR = 10 log10 ; (1) systems have to provide positioning accuracies in the nanometer p(n)js2;s3;sx=0 range, which requires the amplifiers to provide output currents of extremely low noise and high precision in order to avoid where the noise power p(n) is calculated in a given frequency disturbing forces or torques in the actuators. It is estimated range [fa : : : fb] and the harmonics are excluded from the noise that the output current signal to noise ratio (SNR) of the power power calculation. If they were included, the figure would be 20 dB amplifiers needs to increase by approximately every called signal to noise and distortion ratio (SINAD) [4]. This five years in order to keep track with the industry’s growing work uses the SNR, as the investigated processes (jitter and 110 dB requirements [2]. Therefore, a current SNR in excess of PWM) cause few harmonics (if at all) of negligible power. The is desired. State-of-the-art systems usually achieve SNR values Fast Fourier Transform can be used to obtain the signal and 80 − 100 dB in the range of [2], [3]. noise powers from simulations or measurements [5], [6]. A Although mechatronic amplifiers need to provide output cur- Fundamental rents of high SNR to create low-noise torques in the actuators, s1 Harmonics this work analyzes the SNR of the switching stage’s output s3 voltage in order to present a concise analysis of distortion s2 Noise and noise originating from the fundamental building blocks of 0 the power converter, as a distorted voltage finally translates to 0 f f f f 1 2 3 current distortion in filter inductors or actuators. Fig. 1: Discrete amplitude spectrum of a noisy, periodic signal. The Section II presents sources of jitter in power electronic signal to noise ratio (SNR) relates the fundamental power p(s1) to the noise power p(n) in a certain frequency range. converters and proposes a simple new circuit for generating isolated, low-jitter gate signals. The circuit is also immune to As the amplifiers target mechatronic applications, their out- fast common-mode voltage transients across the isolation bar- put must be of low noise and high precision only in a limited rier and its functionality is experimentally verified. Section III frequency range from DC to ≈10 kHz, as the mechanical details advanced modulation structures which outperform con- systems provide sufficient damping at higher frequencies and ventional pulse-width modulators. Their performance is also are thus less sensitive to high-frequency signal distortion or demonstrated with a prototype system. Finally, Section IV noise in the actuator’s currents. summarizes the achieved results and presents an outlook. 978-1-4673-9550-2/16/$31.00 ©2016 IEEE 1198 II. SIGNAL JITTER AND ITS ELIMINATION IN A GATE circuits. Both drivers require an isolated supply and an isolated DRIVER CIRCUIT gate control signal path in order to allow any control system reference potential between the potentials U , U of the Electrical signal jitter has various classifications and, due to POS NEG DC link rails. its often stochastic nature, can be modeled like noise [7]. Fig. 2 shows a periodic digital signal with jitter, which expresses Signal UPOS itself as the time-dependent deviations ∆ti of the signal’s edge Isolator GISO T1 positions from their ideal positions [8]. uG y(t) T G Isolated uOut sig Actual Transitions Supply i t o i Gate Drivers t CLK T2 Ideal Transition Times ti Fig. 2: A digital, periodic signal y(t) shows jitter if its edges occur U Clock NEG at time instants different from the ideal transition times. The time Oscillator difference ∆ti between actual and ideal edge is often of stochastic nature. Fig. 4: Conventional half-bridge topology with two power transistors, In digital signals, where information is encoded in the time their isolated gate drivers and a digital gate signal generator. instants of its edges, jitter alters the information and introduces wideband noise [4]. For high-precision PWM applications with Every functional element in the gate signal path is a potential targeted SNRs in excess of 100 dB and pulse frequencies source of jitter. In this regard, the clock oscillators of digital signal processors (DSPs) or field programmable gate arrays fPWM = 1=TPWM in the range of 50 ::: 200 kHz, even jitter (FPGAs), both being widely used to generate the gate control figures (∆ti) in the picosecond range can introduce significant noise and limit the SNR as the equation from [9] shows: signals, as well as the signal routing in an FPGA, add jitter. However, the most prominent jitter source is the signal isolator, s ! m TPWM which is commonly realized using optocouplers or non-optical SNRmax = 20 log10 p (2) digital signal isolators1. 4 2 · TJit;RMS fBW Fig. 3 illustrates eq. (2) for different pulse frequencies fPWM. B. Gate Driver with Reduced Jitter The bandwidth fBW in which the noise power is assessed is 10 kHz (cf. eq. (1)) and the modulation index m of the Existing jitter minimization techniques reduce the jitter of PWM modulator approaches 1 (0 ≤ m ≤ 1). TJit;RMS is a (periodic) clock signal with phase locked loops (PLL) or the RMS jitter and denotes the stationary RMS value of the filters, and are usually applied in low-power digital-to-analog time deviations ∆ti. As these deviations follow a stochastic converters [11]. This work proposes the circuit depicted in distribution, a sufficient amount of samples, depending on the Fig. 5 to reduce the jitter of the (potentially non-periodic) gate underlying stochastic process, must be considered in order to control signals which includes a basic concept proposed in [12], correctly calculate their RMS value. but extends it by a system that renders the gate drivers immune to fast output voltage transients, i.e., it prevents faulty switching 125.0 actions of the power transistors in case the signal isolator emits 120.0 erroneous signals during short output voltage transients of high 115.0 du=dt. 110.0 10 kHz (dB) 105.0 D-Flip-Flop UPOS max 100.0 50 kHz G GISO D T 95.0 100 kHz Q 1 BLK CE SNR 200 kHz GFF uG 90.0 500 kHz CLKφ 85.0 Driver IC uOut CLK 80.0 CLK ISO io 0 25 50 75 100 125 150 175 200 225 250 Low-Jitter TJit,RMS (ps) Clock Isolator Low-Jitter Fig. 3: Plots of eq. (2): Maximum achievable SNR for a given PWM Clock Oscillator frequency in dependence of the RMS jitter.
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