Analysis and Modeling of Non-idealities in VCO-Based Quantizers Using Frequency-to- Digital and Time-to-Digital Converters
THESIS
Presented in Partial Fulfillment of the Requirements for the Degree Master of Science in the Graduate School of The Ohio State University
By
Samantha M. Yoder
Graduate Program in Electrical and Computer Science
The Ohio State University
2010
Master's Examination Committee:
Mohammed Ismail, Advisor
Waleed Khalil
Steven Bibyk
Copyright by
Samantha M. Yoder
2010
ABSTRACT
Traditional ADCs (analog-to-digital converters) are built using analog circuitry that quantize the input signal in the voltage domain. As technology scales, voltage dynamic range decreases and design difficulties for analog circuits arise. Alternatively, time resolution is improving as technology scales. VCO (voltage controlled oscillator)-based quantizers (Figure i) are highly digital circuits which quantize in the time domain rather than in the voltage domain, and thus are becoming more attractive in deeply scaled technologies. The VCO converts an analog voltage into timing information that can then be quantized using digital circuitry.
Analog Voltage-to- Digital
x(t) y(n) Traditional ADC
VCO-based Voltage-to- ADC Time Time y(n) x(t) Digitization
Figure i: Traditional ADC block diagram vs. VCO-based ADC block diagram
ii
Early work has used a simple digital counter to quantize the VCO signal. However issues with the counter “missing” VCO transitions near the sampling clock edge have led to the use of an FDC (frequency-to-digital converter) as the quantization circuit. The FDC has been widely adopted due to its inherent first order noise shaping characteristic. Another digital time quantization using TDCs (time-to-digital converters) have been traditionally used in PLLs to quantize the VCO phase error but have not been applied to VCO-based
ADCs.
In this document, we propose for the first time the use of a TDC for time quantization in the VCO-based ADC. Both methods of using the TDC and the FDC are compared, Figure ii. While The SNR of the VCO-based quantizer using either the FDC or TDC is dependent on some common parameters such as VCO tuning range, Kv, x(t), and OSR
(oversampling ratio), the TDC has two additional influences on the SNR; namely the
VCO center frequency, fc, and buffer delay of the delay chain.
Measure FDC Frequency
x(t) v(t)=sin(2p ∫ [fc+Kvx(t)] dt)
Measure Period TDC
Figure ii: Time digitization, FDC vs. TDC
iii
Both TDC and FDC based quantizers were examined in the presence of VCO nonlinearity, VCO phase noise, and sampling clock jitter, Figure iii. The comparison involves using the same baseline VCO and sampling clock. Modeling and analysis of the
VCO-based quantizer and theoretical SNR calculations of the ideal VCO-based quantizers with and without non-idealities are presented.
Phase Noise ) B d (
t q S
foffset (Hz)
Kv D S
x(t)=Amsin(2pfmt) FDC/ P TDC
Jittery Clock fm 2fm3fm nfm f (Hz) D S P
fs f (Hz)
Figure iii: VCO nonlinearity, phase noise and clock jitter
The model results show that both FDC and TDC are impacted similarly when VCO nonlinearity and phase noise are introduced. However, when sampling clock jitter is introduced the FDCs SNR degrades significantly compared to the TDC. This can be attributed to the FDC losing its first order noise shaping response, Figure iv.
iv
FDC Ideal, FDC w/ Nonlinear Kv, FDC w/ Phase Noise, FDC w/ Clock Jitter, SNR= 60 dB SNR= 24 dB SNR= 59 dB SNR= 48 dB
0 0 0 0
-20 -20 -20 -20
-40 -40 -40 -40
-60 -60 -60 -60
-80 -80 -80 -80
-100 -100 -100 -100
-120 -120 -120 -120
-140 -140 -140 -140
-160 -160 -160 -160
-180 -180 -180 -180
-200 -200 -1 0 1 2 -1 0 1 2 -200 10 10 10 10 10 10 10 10 -200 -1 0 1 2 -1 0 1 2 10 10 10 10 10 10 10 10 TDC ideal, TDC w/ Nonlinear Kv, TDC w/ Phase Noise, TDC w/ Clock Jitter, SNR= 60 dB SNR= 24 dB SNR= 59 dB SNR= 60 dB
0 0 0 0
-20 -20 -20 -20
-40 -40 -40 -40
-60 -60 -60 -60
-80 -80 -80 -80
-100 -100 -100 -100 -120 -120 -120 -120 -140 -1 0 1 2 -140 10 10 10 10 -1 0 1 2 -140 10 10 10 10 -1 0 1 2 10 10 10 10 -140 -1 0 1 2 10 10 10 10 Figure iv: FDC vs. TDC PSD: Ideal, Nonlinear, Phase Noise, Clock Jitter
In summary this work presents an alternative method to using an FDC in a VCO-based quantizer which can achieve the same SNR performance with less sensitivity to sampling clock jitter.
v
DEDICATION
I dedicate this document to the love of my life, Christopher McDonnell
vi
ACKNOWLEDGMENTS
I would like to make a sincere thank you to the following individuals:
Professor Ismail who inspired me to study the subject of electrical engineering. His continued support and encouragement led me to the Master’s degree program in electrical engineering. Without his guidance, support, and encouragement this document would not have been possible.
Professor Khalil who advised me to study the topic of my thesis. This document would not have been possible without his knowledge, advice, and suggestions which have been an invaluable help throughout my Masters degree. His encouragement and support has led me to continue to the PhD program in electrical engineering.
vii
VITA
June 2004 ...... Strongsville High School
December 2008 ...... B.S. Electrical and Computer Engineering,
The Ohio State University
September 2010 ...... M.S. Electrical and Computer Engineering,
The Ohio State University
PUBLICATION
Hu, John; Haffner, Mark; Yoder, Samantha; Reehal, Gursharan; Scott, Mark;
Ismail, Mohammed; , "An industry-driven laboratory development for mixed-
signal IC test education," Circuits and Systems (ISCAS), Proceedings of 2010
IEEE International Symposium on , vol., no., pp.85-88, May 30 2010-June 2 2010
FIELD OF STUDY
Major Field: Electrical and Computer Engineering
viii
TABLE OF CONTENTS
ABSTRACT ...... ii
DEDICATION ...... vi
ACKNOWLEDGMENTS ...... vii
VITA ...... viii
PUBLICATION ...... viii
FIELD OF STUDY ...... viii
TABLE OF CONTENTS ...... ix
LIST OF TABLES ...... xii
LIST OF FIGURES ...... xiii
LIST OF ABBREVIATIONS ...... xvi
LIST OF SYMBOLS ...... xvii
CHAPTER 1: Introduction ...... 1
1.1 Background ...... 2
1.2 Motivation ...... 2
ix
1.3 Overview of Work ...... 4
CHAPTER 2: VCO-Based Quantizers ...... 6
2.1 VCO Operation ...... 6
2.2 FDC VCO-Based Quantizer ...... 9
2.2.1 Linear Modeling and Analysis ...... 12
2.2.2 Verification ...... 18
2.3 TDC VCO-Based Quantizer...... 21
2.3.1 Linear Modeling and Analysis ...... 25
2.3.2 Verification ...... 31
2.4 Discussion ...... 34
CHAPTER 3: Limitations of the VCO Based Quantizer ...... 35
3.1 VCO Nonlinearity ...... 35
3.1.1 Modeling and Analysis ...... 36
3.1.2 Verification ...... 39
3.2 VCO Phase Noise ...... 41
3.2.1 Modeling and Analysis ...... 42
3.2.2 Verification ...... 49
3.3 Sampling Clock Jitter ...... 52
3.3.1 Modeling and Analysis ...... 52
x
3.3.2 Verification ...... 54
3.4 Discussion ...... 56
CHAPTER 4: Conclusion and Future Work ...... 58
4.1 FDC/ TDC Tradeoffs ...... 58
4.2 Two-Tone Test ...... 60
4.3 Future Work ...... 62
xi
LIST OF TABLES
Table 2.1: FDC VCO-based quantizer design parameters ...... 18
Table 2.2: FDC VCO-based quantizer simulation parameters ...... 19
Table 2.3: TDC VCO-based quantizer design parameters...... 31
Table 2.4: TDC VCO-based quantizer simulation parameters ...... 32
Table 2.5: FDC VCO-based quantizer vs. TDC VCO-based quantizer ...... 34
Table 3.1: Effects of nonidealities on SNR FDC vs. TDC VCO-based Quantizer ...... 57
Table 4.1: FDC/TDC Circuit Restrictions ...... 59
xii
LIST OF FIGURES
Figure i: Traditional ADC block diagram vs. VCO-based ADC block diagram ...... ii
Figure ii: Time digitization, FDC vs. TDC ...... iii
Figure iii: VCO nonlinearity, phase noise and clock jitter ...... iv
Figure iv: FDC vs. TDC PSD: Ideal, Nonlinear, Phase Noise, Clock Jitter ...... v
Figure 1.1: Block diagram (a) Typical Quantizer (b) VCO-based Quantizer...... 1
Figure 1.2: Flash ADC ...... 3
Figure 1.3: Pipeline ADC ...... 3
Figure 1.4: ADC ...... 4
Figure 2.1: VCO block diagram...... 6
Figure 2.2: Buffered VCO output vs. VCO input signal ...... 7
Figure 2.3: PSD VCO output ...... 8
Figure 2.4: VCO-based quantizer ...... 8
Figure 2.5: VCO-based quantizer FDC vs. TDC ...... 9
Figure 2.6: FDC block diagram ...... 9
Figure 2.7: FDC example waveforms ...... 10
Figure 2.8: Multi-bit FDC VCO-based quantizer block diagram ...... 11
Figure 2.9: Single-bit and multi-bit FDC VCO-based quantizer output vs. input signal . 12 xiii
Figure 2.10: Quantization of the FDC input: VCO phase ...... 13
Figure 2.11: VerilogA code: FDC VCO-based quantizer ...... 17
Figure 2.12: FDC VCO-based quantizer test bench ...... 19
Figure 2.13: FDC VCO-based quantizer input vs. output (time domain) ...... 20
Figure 2.14: PSD FDC VCO-based quantizer output ...... 21
Figure 2.15: TDC Block diagram ...... 22
Figure 2.16: TDC example waveform ...... 23
Figure 2.17: Cascaded TDC block diagram ...... 24
Figure 2.18: Single and multiple TDC VCO-based quantizer output vs. input signal ..... 24
Figure 2.19: Quantization of the TDC input: VCO period ...... 25
Figure 2.20: VerilogA code: TDC VCO-based quantizer ...... 29
Figure 2.21: TDC VCO-based quantizer test bench ...... 32
Figure 2.22: TDC VCO-based quantizer input vs. output (time domain) ...... 33
Figure 2.23: PSD TDC VCO-based quantizer output ...... 33
Figure 3.1: VCO nonlinearity in the output spectrum of the VCO-based quantizer ...... 36
Figure 3.2: VCO tuning curve ...... 36
Figure 3.3: VerilogA code nonlinear VCO ...... 37
Figure 3.4: PSD nonlinear FDC VCO-based quantizer output ...... 40
Figure 3.5: PSD nonlinear TDC VCO-based quantizer output...... 41
Figure 3.6: VCO phase noise block diagram ...... 42
Figure 3.7: Simulated VCO phase noise ...... 43
Figure 3.8: Modeling 1/f2 VCO phase noise as jitter ...... 43
xiv
Figure 3.9: VCO phase noise: VerilogA model vs. Simulated ...... 44
Figure 3.10: 1/f3 VCO phase noise block diagram ...... 45
Figure 3.11: Simulated phase noise transfer function ...... 46
Figure 3.12: Jitter filter H(f) ...... 47
Figure 3.13: VerilogA jitter filter...... 47
Figure 3.14: VCO phase noise: VerilogA+Jitter Filter model vs. Simulated ...... 48
Figure 3.15: PSD FDC VCO-based quantizer with phase noise ...... 50
Figure 3.16: PSD TDC VCO-based quantizer with phase noise ...... 51
Figure 3.17: Block diagram: sampling clock jittering VCO-based ADC ...... 52
Figure 3.18: PSD FDC VCO-based quantizer output with jittery clock...... 54
Figure 3.19: PSD TDC VCO-based quantizer output with jittery clock ...... 55
Figure 3.20: PSD FDC VCO-based quantizer ideal vs. non-ideal ...... 56
Figure 3.21: PSD TDC VCO-based quantizer ideal vs. non-ideal ...... 57
Figure 4.1: PSD FDC 2-tone test ...... 61
Figure 4.2: PSD TDC 2-tone test ...... 61
Figure 4.3: modulator using VCO-based quantizer ...... 62
xv
LIST OF ABBREVIATIONS
CMOS Complimentary Metal Oxide Semiconductor CT Continuos Time DFF D Flip-Flop Delta-Sigma DT Discrete Time FFT Fast Fourier Transform FDC Frequency to Digital Converter NTF Noise Transfer Function OSR Oversampling Ratio PSD Power Spectral Density SNDR Signal to Noise plus Distortion Ratio SNR Signal to Noise Ratio STF Signal Transfer Function TDC Time to Digital Converter THD Total Harmonic Distortion VCO Voltage Controlled Oscillator
xvi
LIST OF SYMBOLS
τaj Absolute Jitter
Avco Amplitude of VCO Output
Am Analog Input Signal Amplitude fm Analog Input Signal Frequency Analog Input Signal to be x(t) Quantized
τbuff Delay of Buffer ΣΔ Delta-Sigma y(n) Digital Output
FDCout(n) FDC Output
PIE Integration Error Power
VCOfmax Maximum VCO Frequency
VCOTmax Maximum VCO Period μ Mean
VCOfmin Minumum VCO Frequency
VCOTmin Minumum VCO Period
PN Noise Power N Number of Stages fobs Observation Frequency
τpj Period Jitter
PPN Phase Noise Power q(n) Quantization Error
SΔt Random jitter Power Δt Random Period Jitter fs Sampling Frequency
Ts Sampling Period xvii
σ Sigma
PS Signal Power L(f) Single Side Band Phase Noise fb System Bandwidth Frequency
TDCout(n) TDC Output fc VCO Free Running Frequency fvco VCO Frequency
VCOout VCO Output
Tvco VCO Period
θvco VCO Phase
Φvco VCO Phase Error
Kv VCO Sensitivity Factor
xviii
CHAPTER 1: INTRODUCTION
Typical ADCs convert an analog voltage to digital bits. VCO-based ADCs differ from traditional ADCs because there is an intermediate conversion to time, see Figure 1.1.
First the analog voltage is converted to time information then from time information to digital bits. This conversion process involves a VCO and time quantizer that will be examined in detail in later sections. To gain some understanding of how this process works we must know the operation of the VCO. The output frequency of the VCO is dependent on the input voltage; a larger input voltage means a higher frequency of operation and vice versa. Thus there must be some way of quantizing the VCO waveform to give a representation of the input signal to the VCO.
Voltage-to- Digital
x(t) ADC y(n) Traditional ADC
Voltage-to- VCO-Based Time ADC Time x(t) y(n) Digitization
Figure 1.1: Block diagram (a) Typical Quantizer (b) VCO-based Quantizer
1
1.1 BACKGROUND
The concept of VCO-based quantizer first showed up in literature in 1999. It consisted of a VCO and counter and was used in the modulator [1]. In 2000 the use of a frequency detector in the feedback loop of the modulator eliminated the need for the feedback
DAC [2]. In 2006 VCO-based quantizer utilized a multi-phase VCO and multiple counters to increase the resolution of the quantizer [3]. In 2007 the VCO was implemented as a fully differential structure to help improve linearity of the VCO [4]. At this time the counter was also replaced with a frequency-to-digital converter, FDC. This was due to the problem of missing a VCO count at clock edges of the counter [5].
Successful prototypes of the modulator using the FDC-VCO based ADC have been built in standard CMOS technologies [6], [7]. In 2009 this type of quantizer was used to realize a highly digital MB quantizer [8]. Recently in 2010 the VCO-based quantizer helped realize an all digital ADC, using linearization techniques and digital calibration to help linearize the ADC [9].
1.2 MOTIVATION
Consider the typical ADCs shown in Figure 1.2-1.3. Both ADCs contain many analog
circuit components. Both these ADCs quantize an analog voltage to digital bits. These
types of ADCs can be used in ADCs to help improve the resolution by using noise
shaping and oversampling, Figure 1.4. As technology scales, voltage dynamic range
decreases making it more difficult to quantize in the voltage domain. Also high gain
2 amplifiers that make up these traditional ADCs are getting difficult to design due to the degradation of transistor gDS.
Vref Vin
(2N-1) to N N digital encoder outputs
2N comparators
Figure 1.2: Flash ADC
b1
QN DN
b2
QN-1 QN-1 N-1-bit DN-2 DN-2 shift register bN-1
Q1 Q1 Q1 D1 D1 D1 bN
Vin 1-bit 1-bit 1-bit 1-bit DAPRX DAPRX DAPRX DAPRX
Analog Pipeline
Figure 1.3: Pipeline ADC
3
v(n) H(z) y(n) - Quantizer
Figure 1.4: ADC
Alternatively, time resolution is increasing as technology scales. Thus the VCO-based quantizer has been gaining popularity. It also lends itself to a highly digital implementation and processing techniques.
The VCO-based quantizer has been implemented mostly with a counter or FDC as the time quantizer. However a time-to-digital converter, TDC, may also be used. In recent papers the TDC has been used with pulse-width-modulators to form an ADC [10], [11].
Many publications have analyzed the VCO-based quantizer utilizing an FDC, but to the authors knowledge none have used a TDC. There may be advantages to using one over the other in the VCO-based quantizer. Comparison of these digitization techniques will take into account VCO nonlinearity, phase noise, and sampling clock jitter.
1.3 OVERVIEW OF WORK
Chapter 2 introduces the VCO-based quantizer. The VCO is described by an equation which converts the input to the VCO into a VCO frequency. The methods to digitize the
VCO waveform are the FDC and TDC. Chapter 2 will describe each method in detail.
4
Linear equations and the SNR of the quantization process is derived. The SNR derivation for the FDC matches what has been found in literature [12]. The TDC VCO- based quantizer SNR is derived here for the first time. These theoretical equations are verified by VerilogA simulation, and closely match the theoretical values.
Chapter 3 describes the limitations of the VCO-based quantizer in terms of VCO nonlinearity, VCO phase noise, and sampling clock jitter. The same VCO is used for both the FDC and TDC to compare the two. VCO nonlinearity is simulated by capturing the
VCO tuning curve and modeled with a 6th order polynomial. VCO phase noise is simulated and modeled using previous verilogA models [13]. However the previous models only account for 1/f2 noise and not 1/f3 noise. Therefore a filter is used in conjunction with previous models to give the correct response. Clock jitter will be modeled in the similar manner as the VCO phase noise, only taking into account 1/f2 noise. Theoretical equations are derived in the presence of these non-idealities and compared with VerilogA simulation. VCO nonlinearity is the main bottleneck to these types of quantizers.
Chapter 4 is the conclusion and future work section. In this section a final comparison of the FDC and TDC VCO-based quantizers will be made. Future work will be to place these quantizers in a modulator to help suppress nonlinearity.
5
CHAPTER 2: VCO-BASED QUANTIZERS
2.1 VCO OPERATION
A VCO converts voltage to time information, Figure 2.1. If we assume an ideal VCO we can write the output of the VCO as [14]:
Where the phase and frequency of the VCO can be written as:
Voltage-to- Time
x(t)
q (t) fvco(t) 2p VCO A sinq (t) x(t) Kv s VCO VCO
fc
Figure 2.1: VCO block diagram
6
The frequency of the VCO depends on VCO characteristics such as its free running frequency, fc, and VCO gain, Kv. The frequency of the VCO also depends on the control voltage, x(t). The control voltage along with the VCO gain determines dynamic range of the quantizer. From (2.3) we see that as the value of x(t) increases so does the VCO output frequency and vice-versa. To gain a more intuitive understanding, consider the situation where the input to the VCO is a sinusoidal wave and the output of the VCO is buffered as shown in Figure 2.2.
Buffered VCO Output vs. VCO Input 1.5 VCO Input Buffered VCO Output 1
0.5
0 Voltage (V) Voltage -0.5
-1
-1.5 0 200 400 600 800 1000 Time (s)
Figure 2.2: Buffered VCO output vs. VCO input signal
As shown in Figure 2.2 the larger the input amplitude to the VCO the faster the frequency of the VCO and vice-versa. The VCO output is also shown in the frequency domain,
Figure 2.3. The range of frequencies of the is equal to fc ± Δf, where Δf=Kvx(t). 7
PSD VCO Output 150 f c 100 f f
50
0
-50
-100 Magnitude (dB) Magnitude
-150
-200
-250 0 200 400 600 800 1000 1200 1400 1600 1800 Frequency (Hz)
Figure 2.3: PSD VCO output
Voltage-to- Time Time y(n) x(t) Digitization
Figure 2.4: VCO-based quantizer
The VCO output can be quantized using several circuits, Figure 2.4, but this document will focus on two. This will be the method of using a FDC, and a TDC, as shown in
Figure 2.5. The FDC directly measures the frequency of the VCO waveform, while the
8
TDC measures the period of the VCO waveform then inverted to get the frequency.
These methods will be discussed next.
Measure FDC Frequency
Measure Period TDC
Figure 2.5: VCO-based quantizer FDC vs. TDC
2.2 FDC VCO-BASED QUANTIZER
An FDC is a frequency-to-digital converter. The architecture of the FDC consists of 2-
DFFs and one XOR gate as shown in Figure 2.6 [15].
Q1(n) FDCout(n) FDCin(t) Q2(n) D SET Q D SET Q
CLR Q CLR Q
clock
Figure 2.6: FDC block diagram
Consider the input to the FDC to be a pulse. At the rising clock edge the output of the first DFF will take on its input value, the second DFF will take on the value of the first 9
DFF before the rising clock edge. The XOR gate will detect if there is a difference between the two DFF outputs. Thus the FDC operates as an edge detector, determining if a transition has occurred at the input.
To gain a better understanding of the FDC consider the waveforms shown in Figure 2.7.
Consider the first occurrence when the FDC input changes from a 1 to 0. At the rising clock edge after this transition the first DFF output, Q1, changes to a 0. The value of the second DFF output, Q2, takes on the value of Q1 before that rising clock edge. The XOR gate now sees Q1=0 and Q2=1 and it outputs a 1. This pattern continues throughout the waveform. We notice from the waveforms that there is some delay between the output transition and when the input transition occurs. This delay can be up to one clock period.
Edge 1 occurs FDC in 1 0 -1 0 0.5 1 1.5 Q , Q 1 2 1 0 Q -1 1
0 0.5 1 1.5 Q 2 clock 1 0 -1 0 0.5 1 1.5 FDC Edge 1 detected out 1 0 -1 0 0.5 1 1.5 Quantization error time (s)
Figure 2.7: FDC example waveforms 10
The FDC operates as an edge detector with some error in determining when a transition has occurred at the input signal. If the transitions occur faster at the input, the output of the FDC would produce more 1’s and if the transitions are slower at the FDC input, the output of the FDC would produce more 0’s. This is how the frequency of the input signal is converter to a digital bit.
Consider the FDC connected to the buffered VCO output. The VCO used here will be a ring oscillator consisting of a chain of inverters. Each output stage, or inverter, of the
VCO can be connected to an FDC, and then the FDC outputs can be combined to form a multi-bit quantizer, as shown in Figure 2.8. The VCO phase taps are delayed from one another by 2π/N, N being the number of stages. Thus there are multiple reads of the signal within a single cycle to improve the resolution. The single bit and multi-bit operation are shown in Figure 2.9.
FDC FDC1 FDC2 N
Σ
FDCout
Figure 2.8: Multi-bit FDC VCO-based quantizer block diagram
11
One Bit FDC VCO-based Quantizer
0.5
0
-0.5
0 0.2 0.4 0.6 0.8 Input Two Bit FDC VCO-based Quantizer Output
0.5
0
-0.5
0 0.2 0.4 0.6 0.8
Figure 2.9: Single-bit and multi-bit FDC VCO-based quantizer output vs. input signal
2.2.1 LINEAR MODELING AND ANALYSIS
The FDC VCO-based quantizer is modeled and analyzed using linear modeling. Figure
2.10 shows the VCO phase, FDC output, and clock. Since the VCO is modeled as an ideal sine wave, when the VCO phase accumulates π, the VCO output crosses the zero axis and the FDC output is high at the next rising clock edge.
12
Phase Quantization 2 q (n)
vco )
p q (n-1) vco (n) vco 1
Phase ( Phase (n-1) vco 0 0.45 0.5 0.55 0.6 0.65 Phase Quantization 2 FDC (n-1) FDC (n) FDC output out out 1 clock
0
0.45 0.5 0.55 0.6 0.65 Time (s)
Figure 2.10: Quantization of the FDC input: VCO phase
Using the relationships shown in Figure 2.10 the multi-bit FDC output, using “N” FDCs, can be written based on the VCO phase.
The VCO phase error is the difference between what the actual VCO phase is and when it last accumulated multiple of π. From (2.2) and the fact that integration can be written as a sum rewrite (2.4) as: 13
Using Z-transformations we can write this relationship in terms of the frequency domain
Based on (2.9) the STF and NTF for the FDC VCO-based quantizer is derived.
From the derivations, the input signal is scaled while the quantization noise is first order shaped. To derive the SNR the power of the signal and the power of the noise at the
14 output of the FDC are calculated. If the input to the VCO is a sine wave (2.12) the power of the output signal is (2.13).
The noise power is derived next. The first assumption is that the quantization noise is white. Also if “N” FDCs are used then the noise is reduced by “N” [16]. This means the level of noise is constant across all frequencies and equal to (2.14) using the 2 sided definition of power [17 pp. 532-533].
Since the noise is filtered the power of the filtered noise is derived, the NTF is given in the frequency domain as:
15
Using Euler’s formula the magnitude of the NTF assuming the sampling frequency is much greater than the bandwidth is given as:
The in band power given a bandwidth equal to is given as:
The power of the noise matches the general equation used for first order noise shaping
[17 p. 552]. The SNR is the power of the signal divided by the power of the noise.
The max SNR of the FDC VCO-based quantizer depends on the number of FDCs, the ratio of the sampling frequency to the system bandwidth, and the VCO gain factor. This
SNR value is consisted with what has previously been derived [12].
16
The complete FDC VCO-based quantizer model in VerilogA is shown below. The input to the VerilogA model is the clock signal and the input to the VCO. The model consists of the VCO with “N” phase taps, and “N” FDCs. The VCO is modeled using the ideal relationship and then buffered. At the rising clock edge each FDC operates on its own buffered VCO phase tap. The output of the model is the sum of the FDC.
// VerilogA for Sams, fdc, veriloga `include "constants.vams" `include "disciplines.vams" `define PI 3.141592653589793284686433832795028841971 module fdc(in,clk,out); input in, clk; output out; voltage in,clk,out; parameter real vdd=0.6, // Positive Supply vss=-0.6, // Negative Supply fc=500e6, // VCO center frequency Kv=250e6; // VCO gain Hz/V parameter N=5; // number of phase taps // Define variables real vout,fvco,phase, Ac, vmid; real vcout[0:N-1]; integer q1[0:N-1],q2[0:N-1]; integer i,count; analog begin // Initialized Parameters @(initial_step) begin Ac=(vdd-vss)/2.0; // VCO Amplitude vmid=(vdd+vss)/2.0; // Midrail Voltage end // VCO fvco=Kv*V(in)+fc; // VCO Frequency phase=2.0*`PI*idtmod(fvco,0,1,-0.5); // VCO Phase
// Buffer VCO Phase Taps for(i=0;i Figure 2.11: VerilogA code: FDC VCO-based quantizer 17 Figure 2.11 Continued // FDC @ (cross(V(clk)-vmid,1)) begin // At the rising clock edge count=0; for(i=0;i 2.2.2 VERIFICATION The FDC VCO-based quantizer is designed to have a desired SNR based on the derivations in the linear modeling section. The following parameters are assumed: power supply of 1.2V, system bandwidth equal to 10MHz, and sampling frequency equal to 2 GHz. The input to the VCO will be a sine wave with amplitude equal to half supply. To achieve an SNR=60dB the VCO has a center frequency of 500MHz and gain of 250MHz/V along with 5 FDC’s. These parameters are outlined in Table 2.1. The theoretical SNR for this combination is shown in (2.22). VDD-VSS 1.2 V fs 2 GHz fb 10 MHz Am 0.6 V fc 500 MHz Kv 250MHz/V N 5 Table 2.1: FDC VCO-based quantizer design parameters 18 Figure 2.12 shows the test bench used to verify the design. The FDC VCO-based quantizer is simulated using the VerilogA code and the simulation parameters shown in Table 2.2. Figure 2.12: FDC VCO-based quantizer test bench VDD 0.6 V VSS 0.6V fm 500 kHz Am 0.6 V Tstart 2μs Tstop 100μs Tsimulator 250ps Points 392000 Table 2.2: FDC VCO-based quantizer simulation parameters 19 The results are shown below, where the output of the quantizer is normalized. Since the maximum VCO frequency is less than half the sampling frequency the output does not go rail to rail, Figure 2.13. The PSD of the output is shown in Figure 2.14. The FFT of the output is hann windowed. The simulated VerilogA SNR closely matches the theoretical SNR. Next the VCO-based quantizer using the TDC method will be discussed. FDC VCO-based Quantizer 0.6 Input Output 0.4 0.2 0 Amplitude (V) Amplitude -0.2 -0.4 10 10.5 11 11.5 12 Time(sec) Figure 2.13: FDC VCO-based quantizer input vs. output (time domain) 20 PSD FDC VCO-based Quantizer Output 0 -20 f =500 kHz -40 m -60 -80 -100 Simulated VerilogA -120 SNR= 60.7852dB Amplitude (dB) Amplitude -140 -160 -180 f =10 MHz b -200 1 10 100 Frequency (MHz) Figure 2.14: PSD FDC VCO-based quantizer output 2.3 TDC VCO-BASED QUANTIZER A TDC is a time-to-digital converter. The architecture of the TDC, as shown in Figure 2.15, consists of a delay chain, several DFFs, and a digital block which function will be described shortly. Consider the input to the TDC to be a pulse. If we let the pulse propagate through the delay chain and then clock the DFF’s we a snapshot of that pulse will be shown. Then using digital logic the width of this pulse may be detected by looking at the output of each DFF. If the pulse is long the width will be larger, and vice- versa. The TDC gives a representation of the period of that pulse and can be inverted to get the frequency. 21 n delay elements TDCin(t) tbuff D SET Q D SET Q D SET Q D SET Q CLR Q CLR Q CLR Q CLR Q clock QN(n) Q1(n) Inverted Pulse Detector TDCout(n) Figure 2.15: TDC Block diagram To gain a better understanding of the TDC consider the waveforms shown in Figure 2.16. The output of the TDC, frequency output, between several input pulses each with a different frequency is shown. Increasing frequency to the TDC will result in larger output values. The accuracy of the pulse width will depend on the delay of the buffer which forms the delay chain. 22 Period 1 1 0.5 0 0 10 20 30 40 50 60 70 Period 2 1 0.5 0 TDC 0 10 20 30 40 50 60 70 in Period 3 TDC out 1 0.5 0 0 10 20 30 40 50 60 70 Period 4 1 0.5 0 0 10 20 30 40 50 60 70 time (s) Figure 2.16: TDC example waveform Like the FDC the TDC can have “N” stages cascaded together, Figure 2.17. The same delay chain can be used for each TDC, however different DFF chains and pulse width detectors are needed. The clock signal will be delayed to each TDC to cover a complete sampling cycle and the output of each TDC will be added. This is the equivelent of increasing the sampling clock by “N”. This is a slightly different approach to improve the dynamic range of the TDC than taken in [18]. 23 Delay chain clock TDCout1(n) TDC1: DFF chain + pulse detector TDCout2(n) TDC2: DFF chain + pulse detector Invert TDCoutN(n) TDCout(n) TDCN: DFF chain + pulse detector Figure 2.17: Cascaded TDC block diagram The TDC operates as a pulse width detector which can be inverted to represent the frequency of its input. Now consider the TDC connected to the buffered VCO output. A single TDC and multiple TDC VCO-based quantizer is shown in Figure 2.18. The input to the VCO is a sine wave. 1 TDC VCO-based Quantizer 0.5 0 -0.5 5 6 7 8 9 10 input 6 TDC VCO-based Quantizer output 0.5 0 -0.5 5 6 7 8 9 Figure 2.18: Single and multiple TDC VCO-based quantizer output vs. input signal 24 2.3.1 LINEAR MODELING AND ANALYSIS Figure 2.19 shows the input to the TDC as a pulse, and the output of the DFF at the rising edge of the sampling clock. The input signal is fed through a delay chain consisting of individual buffers with a delay of τbuff. This means that the detected period of the input is a multiple of τbuff, even though the actual period might be a fraction higher or lower. Tvco TDCin(t) t buff SET SET SET D SET Q D SET Q D SET Q D SET Q D SET Q D Q D Q D Q CLR Q CLR Q CLR Q CLR Q CLR Q CLR Q CLR Q CLR Q 0 1 1 1 0 0 0 0 Figure 2.19: Quantization of the TDC input: VCO period The output of the multi-bit TDC, using “N” TDCs, based on the VCO output period may now be derived. First detected output pulse width of the VCO is: The period of the VCO is divided by two since we are just detecting the positive going pulse with some quantization error. Again we assume that the quantization noise is white. The noise is uncorrelated and will combine as the , also the sampling frequency 25 is increased by “N”. This means the level of noise is constant across all frequencies and equal to (2.24) using the 2 sided definition of power [17 pp. 532-533]: Since the frequency of the VCO is of interest the pulse width is inverted. Assume that the second term in the denominator is much smaller than the first. 26 One thing to note is that the quantization noise changes when the input signal changes. There is some correlation between the noise and input signal which is nonlinear. For simplification we will ignore the noise due to the signal itself: After running several simulations these equations hold for the most part and remain a good enough approximation. Based on (2.30) the STF and NTF for the TDC VCO-based quantizer is derived. The noise transfer function for the TDC VCO-based quantizer is given below. From the derivations, the input signal and noise are both dependant on some of the same factors. To derive the SNR the power of the signal and the power of the noise at the output of the TDC are derived. If the input to the VCO is a sine wave the power of the output signal is the following. 27 Next the power of the noise is derived: To the authors knowledge this is the first time these equations have been derived. TDCs are traditionally used to detect the time or phase difference of two signals, but have not been used to detect the frequency of a signal. The complete TDC VCO-based quantizer model in VerilogA is shown below. The input to the VerilogA model is the clock signals and the input to the VCO. The model consists of the VCO, and “N” TDCs. The VCO is modeled using the ideal relationships, delayed along the chain, buffered and then fed to each TDC. At the rising clock edge of each TDC the pulse width of the delay chain output is determined. The output of the model is the inverted sum of the TDC’s. 28 // VerilogA for Sams, tdc, veriloga `include "constants.vams" `include "disciplines.vams" `define PI 3.14159265 module tdc(in, clk1,clk2,clk3,clk4,clk5 ,out); input in,clk1,clk2,clk3,clk4,clk5,; output out; electrical in,clk1,clk2,clk3,clk4,clk5,out; parameter real tbuff= 33p, // Buffer Delay vdd = 0.6, // Positive power supply vss = -0.6, // Negative power supply fc=500M, // VCO center frequency Kv=250M; // VCO gain factor Hz/V parameter N=5, // Number of TDCs n = 150; // Length of delay chain // Define variables integer q1[0:n-1],q2[0:n-1],q3[0:n-1],q4[0:n-1],q5[0:n-1] integer i,vs11,vs12,vs21,vs22,vs31,vs32,vs41,vs42,vs51,vs52; real Ac,vmid,phase,fvco,vcout,vp1,vp2,vp3,vp4,vp5,vp, d[0:n-1]; analog begin //Initialize parameters @(initial_step) begin Ac=(vdd-vss)/2.0; // VCO amplitude vmid=(vdd+vss)/2.0; // Midrail Voltage end // VCO equations fvco=Kv*V(in)+fc; // VCO frequency phase=2.0*`PI*idtmod(fvco,0,1,-0.5); // VCO phase vcout=vmid+Ac*sin(phase); // VCO output // Delay chain @(timer(0,tbuff)) begin // Delay the VCO pulse along the delay chain for(i=1;i for(i=0;i Figure 2.20: VerilogA code: TDC VCO-based quantizer 29 Figure 2.20 Continued // TDC2 @(cross(V(clk2)-vmid,1)) begin for(i=0;i 2.3.2 VERIFICATION The TDC VCO-based quantizer is designed to have a desired SNR based on the derivations in the linear modeling section. The following assumptions are made: power supply of 1.2V, a system bandwidth equal to 10MHz, and sampling frequency equal to 2 GHz. The input to the VCO will be a sine wave with amplitude equal to half supply. To achieve an SNR=60dB a VCO with a center frequency of 500MHz and gain of 250MHz/V along with 5 TDC’s is used. The delay chain consists of 150 buffers each with 32.579ps delay. These parameters are outlined in Table 2.3. The theoretical SNR is given by (2.38). VDD-VSS 1.2 V fs 2 GHz fb 10 MHz Am 0.6 V fc 500 MHz Kv 250MHz/V N 5 32.579ps n 150 Table 2.3: TDC VCO-based quantizer design parameters Figure 2.21 shows the test bench used to verify the design. The FDC VCO-based quantizer is simulated using the VerilogA code and the simulation parameters shown in Table 2.4. 31 Figure 2.21: TDC VCO-based quantizer test bench VDD 0.6 V VSS 0.6V fm 500 kHz Am 0.6 V Tstart 2μs Tstop 100μs Tsimulator 250ps Points 196000 Table 2.4: TDC VCO-based quantizer simulation parameters The results are shown below, where the output is normalized. The PSD of the output is shown in Figure 2.23. The FFT of the output is hann windowed. The simulated VerilogA SNR closely matches the theoretical SNR. 32 TDC VCO-based Quantizer 0.6 Input Output 0.4 0.2 0 Amplitude (V) Amplitude -0.2 -0.4 10 10.5 11 11.5 12 Time(sec) Figure 2.22: TDC VCO-based quantizer input vs. output (time domain) PSD TDC VCO-based Quantizer Output 0 f =500 kHz -20 m -40 Simulated VerilogA -60 SNR= 60.6894dB -80 Amplitude (dB) Amplitude -100 -120 f =10 MHz b -140 1 10 100 Frequency (MHz) Figure 2.23: PSD TDC VCO-based quantizer output 33 2.4 DISCUSSION Two VCO-based quantizers have been designed. One consists of an FDC, the other a TDC. Both are designed to achieve an SNR=60dB. The design parameters and characteristics for the two different quantizers are shown in Table 2.5. Both systems are designed with the same sampling frequency and bandwidth. The VCO for both designs is the same and each quantizer consists of the same number of stages. The FDC has 1st order noise shaping while the TDC does not. However the TDC has two more SNR tuning knobs than the FDC. Parameters FDC VCO-based TDC VCO-based Quantizer Quantizer 1 GHz 1 GHz fs, sampling frequency fb, System bandwidth 10 MHz 10 MHz fm [0:fb], VCO input 500 kHz 500 kHz signal frequency fc, VCO center frequency 500 MHz 500 MHz Kv, VCO gain 250 MHz/V 250 MHz/V N, number of stages 5 5 Noise shaping 1st order None SNR tuning knobs ↑(fs, N, Kv) ↑(fs, N, Kv) ↓(tbuff,fc) SNR 60.78 dB 60.68 dB Table 2.5: FDC VCO-based quantizer vs. TDC VCO-based quantizer 34 CHAPTER 3: LIMITATIONS OF THE VCO BASED QUANTIZER The VCO-based quantizer suffers from the non-ideal behavior of the VCO. Such things as the VCO nonlinearity and phase noise will reduce the performance of these quantizers. In order to model the VCO non-idealities a ring VCO is designed in the TSMC 90nm process. The tuning range of this VCO is simulated and modeled to determine the effects on the FDC and TDC VCO-based quantizers. The phase noise of the VCO is also simulated and modeled. Other circuit non-idealities exist but are ignored here since these quantizers are highly digital circuits. However these digital blocks are sampled using a clock source, therefore jitter in the sampling clock must also be considered. 3.1 VCO NONLINEARITY The main bottleneck to these types of quantizers is the VCO nonlinearity. Nonlinearity in the VCO tuning curve will result in harmonic spurs in the output spectrum, Figure 3.1. These spurs will degrade the SNDR depending on the amount on nonlinearity in the tuning curve. 35 Kv FDC/ D x(t)=Amsin(2pfmt) FFT S TDC P fm 2fm3fm nfm Frequency Figure 3.1: VCO nonlinearity in the output spectrum of the VCO-based quantizer 3.1.1 MODELING AND ANALYSIS A ring VCO is designed for the VCO-based quantizer with a center frequency of 500MHz and VCO tuning curve to satisfy the required 250MHz/V gain. The simulated VCO tuning curve is shown in Figure 3.2. The usable range to give 250MHz/V for a 1.2V supply is highlighted. The actual input voltage to satisfy this is about 400mV peak- peak. The tuning curve is modeled using a 6th order polynomial (3.1). VCO Tuning Curve 750 700 650 600 550 VCO tuning 500 curve 450 Usable Range 400 VCO frequency (Hz) frequency VCO 350 300 250 -0.6 0 0.6 Input Voltage(V) Figure 3.2: VCO tuning curve 36 The non-linear VCO tuning curve can be generalized as the following. The VerilogA code for the nonlinear VCO is shown below. The VCO frequency is written as the nonlinear equation, with coefficients depending on the VCO tuning curve. // Nonlinear VCO fvco=a6*pow(V(in),6)+a5*pow(V(in),5)+a4*pow(V(in),4)+a3*pow(V(in),3)+a2*pow(V(in),2) +a1*V(in)+a; phase=2.0*`PI*idtmod(fvco,0,1,-0.5); // VCO Phase Figure 3.3: VerilogA code nonlinear VCO The input to the VCO is a sine wave, shown below. The VCO frequency can be rewritten as: Using trig identities the VCO frequency equation can be expended as such. 37 The power at each frequency can be combined to get the power of the signal and power of the distortion terms. 38 From the above analysis the THD is: The SNDR is defined as the signal power divided by the noise plus distortion: The equation is simplified in terms of the SNR, signal power, and THD. This will come close to the simulated SNDR, with exception to the power of the signal being slightly different when distortion is present. 3.1.2 VERIFICATION The theoretical SNDR for the FDC VCO-based quantizer is: 39 The VerilogA code for the FDC is simulated as before, only with VCO nonlinearity added. The results are shown below. The theoretical SNDR closely matched the simulated VerilogA code. PSD Non-linear FDC VCO-based Quantizer Output 0 -20 f = 500kHz m -40 Simulated VerilogA Distortion -60 SNDR= 24.257dB SFDR= 24.676dB -80 THD= 0.37213% -100 -120 Amplitude (dB) Amplitude -140 -160 f =10 MHz -180 b -200 1 10 100 Frequency (MHz) Figure 3.4: PSD nonlinear FDC VCO-based quantizer output The theoretical SNDR for the TDC VCO-based quantizer is: 40 The VerilogA code for the TDC is simulated as before, only with VCO nonlinearity added. The results are shown below. The theoretical SNDR closely matched the simulated VerilogA code. PSD Non-linear TDC VCO-based Quantizer Output 0 f =500 kHz m -20 Distortion -40 Simulated VerilogA -60 SNDR= 24.2914dB SFDR= 24.676dB THD= 0.37213% -80 Amplitude (dB) Amplitude -100 -120 f =10 MHz b -140 1 10 100 Frequency (MHz) Figure 3.5: PSD nonlinear TDC VCO-based quantizer output Both the TDC and FDC handle linearity in the same manner, and one is not advantageous over the other. 3.2 VCO PHASE NOISE Phase noise is defined in the frequency domain. Phase noise in the frequency domain is the same thing as jitter in the time domain. Jitter adds to the VCO frequency and creates 41 phase noise in the VCO, Figure 3.6 [13]. This phase noise has a slope of 1/f2 when the VCO jitter is white. This is due to the fact that the VCO phase is the integral of the VCO frequency. ) ) 2 B 1/f B d ( d ( t q t S S f (Hz) f (Hz) t fvco(t) 2p q(t) sinq(t) x(t) Kv s fc Figure 3.6: VCO phase noise block diagram 3.2.1 MODELING AND ANALYSIS The phase noise plot for the VCO is shown below, simulated using SpectreRF. The VCO has a center frequency of 500MHz and designed for a large tuning range. It contains both 1/f3 and 1/f2 noise. 42 Simulate Phase Noise -40 -50 1/f3 -60 -70 -80 -90 -100 1/f2 L(f) (dBc/Hz) L(f) -110 -120 -130 -140 4 5 6 7 8 10 10 10 10 10 Relative Frequency Offset(Hz) Figure 3.7: Simulated VCO phase noise Pre-existing models in VerilogA model 1/f2 noise as shown below [13]. // VCO fvco=Kv*V(in)+fc; // VCO Frequency fjvco=1/(1/fvco+jitter); // Add jitter phase=2.0*`PI*idtmod(fjvco,0,1,-0.5); // VCO Phase vcout=Avco*sin(phase); // VCO output // Update jitter twice per period @ (cross(phase + `PI/2, +1, ttol) or cross(phase - `PI/2, +1, ttol)) begin jitter=sqrt(2)*($rdist_normal(seed,0,sig)); end Figure 3.8: Modeling 1/f2 VCO phase noise as jitter Jitter is considered white, with a normal distribution. It can be related to the phase noise plot in the 1/f2 region using the following relationships [19]. 43 The simulated phase noise shows L(f)=-140 at f=100MHz. Using (3.21) sigma is calculated as. The simulated VerilogA model is shown compared to the simulated phase noise, Figure 3.9. The VerilogA model accurately follows the simulated phase noise in the portion where the phase noise is 1/f2. The model falls short in the 1/f3 region. Simulated Phase Noise -40 Simulated VerilogA L(f) -50 Simulated L(f) -60 -70 -80 -90 -100 L(f) (dBc/Hz) L(f) -110 -120 -130 -140 -150 4 5 6 7 8 10 10 10 10 10 Relative Frequency Offset (Hz) Figure 3.9: VCO phase noise: VerilogA model vs. Simulated 44 Following the block diagram from before, the VCO phase adds 1/f2 shaping to the jitter. If the jitter is shaped by a filter to have 1/f shaping, then the overall phase will have 1/f3 shaping, Figure 3.10 [20]. ) B d ( t S t f (Hz) ) 3 B 1/f d ( ) t q B H(f) d 1/f S ( t f (Hz) S ) f ( 2 f (Hz) H fvco(t) 2p q(t) sinq(t) x(t) Kv s fc Figure 3.10: 1/f3 VCO phase noise block diagram This idea is used but the filter will not just have 1/f shaping to it. First the transfer function of the VCO phase noise is derived; it is shown plotted vs. the simulated phase noise, Figure 3.11. The transfer function of the simulated phase noise is given below. 45 Simulate Phase Noise -40 Simulated L(f) -50 Transfer Function L(f) -60 -70 -80 -90 -100 L(f) (dBc/Hz) L(f) -110 -120 -130 -140 -150 4 5 6 7 8 10 10 10 10 10 Relative Frequency Offset(Hz) Figure 3.11: Simulated phase noise transfer function Now that the simulated phase noise is modeled Figure 3.8 and Figure 3.10 are used determine the jitter filter H(f). The gain of H(f) must be 1 where we previously calculated jitter so that we may use the same value for jitter. H(f) is shown below. 46 H(f) 20 15 10 Magnitude (dB) Magnitude 5 0 4 5 6 7 8 10 10 10 10 10 Frequency (Hz) Figure 3.12: Jitter filter H(f) This filter is applied to the white noise jitter model from Figure 2.8, shown below. fjvco=1/(1/fvco+jitterc); // Add shaped jitter // Shape jitter to get jitterc jitterc=laplace_nd(jitter,{0,5.642e27, 6.412e23,7.87e18, 1.699e13, 1.075e7, 0.995}, {4.05e22,8.1e22,4.05e22,1.538e18,6.456e12,6.23e6,1}); Figure 3.13: VerilogA jitter filter Using the new model the VCO is simulated using the same value for sigma. The modeled VCO phase noise is plotted against the simulated VCO phase noise and closely matches one another, Figure 3.14. 47 Simulated Phase Noise -40 Simulated VerilogA L(f) -50 Simulated L(f) -60 -70 -80 -90 -100 L(f) (dBc/Hz) L(f) -110 -120 -130 -140 -150 4 5 6 7 8 10 10 10 10 10 Relative Frequency Offset (Hz) Figure 3.14: VCO phase noise: VerilogA+Jitter Filter model vs. Simulated The FDC output with phase noise can be written as the following. The power of the phase noise at the FDC output will be the integrated noise from the observation time to the system bandwidth 48 where The TDC phase noise can be written as the following, ignoring the phase noise in the quantization error. The power of the phase noise at the TDC output will be the integrated noise from the observation time to the system bandwidth 3.2.2 VERIFICATION The SNR with phase noise for the FDC is shown below. 49 The FDC is simulated as before, only this time with phase noise. The PSD of the FDC output is shown below; the modeled SNR closely matches the theoretical value in (3.33). PSD FDC VCO-based Quantizer Output with Phase Noise 0 -20 f = 500kHz m -40 Simulated VerilogA SNR= 59.2696dB -60 -80 Amplitude (dB) Amplitude -100 -120 f =10 MHz b -140 1 10 100 Frequency (MHz) Figure 3.15: PSD FDC VCO-based quantizer with phase noise The TDC SNR with phase noise is written below. 50 The TDC is simulated as before, only this time with phase noise. The PSD of the TDC output is shown below; the modeled SNR closely matches the theoretical value in (3.35). PSD TDC VCO-based Quantizer Output with Phase Noise 0 -20 f =500 kHz m -40 -60 Simulated VerilogA SNR= 59.4559dB -80 Amplitude (dB) Amplitude -100 -120 f =10 MHz b -140 1 10 100 Frequency (MHz) Figure 3.16: PSD TDC VCO-based quantizer with phase noise Both the FDC and TDC SNR degrade by about the same factor. The power of the phase noise in both cases gets multiplied by the number of stages, sampling frequency, and center frequency. 51 3.3 SAMPLING CLOCK JITTER It is important to model jitter from the sampling clock. A jittery clock in a typical ADC will cause a skirt around the desired signal, Figure 3.17. This is also the case with the VCO-based quantizer. For the FDC case there will be further noise cause by integration error due to jitter [12]. D S x(t)=Amsin(2pfmt) FDC/ P TDC FFT fm Jittery Clock Frequency D S P fs Frequency Figure 3.17: Block diagram: sampling clock jittering VCO-based ADC 3.3.1 MODELING AND ANALYSIS Both the FDC and TDC will experience the same amount of jitter in their sampling clock. The sampling clock is 2 GHz, a reasonable period jitter for this clock is 2ps rms [21]. As stated before sampling the input signal with a jittery clock will cause a skirt around the signal at the output spectrum. Sampling error is supposed to be related to input signal frequency in ideal ADCs and also these quantizers [12]. This was not observed during simulation and will be ignored for now since the jitter is so small. The integration error in 52 the FDC will be quite substantial and must be modeled. A similar derivation is followed in [12]. Consider the FDC output shown below. The phase of the VCO is given as: The difference between the VCO phases when sampling jitter taj , absolute jitter, is added is: The phase difference contains the actual signal and phase error which depends on the period jitter tpj: The power of the error is given in (3.40) where there is assumed no correlation between the two error components [12]: 53 3.3.2 VERIFICATION The SNR due to integration error, when tpj=2ps, for the FDC in given by: The FDC is simulated as before, only this time with clock jitter. The PSD of the FDC output is shown below; the modeled SNR closely matches the theoretical value in (3.42). PSD FDC VCO-based Quantizer Output with Jittery Clock 0 f =500 kHz m -20 Simulated VerilogA SNR= 48.5369dB -40 -60 Amplitude (dB) Amplitude -80 -100 f =10 MHz b -120 1 10 100 Frequency (MHz) Figure 3.18: PSD FDC VCO-based quantizer output with jittery clock 54 The TDC is simulated as before, only this time with clock jitter. The PSD of the TDC output is shown below; the modeled SNR closely matches ideal value, and sampling uncertainty is not impacting the SNR with such a small rms jitter value. PSD TDC VCO-based Quantizer Output with Jittery Clock 0 f =500 kHz -20 m Simulated VerilogA -40 SNR= 60.8622dB -60 -80 Amplitude (dB) Amplitude -100 -120 f =10 MHz b -140 1 10 100 Frequency (MHz) Figure 3.19: PSD TDC VCO-based quantizer output with jittery clock The FDC SNR degrades significantly due to sampling clock jitter when compared with the TDC. This is due to the fact that the sampling clock jitter also causes integration error of the VCO phase which destroys the first order noise shaping of the FDC. 55 3.4 DISCUSSION Now consider all the non-idealities: VCO nonlinearity, VCO phase noise, and sampling clock jitter. Figure 3.20-3.21 shows the non-ideal vs. the ideal FDC and TDC. Both are limited in SNR due to the VCO nonlinearity. PSD FDC VCO-based Quantizer Output 0 Ideal FDC -20 Simulated VerilogA Non-Ideal FDC Ideal SNR= 60.7852dB -40 Non-Ideal SNR= 24.227dB -60 -80 -100 -120 Amplitude (dB) Amplitude -140 -160 -180 -200 1 10 100 Frequency (MHz) Figure 3.20: PSD FDC VCO-based quantizer ideal vs. non-ideal 56 PSD TDC VCO-based Quantizer Output 0 Simulated VerilogA Ideal TDC -20 Ideal SNR= 60.6894dB Non-Ideal TDC Non-Ideal SNR= 24.2884dB -40 -60 -80 Amplitude (dB) Amplitude -100 -120 -140 1 10 100 Frequency (MHz) Figure 3.21: PSD TDC VCO-based quantizer ideal vs. non-ideal The SNR of the FDC and TDC are summarized in Table 3.1. The theoretical and modeled SNR with non-idealities is shown. The theoretical values closely match the modeled values and have been confirmed with multiple simulations. FDC SNR TDC SNR Theoretical VerilogA Theoretical VerilogA Ideal 60.11 dB 60.78 dB 61.03 dB 60.68 dB VCO Nonlinearity 24.29 dB 24.25 dB 24.29 dB 24.29 dB VCO Phase Noise 58.63 dB 59.27 dB 59.19 dB 59.45 dB Sampling Clock Jitter 48 dB 48.53 dB 60.86 dB All Non-Idealities 24.22 dB 24.21 dB 24.29 dB 24.28 dB Table 3.1: Effects of nonidealities on SNR FDC vs. TDC VCO-based Quantizer 57 CHAPTER 4: CONCLUSION AND FUTURE WORK This document presented an analytical and modeling approach to understanding the VCO-based quantizer. VerilogA was used to verify the theoretical equations derived by modeling and analysis. Two VCO-based quantizers were compared, one using the FDC the other a TDC. The FDC has been the recent method of digitization due to its inherent first order noise shaping. While TDCs have not been traditionally used for the VCO- based quantizer is has been used in asynchronous ADCs [10] [11]. These VCO-based quantizers were compared in the presence of VCO nonlinearity, VCO phase noise, and sampling clock jitter. VCO nonlinearity remains the main bottleneck of these types of quantizers and has been remedied by use of a modulator [5] [6] [7], or linearization of the VCO tuning curve [9]. While both quantizers responded similarly to VCO nonlinearity and phase noise, the TDC was less sensitive to sampling clock jitter. This is due to the fact that the FDC quantizes the VCO phase which is the integral of VCO frequency. Sampling clock jitter introduces integration error which corrupts the first order noise shaping of the FDC. 4.1 FDC/ TDC TRADEOFFS What has not been discussed yet is the requirements for each circuit. For the FDC, the sampling frequency must be 2x the maximum VCO frequency, according to the Nyquist 58 Criteria. Since the maximum VCO frequency will be much greater than the signal frequency, this system will always be oversampled. There is also this requirement to have a zero dc offset. This means that there are an equal number of 1’s and 0’s when the VCO frequency is at its center frequency. For this to occur the center frequency must be 4x smaller than the sampling frequency. This becomes important when the VCO is used in a modulator. To have multi-bit operation of the FDC VCO-based quantizer, the VCO will need to be a ring VCO to generate multiple phases. If instead of using a multi- phase output, the VCO output is delayed using a delay chain, the VCO phase noise will increase [16]. Unlike the FDC the TDCs sampling frequency must be 2x the input frequency to the VCO. However the delay chain must be able to capture a complete pulse width, this means the maximum VCO period must be 1.5 times smaller than the total delay of the chain. Also the minimum VCO period should not be less than a buffer delay. Since the TDC relies on a single output of the VCO it may be implemented with any VCO desired such as an LC tank. These two VCO-based quantizers have different circuit requirements, depending on the application and design requirements it might be beneficial to use one design over the other. This is outlined in Table 4.1. Restrictions FFDC TDC fs, Sampling frequency fs≥2 x VCOfmax fs≥2 x fb VCO frequency fc=fs/4 VCOTmax≥1.5 x Total Delay VCOTmin≥ tbuff VCO Ring VCO for MB operation Any SNR Tuning Knobs ↑(fs, N, Kv) ↑(fs, N, Kv) ↓(tbuff,fc) Table 4.1: FDC/TDC Circuit Restrictions 59 4.2 TWO-TONE TEST It is also important to determine how the ideal quantizers react to a two tone test. The output of the TDC period is inverted to give frequency, nonlinear relationships will exists, and might cause some distortion. The two tone test for both quantizers is tested using two sinusoids each with the same amplitude. The two frequencies of this test will st nd be fm=500 kHz, 125 kHz. The following 1 order and 2 order distortion products might exist: The PSD for the FDC and TDC using the two input frequencies is shown below. The FDC does not experience intermodulation distortion, however the TDC does. This can be attributed to the fact that the TDC measures the period of the signal and inverts to get frequency which is a nonlinear relationship. The TDC also has a nonlinear relationship of its quantization noise with the input signal. This causes spurs in the output which degrade the SNR. 60 PSD FDC VCO-based Quantizer Output 0 f =125 kHz f =500 kHz -20 m m -40 -60 Simulated VerilogA SNR= 66.5952dB -80 -100 -120 Amplitude (dB) Amplitude -140 -160 -180 -200 1 10 100 Frequency (MHz) Figure 4.1: PSD FDC 2-tone test PSD TDC VCO-based Quantizer Output 0 f =500 kHz f =125 kHz m m -20 -40 Simulated VerilogA SNR= 59.4972dB -60 -80 Amplitude (dB) Amplitude -100 -120 -140 1 10 100 Frequency (MHz) Figure 4.2: PSD TDC 2-tone test 61 4.3 FUTURE WORK There is still much to be determined about the circuit components that make up the TDC since the TDC has not been used to determine the frequency of a signal before. Also more test should be run, as shown by the two-tone test the TDC has nonlinear relationships unlike the FDC. Furthermore, VCO nonlinearity degrades the SNDR of these quantizers to the point of being useless. The quantizers should be examined in a modulator to get a reasonable SNDR, Figure 4.3. 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