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Virtual Events 61 OCTOBER 2020 Join the HiPEAC virtual events Future Real-Time Safety-Critical RISC-V Computers A holistic approach for Cyber-Physical Systems of Systems Welcome to the virtual Computing Systems Week contents 4 11 12 Innovation Europe EPEEC Programming Guidelines The impact of COVID-19 for Parallel Applications on the HiPEAC Jobs Portal 3 Welcome 14 HiPEAC futures Koen De Bosschere Acaces 2020 Career Session 4 Innovation Europe 16 HiPEAC futures First Milestones towards Future Real-Time Safety-Critical Three-minute thesis RISC-V Computers 17 News 6 Innovation Europe Simulating COVID-19 and flu spread using HiDALGO AMPERE: A holistic approach for real-time, high- Or how technology can support decision-making for an performance and energy-efficient Cyber-Physical Systems effective response to a pandemic of Systems 17 News 8 Innovation Europe CPS Convergence and Society SMART4ALL is a four-year innovation action promoting 18 News marketplace-as-a-service in South East Europe Welcome to the virtual Computing Systems Week hosted 10 Innovation Europe by Tampere University HENSOLDT Cyber presents MiG-V, the first RISC-V 19 News Processor “Made in Germany“ for Security Applications Afterthoughs on the ACACES2021 virtual summer school 11 Peac Performance 20 HiPEAC Conference 18-20 January 2021, Budapets EPEEC Programming Guidelines for Parallel Applications - Increasing application developers’ productivity 12 HiPEAC futures Impact of Covid-19 on HiPEAC Jobs Portal HiPEAC is the European network on high performance embedded architecture and compilation. hipeac.net @hipeac hipeac.net/linkedin HiPEAC has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement no. 871174. Cover image: Laura Vanzo, Visit Tampere Design: www.magelaan.be Editor: Rebecca Gorby & Vicky Wandels Email: [email protected] 2 HiPEACINFO 61 welcome 14 18 19 Acaces 2020 Career Session Virtual Computing Systems Week Afterthoughs on the ACACES2021 hosted by Tampere University virtual summer school The word of the year 2020 will probably be COVID-19. It started like yet another virus, but after some time, it became clear that it was the so-called “big one”. COVID- 19 became a humbling wake-up call. We sometimes believe that we are the masters of the universe, but we are not. A particle of 100 nm was, in no time, able to change the lifestyle of seven billion people on planet Earth, caused more than one million of deaths, ended thousands of businesses, and even changed the course of elections. The impact of the virus is on a par with the impact of a major natural disaster. Eventually, we will outsmart the virus with a vaccine, but it will take at least another year before the virus is under control. Inoculating seven billion people (twice) is no small task. Even at a rate of one shot per minute, it will take more than 100 000 person years, and depending on immunity response, this process might have to be repeated regularly. This means that unfortunately, COVID-19-related issues will not disappear the day after the first vaccines become widely available. By the time we will have acquired enough immunity, the world will have changed: new leaders will be in power, new businesses will have emerged, millions of people will have changed jobs, and the world economy will have evolved. Now is the right time to think outside the box and to propose bold revisions, to work towards a sustainable economy, to reduce inequality and injustice, to remedy the excesses of globalization and to create a better society. This is a once-in-a-lifetime opportunity for visionary leaders. I hope they will rise soon. It is crucial that we learn lessons from this pandemic: global problems can only be solved through solid science and global collaboration. COVID-19 is just one example of a global problem. Climate change is another, as is the reduction of biodiversity. COVID- 19 teaches us that there are no simple solutions for complex problems and that we need the joint creativity (science, politics, economy, media, education, etc.) of the whole world to find solutions for such problems. Fortunately, complex solutions will always require advanced computing, and that means that the computing industry will have a bright future, and will become even more relevant for society than it already is. I hope that we are all looking for new business opportunities in these turbulent times. Take care, Koen De Bosschere, HiPEAC coordinator HiPEACINFO 61 3 European technologies for a better-integrated world Innovation Europe FIRST MILESTONES TOWARDS FUTURE REAL-TIME SAFETY-CRITICAL RISC-V COMPUTERS The space industry, like other industries that make use of certifiable software-hardware platform using the RISC-V microelectronic circuits, depends to a great extent on American open-standard Instruction Set Architecture (ISA) and entirely technology. Historically, the United States has had a lead developed by European companies. Furthermore, the project in the sector by delivering state-of-the-art technologies. An also aims at providing avionics grade readiness, seeking example of this is the GAIA (Global Astrometric Interferometer DO-178C level B certification and even anticipating its usage in for Astrophysics) mission that was forced to use American other critical domains, like automotive or railways. technology due to a lack of an European alternative. This scenario can be problematic for European actors when the Currently, the project has been running for about one year, United States is able to exclude other players from the use of its and it is already achieving its first milestones. Platform technology, as well as to prevent licensing. requirements have been fully defined and early versions for Field Programmable Gate Array (FPGA) of the integrated In recent years, European developments within space- multicore with enhanced quota and performance monitoring computing have progressed and American space missions also units are being tested and further developed. It is expected currently use European technology for on-board processing. As that by the end of the project, in 2022, the platform will reach the space industry progresses to more advanced system-on-chip readiness level TRL8. architectures, the current lead manufacturers for space-grade processors in terms of performance is the United States again. The De-RISC platform rests on two fundamental pillars: high- At the same time, the trend towards higher integration does not performance and safety. Performance is delivered by a 64-bit only require high-performance. There is an increasing need for multicore architecture composed of a single scalable General- cybersecurity and partitioning as multiple software functions Purpose Processor (GPP), which in turn is comprised of four that were previously run on separate components in isolation NOEL-V cores (i.e. Cobham Gaisler’s RISC-V version of their are moved to the same system-on-chip. insignia processor, the LEON-5). Additionally, three levels of cache (core-private, GPP-shared and system-shared) and new Under such conditions, the De-RISC project was born. The processor cores with fully pipelined IEEE-754 Floating point project aims at productizing the first market-ready European units allow the platform to provide an increase in computational Cooperation for Space Standardization (ECSS) level B space- performance, compared to current systems. 4 HiPEACINFO 61 Innovation Europe monitoring units, will increase the amount of available tools to system integrators and platform users by providing fine-grain evidence of correct timing behavior. The platform is required to have a critical configuration that permits the user to either eliminate or bound temporal interference, and where core-local activities are not affected by another core’s activity. An example of this is the case of the Level 2 cache, which will allow partitioning across cores to avoid data evictions to critical tasks. This critical configuration also allows the user to disable cache coherency (maintained Image 1. Detail from De-RISC's architecture showcasing a scalable within the GPP) for certain memory areas without shared data General-Purpose Processor (GPP) element composed of RISC-V cores. in situations where cores mutually invalidate cache lines, hence De-RISC's platform will feature one GPP with four cores. making it difficult to predict latencies. As the development of the platform continues, more features Functionality-wise, the platform will support plenty of well- tackling security concerns and resource partition will be known standard Input/Output (IO) peripherals (e.g. I²C, SPI, implemented to reach platform readiness. 2x CAN-FD interfaces, 2x SpaceWire interfaces, 2x SpaceFibre interfaces) allowing its applicability to other domains beyond The project is composed by Cobham Gaisler (Sweden), fentISS (Spain), space. The system-on-chip platform also provides a fault- Thales Research & Technology (France) and the Barcelona tolerant DDR2 and DDR3 controller with strong error detection Supercomputing Center (BSC) (Spain), each partner contributing and correction capabilities. crucially to the project’s success. Gaisler is in charge of developing the hardware platform, while fentISS develops the software stack. BSC adds On the safety side, De-RISC combines state-of-the-art software to the platform with enhanced hardware safety features and Thales and hardware solutions to control the added high-performance validates the design with space use cases, like a telemetry and features.
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