Introduction to Embedded Systems
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Chapter 5 Multiprocessors and Thread-Level Parallelism
Computer Architecture A Quantitative Approach, Fifth Edition Chapter 5 Multiprocessors and Thread-Level Parallelism Copyright © 2012, Elsevier Inc. All rights reserved. 1 Contents 1. Introduction 2. Centralized SMA – shared memory architecture 3. Performance of SMA 4. DMA – distributed memory architecture 5. Synchronization 6. Models of Consistency Copyright © 2012, Elsevier Inc. All rights reserved. 2 1. Introduction. Why multiprocessors? Need for more computing power Data intensive applications Utility computing requires powerful processors Several ways to increase processor performance Increased clock rate limited ability Architectural ILP, CPI – increasingly more difficult Multi-processor, multi-core systems more feasible based on current technologies Advantages of multiprocessors and multi-core Replication rather than unique design. Copyright © 2012, Elsevier Inc. All rights reserved. 3 Introduction Multiprocessor types Symmetric multiprocessors (SMP) Share single memory with uniform memory access/latency (UMA) Small number of cores Distributed shared memory (DSM) Memory distributed among processors. Non-uniform memory access/latency (NUMA) Processors connected via direct (switched) and non-direct (multi- hop) interconnection networks Copyright © 2012, Elsevier Inc. All rights reserved. 4 Important ideas Technology drives the solutions. Multi-cores have altered the game!! Thread-level parallelism (TLP) vs ILP. Computing and communication deeply intertwined. Write serialization exploits broadcast communication -
Arduino Duemilanove W/ Atmega328
Arduino Duemilanove w/ Atmega328 Overview The Arduino Duemilanove ("2009") is a microcontroller board based on the ATmega168 (datasheet) or ATmega328 (datasheet). It has 14 digital input/output pins (of which 6 can be used as PWM outputs), 6 analog inputs, a 16 MHz crystal oscillator, a USB connection, a power jack, an ICSP header, and a reset button. It contains everything needed to support the microcontroller; simply connect it to a computer with a USB cable or power it with a AC-to-DC adapter or battery to get started. "Duemilanove" means 2009 in Italian and is named after the year of its release. The Duemilanove is the latest in a series of USB Arduino boards; for a comparison with previous versions, see the index of Arduino boards. Summary Microcontroller ATmega168 Operating Voltage 5V Input Voltage 7-12V (recommended) Input Voltage (limits) 6-20V Digital I/O Pins 14 (of which 6 provide PWM output) Analog Input Pins 6 DC Current per I/O Pin 40 mA DC Current for 3.3V Pin 50 mA 16 KB (ATmega168) or 32 KB (ATmega328) of which 2 KB used by Flash Memory bootloader SRAM 1 KB (ATmega168) or 2 KB (ATmega328) EEPROM 512 bytes (ATmega168) or 1 KB (ATmega328) Clock Speed 16 MHz Schematic & Reference Design EAGLE files: arduino-duemilanove-reference-design.zip Schematic: arduino-duemilanove-schematic.pdf Power The Arduino Duemilanove can be powered via the USB connection or with an external power supply. The power source is selected automatically. External (non-USB) power can come either from an AC-to-DC adapter (wall-wart) or battery. -
Computer Organization & Architecture Eie
COMPUTER ORGANIZATION & ARCHITECTURE EIE 411 Course Lecturer: Engr Banji Adedayo. Reg COREN. The characteristics of different computers vary considerably from category to category. Computers for data processing activities have different features than those with scientific features. Even computers configured within the same application area have variations in design. Computer architecture is the science of integrating those components to achieve a level of functionality and performance. It is logical organization or designs of the hardware that make up the computer system. The internal organization of a digital system is defined by the sequence of micro operations it performs on the data stored in its registers. The internal structure of a MICRO-PROCESSOR is called its architecture and includes the number lay out and functionality of registers, memory cell, decoders, controllers and clocks. HISTORY OF COMPUTER HARDWARE The first use of the word ‘Computer’ was recorded in 1613, referring to a person who carried out calculation or computation. A brief History: Computer as we all know 2day had its beginning with 19th century English Mathematics Professor named Chales Babage. He designed the analytical engine and it was this design that the basic frame work of the computer of today are based on. 1st Generation 1937-1946 The first electronic digital computer was built by Dr John V. Atanasoff & Berry Cliford (ABC). In 1943 an electronic computer named colossus was built for military. 1946 – The first general purpose digital computer- the Electronic Numerical Integrator and computer (ENIAC) was built. This computer weighed 30 tons and had 18,000 vacuum tubes which were used for processing. -
Parallel Computer Architecture
Parallel Computer Architecture Introduction to Parallel Computing CIS 410/510 Department of Computer and Information Science Lecture 2 – Parallel Architecture Outline q Parallel architecture types q Instruction-level parallelism q Vector processing q SIMD q Shared memory ❍ Memory organization: UMA, NUMA ❍ Coherency: CC-UMA, CC-NUMA q Interconnection networks q Distributed memory q Clusters q Clusters of SMPs q Heterogeneous clusters of SMPs Introduction to Parallel Computing, University of Oregon, IPCC Lecture 2 – Parallel Architecture 2 Parallel Architecture Types • Uniprocessor • Shared Memory – Scalar processor Multiprocessor (SMP) processor – Shared memory address space – Bus-based memory system memory processor … processor – Vector processor bus processor vector memory memory – Interconnection network – Single Instruction Multiple processor … processor Data (SIMD) network processor … … memory memory Introduction to Parallel Computing, University of Oregon, IPCC Lecture 2 – Parallel Architecture 3 Parallel Architecture Types (2) • Distributed Memory • Cluster of SMPs Multiprocessor – Shared memory addressing – Message passing within SMP node between nodes – Message passing between SMP memory memory nodes … M M processor processor … … P … P P P interconnec2on network network interface interconnec2on network processor processor … P … P P … P memory memory … M M – Massively Parallel Processor (MPP) – Can also be regarded as MPP if • Many, many processors processor number is large Introduction to Parallel Computing, University of Oregon, -
Arduino Uno SMD
Arduino Uno SMD Overview The Arduino Uno SMD is a version of the Arduino Uno, but uses an surface mount version of the Atmega328P instead of the through-hole version. This version was made in response to a shortage in supply of the through-hole Atmega328P. The board is based on the ATmega328 (datasheet). It has 14 digital input/output pins (of which 6 can be used as PWM outputs), 6 analog inputs, a 16 MHz crystal oscillator, a USB connection, a power jack, an ICSP header, and a reset button. It contains everything needed to support the microcontroller; simply connect it to a computer with a USB cable or power it with a AC-to- DC adapter or battery to get started. The Uno differs from all preceding boards in that it does not use the FTDI USB-to-serial driver chip. Instead, it features the Atmega8U2 programmed as a USB-to-serial converter. "Uno" means one in Italian and is named to mark the upcoming release of Arduino 1.0. The Uno and version 1.0 will be the reference versions of Arduino, moving forward. The Uno is the latest in a series of USB Arduino boards, and the reference model for the Arduino platform; for a comparison with previous versions, see the index of Arduino boards. Summary Microcontroller ATmega328 Operating Voltage 5V Input Voltage (recommended) 7-12V Input Voltage (limits) 6-20V Digital I/O Pins 14 (of which 6 provide PWM output) Analog Input Pins 6 DC Current per I/O Pin 40 mA DC Current for 3.3V Pin 50 mA Flash Memory 32 KB (ATmega328) of which 0.5 KB used by bootloader SRAM 2 KB (ATmega328) EEPROM 1 KB (ATmega328) Clock Speed 16 MHz Schematic & Reference Design EAGLE files: arduino-uno-smd-reference-design.zip Schematic: arduino-uno-smd-schematic.pdf Power The Arduino Uno can be powered via the USB connection or with an external power supply. -
Arduino Nano
Arduino Nano Arduino Nano Front Arduino Nano Rear Overview The Arduino Nano is a small, complete, and breadboard-friendly board based on the ATmega328 (Arduino Nano 3.0) or ATmega168 (Arduino Nano 2.x). It has more or less the same functionality of the Arduino Duemilanove, but in a different package. It lacks only a DC power jack, and works with a Mini-B USB cable instead of a standard one. The Nano was designed and is being produced by Gravitech. Schematic and Design Arduino Nano 3.0 (ATmega328): schematic, Eagle files. Arduino Nano 2.3 (ATmega168): manual (pdf), Eagle files. Note: since the free version of Eagle does not handle more than 2 layers, and this version of the Nano is 4 layers, it is published here unrouted, so users can open and use it in the free version of Eagle. Specifications: Microcontroller Atmel ATmega168 or ATmega328 Operating Voltage (logic 5 V level) Input Voltage 7-12 V (recommended) Input Voltage (limits) 6-20 V Digital I/O Pins 14 (of which 6 provide PWM output) Analog Input Pins 8 DC Current per I/O Pin 40 mA 16 KB (ATmega168) or 32 KB (ATmega328) of which 2 KB used by Flash Memory bootloader SRAM 1 KB (ATmega168) or 2 KB (ATmega328) EEPROM 512 bytes (ATmega168) or 1 KB (ATmega328) Clock Speed 16 MHz Dimensions 0.73" x 1.70" Power: The Arduino Nano can be powered via the Mini-B USB connection, 6-20V unregulated external power supply (pin 30), or 5V regulated external power supply (pin 27). -
Digital Signal Processing – II
www.jntuworld.com Digital Signal Processing – 8 December 24, 2009 VIII. DSP Processors 2007 Syllabus: Introduction to programmable DSPs: Multiplier and Multiplier-Accumulator (MAC), Modified bus structures and memory access schemes in DSPs, Multiple access memory, Multiport memory, VLSI architecture, Pipelining, Special addressing modes, On-chip peripherals. Architecture of TMS 320C5X – Introduction, Bus structure, Central Arithmetic Logic Unit, Auxiliary register, Index register, Auxiliary register, Compare register, Block move address register, Parallel Logic Unit, Memory mapped registers, Program controller, Some flags in the status registers, On-chip registers, On-chip peripherals. Contents: 8.1 DSP Processors – Market 8.2 DSP Processors – Features 8.3 Multiply-and-Accumulate 8.4 Interrupts – handling incoming signal values 8.5 Fixed- and Floating-point 8.6 Real-time FIR filter example We shall use “DSP” to mean Digital Signal Processor(s) and sometimes even refer to them as DSP processors, also as programmable digital signal processors (PDSPs). This includes 1. General purpose DSPs (such as the TMS320’s of TI and DSP563’s of Motorola and others) 2. Special purpose DSPs tailored to specific applications like FFT However, the so-called programmability of DSPs mentioned above pales in comparison to that of general purpose CPUs. In what follows, for the most part, we contrast general purpose CPUs (whose strength is in general purpose programmability) with DSPs (whose strength is in high throughput, hardwired, number crunching). For a -
Computer Memory Architecture Pdf
Computer memory architecture pdf Continue The methods used to implement the electronic computer storage memory architecture describe the methods used to implement electronic computer data storage, in such a way that it is a combination of the fastest, most reliable, most durable and least expensive way to store and obtain information. Depending on the application, one of these requirements may need to be compromised to improve the other requirement. Memory architecture also explains how binary digits are converted into electrical signals and then stored in memory cells. As well as the structure of the memory cell. For example, dynamic memory is commonly used for primary storage because of the fast speed of access. However, dynamic memory must be repeatedly updated with a spike of current dozens of times per second, or stored data will disintegrate and be lost. Flash memory allows you to store for years, but it's much slower than dynamic memory, and static memory storage cells wear out when used frequently. Similarly, the data bead is often designed to meet specific needs such as serial or parallel access to data, and memory can be designed to detect parity errors or even correct errors. The earliest memory architectures are Harvard Architecture, which has two physically separate memories and data transfer paths for the program and data, and Princeton's architecture, which uses a single path of memory and data for both the program and the storage of data. Most general-purpose computers use a hybrid split-cache modified Harvard architecture, which appears to be an application program to have a clean Princeton architectural machine with gigabytes of virtual memory, but internally (for speed) it works with a cache of instructions physically separate from a data cache more like the Harvard model. -
Communication Protocols on the PIC24EP and Arduino-A Tutorial For
Communication Protocols on the PIC24EP and Arduino – A Tutorial for Undergraduate Students A thesis submitted to the graduate school of the University of Cincinnati in partial fulfillment of the requirements for the degree of Master of Science In the Department of Electrical Engineering and Computing Systems of the College of Engineering and Applied Science By Srikar Chintapalli Bachelor of Technology: Electronics and Communications Engineering NIT Warangal, May 2015 Committee Chair: Dr. Carla Purdy Abstract With embedded systems technology growing rapidly, communication between MCUs, SOCs, FPGAs, and their peripherals has become extremely crucial to the building of successful applications. The ability for designers to connect and network modules from different manufacturers is what allows the embedded computing world to continue to thrive and overcome roadblocks, driving us further and further towards pervasive and ubiquitous computing. This ability has long been afforded by standardized communication protocols developed and incorporated into the devices we use on a day-to-day basis. This thesis aims to explain to an undergraduate audience and to implement the major communication protocols that are used to exchange data between microcontrollers and their peripheral modules. With a thorough understanding of these concepts, students should be able to interface and program their microcontroller units to successfully build projects, giving them hands on experience in embedded design. This is an important skill to have in a field in which configuring the electronics and hardware to work correctly is equally as integral as writing code for the desired application. The protocols that are discussed are the three main serial communication protocols: I2C (inter-integrated circuit), SPI (serial peripheral interface), and TTL UART (universal asynchronous receiver transmitter). -
Using EEPROM in Your DDS Development Kit
Using EEPROM in your DDS Development Kit By Bruce Hall, W8BH This article will describe how to store and retrieve data using the EEPROM in your DDS Development kit. I will upgrade the VFO memory project with EEPROM, enabling frequency memories to be created and stored without programming. EEPROM stands for Electrically Erasable and Programmable Read Only Memory. It is a section of the ATmega88 microcontroller which is used for storing small amounts of data. Up to 512 bytes of data can be stored, which remain on the chip until erased. In today‟s gigabyte word, half a kilobyte does not sound like much, but it is still very useful in our DDS kit. In my VFO memory project, described at http://w8bh.net/avr/AddMemories.pdf, I created a list of frequency presets. You can scroll through them with the encoder, allowing quick band changes. Unfortunately, once you compile your code, you are stuck with whatever frequencies you programmed. There is no way to change presets „in the field‟. EEPROM gives us a great way to save VFO memories and other program settings. EEPROM allow us to change these settings without recompiling, and untethers our DDS kit from the programming cable. I got excited about using EEPROM and quickly searched the internet for good programming examples. I found plenty of C code examples, mostly written for the Arduino, that show how to use EEPROM. But there were very few assembly language examples. I hope that some of you find my example helpful in your own designs. Reading and Writing EEPROM Reading and writing the EEPROM is more complicated that reading and writing data from other memory locations. -
Introduction to Computer Architecture
Introduction to Computer Architecture Mark Bull, EPCC Building Blocks of HPC Systems Four principal technologies which make up HPC systems: • Processors • to calculate • Memory • for temporary storage of data • Interconnect • so processors can talk to each other (and the outside world) • Storage • disks for storing input/output data and tapes for long term archiving of data • These talks will focus on the first two of these. 2 Processors • Basic functionality • execute instructions to perform arithmetic operations (integer and floating point) • load data from memory and store data to memory • decide which instructions to execute next • Arithmetic is performed on values in registers (local storage in the processor) • moving data between memory and registers must be done explicitly by load and store instructions • separate integer and floating point registers • typical size ~100 values • Basic characteristics: • Clock speed • Peak floating point capability 3 Processors (cont.) • Clock speed determines rate at which instructions are executed • modern chips are around 2-3 GHz • integer and floating point calculations can be done in parallel • can also have multiple issue, e.g. simultaneous add and multiply • peak flop rate is just clock rate x no. of floating point operations per clock cycle • Whole series of hardware innovations • pipelining • out-of-order execution, speculative computation • ... • Details of these become important for extracting high performance • most features are fairly generic 4 Moore’s Law • “CPU power doubles every -
Programmable Address Generation Unit for Deep Neural Network Accelerators
DEGREE PROJECT IN ELECTRICAL ENGINEERING, SECOND CYCLE, 30 CREDITS STOCKHOLM, SWEDEN 2020 Programmable Address Generation Unit for Deep Neural Network Accelerators MUHAMMAD JAZIB KHAN KTH ROYAL INSTITUTE OF TECHNOLOGY SCHOOL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE KTH ROYAL INSTITUTE OF TECHNOLOGY Electrical Engineering and Computer Science Programmable Address Generation Unit for Deep Neural Network Accelerators Muhammad Jazib Khan Master in Electrical Engineering Supervisor KTH: Yu Yang Examiner: Prof. Ahmed Hemani School of Electrical Engineering and Computer Science Host company: Robert Bosch GmbH Supervisor Bosch: Sebastian Vogel and Dr. Leonardo Ecco Abstract The Convolutional Neural Networks are getting more and more popular due to their applications in revolutionary technologies like Autonomous Driving, Biomedical Imaging, and Natural Language Processing. With this increase in adoption, the complexity of underlying algorithms is also increasing. This trend entails implications for the computation platforms as well, i.e. GPUs, FPGA, or ASIC based accelerators, especially for the Address Generation Unit (AGU), which is responsible for the memory access. Existing accelerators typically have Parametrizable Datapath AGUs, which have minimal adaptability towards evolution in algorithms. Hence new hardware is required for new algorithms, which is a very inefficient approach in terms of time, resources, and reusability. In this research, six algorithms with different implications for hardware are evaluated for address generation, and a fully Programmable AGU (PAGU) is presented, which can adapt to these algorithms. These algorithms are Standard, Strided, Dilated, Upsampled and Padded convolution, and MaxPooling. The proposed AGU architecture is a Very Long Instruction Word based Application Specific Instruction Processor which has specialized components like hardware counters and zero-overhead loops and a powerful Instruction Set Architecture (ISA), which can model static and dynamic constraints and affine and non-affine Address Equations.