Implementing Bead Probe Technology for In-Circuit Test: A Case Study

Mike Farrell Agilent Technologies Loveland, Colorado michael_farrell at agilent dot com

Glen Leinbach Caber Contacts, LLC Fort Collins, Colorado glen_leinbach at comcast dot net

Copyright © 2007 IEEE. Reprinted from 2007 ITC International Test Conference, Paper 18.1

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Implementing Bead Probe Technology for In-Circuit Test: A Case Study

Mike Farrell Glen Leinbach Agilent Technologies Caber Contacts, LLC Loveland, Colorado Fort Collins, Colorado michael_farrell at agilent dot com glen_leinbach at comcast dot net 970-679-5526 970-217-1051

and wetting of SAC2 solders. The additional flux Abstract residue left on test points plus the poorer wetting A major OEM implements bead probe technology characteristics of lead-free solder have required the use on a new design to gain test access and coverage of of some best practices to assure reliable probe contact high-speed circuits. Conventional probing techniques at ICT. [Rein05] are incompatible with the density and speed Bare copper (SMOBC-OSP3) test pads and vias requirements of the board. The experiences of a first make unreliable test contacts due to the buildup of implementation of bead probe technology are discussed copper oxide on the surface. The thin copper will not here, including CAD issues at board layout, test fixture prevent board damage during multiple probings. construction and debug, soldering process difficulties, Solder-coated vias are not recommended for probing and test probing problems during the ramp to high- since solder paste applied to them often runs down into volume production. the hole, resulting in the probe contacting either a flux- Introduction filled hole or a flux-covered annular copper ring around the hole. Neither results in reliable contact. A major OEM was developing a high-volume Solid copper test pads covered with reflowed solder graphics board which used DDR21 technology. Product paste, or loaded and soldered through-hole leads, are quality would be assured by a combination of in-circuit the only recommendation for use as test points. test (ICT) and functional test. High-speed busses [Rein06] connecting the two DDR2 memory devices, a DDR2 DIMM connector, and the controller ASIC and other Test Access vs. Test Coverage components could not accommodate conventional ICT Although the terms are often used interchangeably, probe pads due to signal integrity requirements and in this paper “test access” is defined as electrical access layout limitations. This would result in a significant test to a circuit node for testing. “Test coverage” is defined coverage reduction of the board, specifically the DDR2 as the ability to electrically test the board’s section. No test access to the DDR2 section at ICT components. Improving test access is usually a part of meant testing this section at functional test only, improving test coverage, but other factors play a part in complicating component level diagnosis and increasing test coverage. repair costs in manufacturing. On a previous board similar to this design, test Conventional ICT Probing access using conventional probing technology also was The established method of probing boards at ICT not able to test the DDR2 section of the board and has been complicated by the industry’s transition to DIMM connector, resulting in only about 55 percent lead-free processes. Most manufacturers already used a test coverage at ICT through direct and indirect test “no-clean” process, where all solder flux residue is left methods. The DDR2 section of the controlling ASIC on the board covering the solder joints. and the DDR2 memory devices were tested at functional test only. Defects were difficult and Switching to lead-free solder and its higher expensive to isolate. Also, pull-up and pull-down soldering temperatures caused flux breakdown, increas- resistors and capacitors associated with the DDR2 ing solder defect rates such as opens and poor wetting. section could not be tested at functional test. Many manufacturers switched to higher flux content solder pastes to reduce defects by improving the flow 2 Tin(Sn)-silver(Ag)-copper(Cu) lead-free solders 3 Solder Mask On Bare Copper with Organic 1 Double-data-rate two synchronous dynamic random Solderablility Protection: Provides a solderable finish to access memory the PCB pads and through holes.

Paper 18.1 INTERNATIONAL TEST CONFERENCE 1 1-4244-1128-9/07/$25.00©2007 IEEE Alternative test methods such as AOI, X-Ray, and by node name. The test access points information visual inspection were options to increase the test contains the X-Y location, the geometry type coverage of the DDR2 section of the board, but the (through-hole pin, solid pad, via, bead probe), and the OEM wanted to use the existing in-circuit test process side of the board (top or bottom) for the test access if possible and not add another step to the point. This information was instrumental in ensuring manufacturing process. that bead probe access points were limited to nodes in the DDR2 and USB sections. Also, since the bead Implementation probe geometry was identified as a via due to CAD This project was selected by the OEM to conduct an system limitations, it was possible that the test access opportunistic experiment: Implement Agilent Bead location could appear as a possible access point on both Probe Technology (ABPT) [Park04], [Park05] the top and bottom of the board when the CAD was [DoGr06] in the DDR2 section of the board to increase translated. It was imperative to ensure that the test access. The additional test access to previously translation process provided the correct side of the inaccessible nodes should increase the board’s test board on which each bead probe access point was coverage, driving yield improvements at the down- located. Until the translation process was validated, a stream steps of functional test and final assembly. If manual review of the translated data and CAD was yields of this board improved, bead probe technology required to ensure that bead probe test access points would then be implemented on future designs. were assigned to the correct side of the board. In some This product is a high-volume graphics formatter cases, this required modification of the translation board. It uses SMOBC-OSP metallization and is software. assembled in a no-clean lead-free process. Verification Review Board Layout Once the layout of the product was complete, the The first step in the process was to develop a layout CAD was reviewed for the following issues: component (test attribute) for the CAD design system • Verifying that the resulting board_xy file (used to for a bead probe test access point. The designers construct the in-circuit test fixture) contained the worked with Agilent’s bead probe experts to develop a bead probe locations. bead probe test geometry containing the size and shape • Determining which nodes used bead probe test for the apertures in the solder mask and in the solder access points and ensuring that only the DDR2 paste stencil which would be compatible with 4-mil- and USB 2.0 sections of the board used bead wide traces. The resulting geometry was an obround probe test access. opening in the solder mask, providing a test pad 20 mils • long on a 4-mil trace on which to build a bead probe. Ensuring that the resulting board_xy file The OEM’s standard layout rules which had been correctly identified the placement of the bead established for test vias and test pads were used to place probe on either the top or bottom of the board. the bead probe test access points on the board. It was During the test access review, the following prob- jointly decided by the OEM and Agilent to implement lems were discovered: bead probe test access only on the DDR2 section and Layout Driven Problems the USB 2.0 section where it was impractical to place conventional test pads. (Figure 1) • The first problem found was that the bead probe locations were not being translated over to the board_xy file. The problem was that bead probe locations were identified in the CAD data file as vias with a 2-mil pad. The CAD translation has the option of setting the minimum acceptable via pad size. Changing the acceptable via pad size to match the bead probe geometry fixed this problem. • The next problem was related to the first: The bead probe locations were identified as accessible Figure 1: Six bead probe locations on DDR2 bus on from both the top and bottom of the board bare board. because they had been interpreted as vias in the CAD data file. The CAD translation software The layout designer assigned the test attribute to the had an option to only allow test access to the side bead probe locations. The derived files from the CAD of the board identified in the CAD data file for used for test development show the test access points

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each individual via. Turning on this feature cor- with the same diameter as the probe shaft. The probe rected the problem. face is smooth. The fixture was a dual-well vacuum box • One of the common problems found during the fixture with top and bottom side probing which can test test access review was that some bead probes had four boards at a time. (Figure 2) been placed too close to components. With stan- For standard test access, 8-ounce probes were used. dard test access points such as test vias and solid For bead probe locations, 6-ounce probes were used. test pads, the designer has standard tools to help The only issue was that the fixture vendor used sharp ensure that proper spacings and keepouts are chisel probes in some of the bead probe locations. maintained. Additionally, the diameter of a con- These were replaced with flat-faced probes during ventional test pad is larger than that of its test fixture debug. (Figure 3) probe so the probe will never hit the component body or leads. However, the size of a bead probe is very small and the diameter of the flat face of the test probe is larger. A bead can be placed so close to a component that the flat-faced probe may hit the body or leads of the component. The Agilent 3070 software has a tool to help remove a test point that is either under or too close to a component. It relies on the component outline being correct in the board_xy file. The final board design had 148 nodes that used bead probe test access locations. The additional test access to these nodes allowed testing the DDR2 section of the board: Two DDR2 memory devices, the DDR2 DIMM connector, associated resistors and capacitors, and the DDR2 section of the ASIC. The added test access of the 148 nodes increased the board’s test access from 46 percent to 70 percent of circuit nodes. Test coverage Figure 3: Close-up of ICT probes. Red = standard prior to adding test access to the DDR2 section was chisel probe. Blue = .100” spacing flat-faced probes approximately 45 percent. This additional test access for BPT. Green = .075” spacing flat-faced probes for improved the total test coverage for the board from 45 BPT percent to 85 percent: a significant increase. Fixture Cost Fixture cost for adding top side probing to this four- board fixture added less than $5,000 to the cost of the fixture, but this one-time cost is outweighed by the increase in test coverage in the high-speed areas of the board. If double-sided probing was already required for this board, the additional cost to add bead probes would have been negligible.

Fixture Debug After receiving the in-circuit fixture, debugging and testing of the in-circuit program was done with five prototype boards built for the OEM by a contract manufacturer (CM) in the US. The bead probe locations Figure 2: Twin, dual-well ICT fixture for testing were examined with a microscope. The beads were four boards well formed and flux residue was minimal. The bead The ICT Fixture probe locations performed well with good electrical contact. (Figure 4) Building the in-circuit test fixture was a straight- forward process. New probes designed by Everett Charles Technologies (ECT) for BPT (Bead Probe Test) were used. These were headless flat-faced probes

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Figure 4: Nine bead probes on the DDR2 bus. Debugging and testing of the DDR2 section of the board where bead probes were used went well. There were no noticeable differences between the tests using standard test access and bead probes. The presence of bead probes allowed the direct debugging of a DDR2 Figure 6: Deformation of a single bottom-side bead digital test model and also allowed testing the DDR2 probe after multiple probings. The number of probe DIMM connector using TestJet/VTEP. Functional test cycles is shown in yellow. did not cover the DIMM connector. This test also implied that since the bead probe was Bead Probe Durability still nominally shaped after 50 to 100 cycles, the problem of crushed beads was due to a fixture On the top side of some of the boards used for problem.. debugging the test, boards several beads had been flattened. It was not known if being probed multiple To determine if a wiping action actually occurred, a times was damaging the beads or there was a problem test bed was assembled using a single flat faced probe with the ICT fixture (Figure 5). and a small test board with a bead probe mounted on a vise (Figure 7).

. Figure 5: Beads crushed during test debug. Figure 7: Flat faced probe (right) and test board To determine the durability of bead probes during with bead probe (right) mounted on test bed. multiple test actuations, a single board was pulled down Arrows indicate direction of travel of probe. on the vacuum-actuated ICT fixture over 300 times. The vise pressed the probe onto the bead probe and Photomicrographs were taken of bead probes several released it at low speed (Figure 8.) times during the test (Figure 6.) It was observed that the deformation (flattening) of the beads increased with the number of probings. This implied that the action of the test probe on the bead probe involved some kind of wiping or rolling action, and not just simple orthogonal pressure. This action could improve probe contact by displacing flux residues Figure 8: Flat faced probe coming down on bead Note in Figure 6 the “fuzzy” area of flux residue around probe (left) and in contact with bead probe (right.) the bead.

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High magnification video was also taken and analyzed. As the flat-faced probe began its release, it slightly but visibly wiped across the face of the bead probe, confirming the theory about a wiping action. It was then found that the original cause of the crushed beads was that the probes in the ICT fixture had not been completely seated, resulting in the probe running out of travel and bottoming out. This put very large forces on the bead probes, crushing them. The First Large Prototype Build For the prototype build, the CM moved the product to a high-volume facility offshore. The OEM made minor modifications to the board layout, and the fixture and test suites were updated. Over 600 boards were Figure 10: Missing solder on unloaded resistor pack built by this CM’s high volume offshore facility and land patterns. sent to the Agilent Loveland facility for test. These boards had major probe contact problems. A If the board failed pins test, it was put aside and tested visual review of the bead probe locations using a later. Some of the boards that passed the pins contact microscope found the following solder problems with tests had failures during unpowered analog the bead probe sites (Figure 9): measurement test, such as resistors reading high and • capacitors measuring high or missing. The boundary- No solder scan test for the DDR2 section of the ASIC also failed • Insufficient solder intermittently. Boards were retested until they passed • Large amounts of flux residue or a real failure was found. Boards that did not pass • pins test after cycling the fixture 10 times were retested. Poor wetting If they did not pass after a number of tries, the test suite was reduced to ensure that there were no shorts, that the major power devices had been tested and that the EEPROM was programmed. Boards with real failures were tagged. About ten of the 600+ boards were reviewed under a microscope by an SMT process engineer to determine probable causes of the soldering problems. A report was generated and communicated to the OEM and the CM. After testing the 600+ prototype boards and dis- cussing the results with the OEM, two things became apparent: The high-volume CM may not have known about the bead probes in general or about the experiment with this board. Also, there had been high turnover of new product introduction (NPI) engineers

Figure 9: One acceptable bead probe (top left), one covering this project leading to possible communication with insufficient solder (top center), one with poor problems. wetting (lower right) and two with no solder at all. The OEM then rolled the board design. A number of the resistor packs that had provided serial There were also areas on this board unrelated to termination to the DDR2 DIMM connector were bead probes which exhibited missing and insufficient eliminated. The ICT fixture and program were modified solder, indicating that the soldering problems may not to accommodate the design change. The OEM worked have been unique to bead probes. (Figure 10) with the high-volume CM’s engineers to ensure that Contact issues were a major problem in testing the they understood bead probes. An Agilent application 600+ boards. To resolve the contact issue for this batch engineer (AE) from the Loveland facility visited the of boards, the test plan was modified to first cycle the high-volume CM to discuss bead probe technology and vacuum 10 times and then run the probe-contact test. If its uses in future products. The AE recommended a board would then pass the pins contact test, the adding automated optical inspection (AOI) to monitor in-circuit test was allowed to continue. the application of solder to the bead probe locations,

Paper 18.1 INTERNATIONAL TEST CONFERENCE 5 and recommended exploring methods to reduce flux residue on the bead probe locations. The AE learned that the CM had used at least two different stencils: One used the recommended diamond-shaped apertures for bead probe locations, and the other used circular apertures. At the time of this publication the results comparing their performance were not complete. Second Large Prototype Run The high-volume CM built the next run of prototype boards and paid closer attention to the bead probe quality. (Figure 11) Figure 12: Single bead probe at high magnification showing flux residue. Early Production: The First Run The first production run again exhibited considerable bead probe contact problems at ICT. This time the first-pass yield at pins contact test fell to only about 35 percent. To do a quick check to see if there was solder flux residue on the bead probes preventing contact, the engineer lightly rubbed the top and bottom surfaces of the boards while wearing an ESD-safe cotton glove. Upon testing, the yield for pins contact test rose to almost 100 percent. This indicated that the problem was probably flux residue and not presence of a harder oxide or a problem with the fixture. Figure 11: Two well-formed bead probes after in- Research indicated that the lead-free SAC solder paste circuit testing. used was a standard formulation from a leading solder Approximately 275 boards were sent to the Agilent paste manufacturer. This manufacturer also offers the Loveland facility for testing. There were five same paste formulation in a version designed to “offer variations of the board using different component increased in-circuit pin test yields.” Most leading loading options. Test engineers in Loveland suspect solder paste manufacturers also offer similar products. that the two paste stencils were divided between Early Production: The Second Run different versions of boards and are awaiting confirmation from the OEM. Depending on which For a solder paste to be compatible with in-circuit version of board was tested, the first-pass yield for probe testing, any flux residue left on the bead probes pins contact test (where pin contact integrity is and conventional test pads should flake away during verified) was between 45% and 80%. Testing on this probing (Figure 13) or be soft enough to allow good batch was much smoother and quicker. There were contact. limited cases where a small number of bead probe locations had minimal solder, mainly around the two USB connectors. Boards that failed the pins contact test usually would pass after repeated (between 2 and 15) cycles of activating the vacuum fixture. The SMT process engineer again reviewed about ten boards from this build and generated a report. The flux residue was still a potential problem, although it had been reduced from the previous build. The OEM is not sure if the high-volume CM will be able to reduce the Figure 13: SEM images show unprobed and probed amount of flux residue any further. (Figure 12) beads. Note flux flaked away from probed bead. For the second run, the solder paste manufacturer’s “in- circuit test friendly” formulation of solder paste was used. Upon microscopic examination of boards from both batches, differences in the properties of the flux

Paper 18.1 INTERNATIONAL TEST CONFERENCE 6 residues were apparent. A small needle probe was used to nodes which are inaccessible to standard to scrape the residue along the side of several bead probing or to those which are not critical to the probes and larger pads. Residue on boards from the production and test processes. Using established first run was comparatively gummy and waxy, much conventional probing methods wherever possible like candle wax. It was easy to scrape a hard, curl- reduces risk. shaped flake of this residue. (Figure 14) • Constant communication with the CAD layout team, stencil manufacturer, CM, and fixture manufacturer on the how to design, implement, and use bead probes is important since it still is a new technology. Particular care in communication when personnel changes occur is imperative. • Use of a pin probe testable solder paste if a no- clean process is used will reduce probe contact problems. Most solder paste manufacturers offer these kinds of paste. • Once the manufacturer has demonstrated the ability to implement and use bead probes for ICT, the next logical step for the designer is to Figure 14: Large flake of flux residue on board built use bead probes on circuit nodes where with conventional solder paste. conventional probing is possible to take Boards from the second run with the “test friendly” advantage of the low impact of bead probes on solder paste had residue which was either still liquid or circuit geometries and the layout process. weak and brittle when probed with the needles probe. Summary: This should provide better electrical contact. (Figure 15) • Bead probes provided significant increases in test access and test coverage to areas and components of these boards. Conventional probe access was impossible. Test access increased from 46% to 70% of circuit nodes, increasing component test coverage from 45% to 85%. • Since the bead probe is a unique new feature, the existing CAD systems did not have automatic tools for adding bead probes or setting keep-out distances from component bodies. However, new tools were becoming available as introduction of this board proceeded. • The type and amount of solder flux on no-clean Figure 15: Soft, liquid flux residue from “test- lead-free boards was critical to probe contact friendly” solder paste. integrity. Probing Results: • Changing to a “test-friendly” solder paste version of the CM’s standard solder paste which was 108 boards with the new solder paste were tested. formulated for probe testing compatibility There was a fixture construction problem resulting in resulted in a significant improvement in probe three probes being off target. 50 of the boards failed contact results. Residues were soft, not hard, probe contact test due to this problem. gummy or tacky. This allowed good probe Of the remaining 58 boards where the probes contacted contact without preventing a buildup of flux the bead probes, 100% passed the probe contact test. residue on the probes. [SuPa08], [Smit09] This demonstrates that using a solder paste formulated for pin probe testing results in excellent probe contact. Conclusions: Best Practices • Close cooperation and communication among the OEM, the CM and particularly the CM’s process • For a first-time implementation of bead probe engineering group is imperative. The solder technology, the designer should add bead probes paste, fixture, and the stencil manufacturers also

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require training and communication for successful bead probe implementation. • Solder paste and flux choice is critical for successful implementation of bead probes in no- clean processes. Probe contact may be poor if a solder paste leaves hard, gummy, or waxy residues. • Fixture construction factors such as accuracy of probe location and proper seating of the probes is critical. • Since this product was designed and bead probes were implemented, a layout tool has become commercially available which adds bead probes to the design, sets keepout distances, selects those to be used for test, and analyzes test access. [PaDe07]

References [DoGr06] “Implementation of Solder-Bead Probing in High Volume Manufacturing”, M. Doraiswamy and J. J. Grealish, Proceedings, International Test Conference, paper 5.4, Santa Clara CA, Oct 2006 [Park04] K. P. Parker, “A New Probing Technique for High-Speed/High-Density Printed Circuit Boards,” Proceedings IEEE International Test Conference, 2004, pp 365-374 [Park05] K. P. Parker, “Bead Probes in Practice,” Pro- ceedings IEEE International Test Conference, Paper 26.2, Austin TX, Nov 2005 [Rein05] R. D. Reinosa, “Effect of Lead Free Solders on In-Circuit Test Process”, Proceedings, International Test Conference, Paper 26.3, Austin TX, Nov 2005 [Rein06] R. D. Reinosa, “Lead-free Through-Hole Techno- logy (THT) and Contact Repeatability in In- Circuit Test”, Proceedings, International Test Conference, Paper 5.3, Santa Clara CA, Oct 2006 [PaDe07] K. P. Parker and D. DeMille, “A Bead Probe CAD Strategy for In-Circuit Test”, Proceedings, International Test Conference, Paper 18.2, Santa Clara CA, Oct 2007 [SuPa08] D. Suraski and M. Parker, “Considerations for the Pin Probe Testing of No-Clean Solder Paste”, www.aimsolder.com [Smit09] B. Smith, “No-Clean Solder Paste Innovations”, Surface Mount Technology (SMT), November 1999

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