Performance Analysis of Instruction Set Architecture Extensions for Multimedia§

Total Page:16

File Type:pdf, Size:1020Kb

Performance Analysis of Instruction Set Architecture Extensions for Multimedia§ Performance Analysis of Instruction Set Architecture Extensions for Multimedia§ Nathan Slingerland Alan Jay Smith [email protected] [email protected] Apple Computer, Inc. University of California at Berkeley Abstract kernels taken from vendor provided libraries [1], [5] , [8] , [26] , [27] , [31] , [33]. Our contribution is unique as we do not focus Many microprocessor instruction sets include instructions for exclusively on a single architecture, and we study the performance accelerating multimedia applications such as DVD playback, of kernels derived from a real, measured, general purpose speech recognition and 3D graphics. Despite general agreement multimedia wor kload. Our results are obtained from actual on the need to support this emerging workload, there are hardware measurements rather than through simulation, instilling considerable differences between the instruction sets that have confidence in our results. been designed to do so. In this paper we study the performance of five instruction sets on kernels extracted from a broad multimedia Section 2 summarizes the multimedia workload we studied, and workload. Each kernel was recoded in the assembly language for details the sixteen computatio nally important kernels which we each of the five multimedia extensions. We compare the extracted from it. Our methodology for recoding the kernels with performance of contemporary implementations of each extension multimedia instructions and their measurement is described in against each other as well as to the original compiled C Section 3. An overview of the five instructions sets, and their performance. From our analysis we determine how well implementations, is given in Section 4. multimedia workloads map to current instruction sets, noting Our analysis is divided into two parts. Section 5 reflects our what was useful and what was not. We also propose two experience in coding the kernels, and lends insight into those enhancements to current architectures: strided memory instruction set features that we found useful. In Section 6 we operations, and fat subwords. compare the performance of five different processors each of Keywords: SIMD, subword paralle l, multimedia, instruction set, which implements a particular multimedia instruction set. We performance, measurement, MMX, SSE, AltiVec, VIS, MVI compare the performance of the five architectures both against one another, as well as their relative improvement over compiled 1. Introduction (optimized) C code. Finally, in Section 7 we propose two new directions for multimedia architectures on general purpose Specialized instructions have been introduced by microprocessor microprocessors: strided memory operations and fat subwords. vendors to support the unique computational demands of multimedia applications. The mismatch between wide data paths 2. Workload and the relatively short data types found in multimedia applications has lead the industry to embrace SIMD (single The lack of a standardized multimedia benchmark has meant that instruction, multiple data) style processing. Unlike traditional workload selection is the most difficult aspect of any study of forms of SIMD computing in which multiple individual multimedia. It was for this reason that we developed the Berkeley processors execute the same instruction, multimedia instructions multimedia workload, which is described in [35]. [35] is highly are executed by a single processor, and pack multiple short data recommended reading for any reader concerned about how elements into a single wide (64 or 128-bit) register, with all of the applications were selected or the technical merit and relevance of sub-elements being operated on in parallel. the Berkeley multimedia workload. It details why we felt existing multimedia benchmarks were unsuitable, develops and The goal of this paper is to quantify how architectural differences characterizes our workload, and extracts the kernels that we study between multimedia instruction sets translate into differences in here. The Berkeley multimedia workload was developed for use in performance. Prior studies have primarily focused on a single this research as well as our study of multimedia cache behavior in instruction set in isolation and have measured the performance of [36]. In selecting the component applications, we strove to cover as many types of media processing as possible: image compression (DjVu, JPEG), 3D graphics (Mesa, POVray), document rendering (Ghostscript), audio synthesis (Timidity), audio compression §Funding for this research has been provided by the State of California under the MICRO program, and by AT&T, Cisco Corporation, Fujitsu Microelectronics, IBM, Intel Corporation, Maxtor Corporation, Microsoft Corporation, Sun Microsystems, Toshiba Corporation and Veritas Software Corporation. 1 Sat Native Src Static %Static %CPU Kernel Name Source Application Data Type Arith Width Lines Instr Instr Cycles Add Block MPEG-2 Decode 8-bit (U) Ö 64-bits 46 191 0.1% 13.7% Block Match MPEG-2 Encode 8-bit (U) 128-bits 52 294 0.4% 59.8% Clip Test and Project Mesa FP limited 95 447 0.1% 0.8% Color Space Conversion JPEG Encode 8-bit (U) limited 22 78 0.1% 9.8% DCT MPEG-2 Encode 16-bit (S) 128-bits 14 116 0.1% 12.3% FFT LAME FP limited 208 981 4.4% 14.5% Inverse DCT MPEG-2 Decode 16-bit (S) Ö 128-bits 75 649 0.3% 29.7% Max Value LAME 32-bit (S) unlimited 8 39 0.2% 12.0% Mix Timidity 16-bit (S) Ö unlimited 143 829 1.0% 35.7% Quantize LAME FP unlimited 55 312 1.4% 15.3% Short Term Anal Filter GSM Encode 16-bit (S) Ö 128-bits 15 79 0.1% 20.2% Short Term Synth Filter GSM Decode 16-bit (S) Ö 128-bits 15 114 0.2% 72.7% Subsample Horizontal MPEG-2 Encode 8-bit (U) Ö 88-bits 35 244 0.3% 2.6% Subsample Vertical MPEG-2 Encode 8-bit (U) Ö unlimited 76 478 0.6% 2.1% Synthesis Filtering Mpg123 FP Ö 512-bits 67 348 0.4% 39.6% Transform & Normalize Mesa FP limited 51 354 0.1% 0.7% Table 1. Multimedia Kernels Studied - from left to right, the columns list 1) primary data type specified as N-bit ({Unsigned, Signed}) integer or floating point (FP), 2) if saturating arithmetic is used, 3) native width; the longest width which does not load/store/compute excess unused elements, 4) static C source line count (for those lines which are executed), 5) static instruction count (for those instructions which are executed) 6) percentage of total static instructions, 7) percentage of total CPU time spent in the kernel. The later three statistics are machine specific and are for the original C code on a Compaq DS20 (dual 500 MHz Alpha 21264, Tru64 Unix v5.0 Rev. 910) machine. (ADPCM, LAME, mpg123), video compression (MPEG-2 at invasive as possible. This also allowed us to quickly test new DVD and HDTV resolutions), speech synthesis (Rsynth), speech revisions of the code by linking against different versions of the compression (GSM), speech recognition (Rasta) and video game library. When adding a new architecture to our study it was (Doom) applications. Open source software was used both for its possible to simply start with a copy of the C reference version of portability (allowing for cross platform comparisons) and the fact the library and then implement and debug replacement SIMD that we could analyze the source code directly. assembly functions one at a time. It is usually neither time nor resource efficient to hand optimize 3.2. Coding Process every line of code in an application. Instead, optimization should focus on execution hot spots or computational kernels, thereby Ideally, high level language compilers would be able to limiting the recoding effort to those portions of the code that have systematically and automatically identify parallelizable sections of the most potential to improve overall performance. In order to code and generate the appropriate SIMD instruction sequence. evaluate the multimedia instruction sets, kernels were distilled SIMD optimizations would then not just be limited to multimedia from the workload based on their computational significance and applications, but could be more generally applied to any amenability to hand optimization with SIMD instructions; [35] application exhibiting the appropriate type of data parallelism. discusses the kernel selection process in detail. Each kernel was [21] has proposed strategies for extracting parallelism from hand coded in the assembly language of each of the five multimedia workloads with compilers. Recently, in fact, the very instruction sets. Table 1 lists the kernel codes examined. first commercial compilers have become available for Intel’s SSE ([16]) and Motorola’s AltiVec ([45]), although their effectiveness 3. Methodology is still an open question. The lack of languages which allow programmers to specify data types and overflow semantics at 3.1. Berkeley Multimedia Kernel Library variable declaration time has hindered the development of automated compiler support for multimedia instruction sets [10]. From a performance standpoint, no piece of code can realistically In addition, current SIMD extensions are clearly targeted for use be extracted and studied in isolation. In order to measure the by an expert applications programmer coding by hand in assembly performance of the multimedia instruction sets, we distilled from or through high-level language macros. our Berkeley multimedia workload a set of computationally important kernel functions, which when taken together form the 3.2.1. Hand Coding Berkeley multimedia kernel library (BMKL). All of the parent applications in the Berkeley multimedia workload were modified As is the case with digital signal processors (DSPs), the most to make calls to the BMKL rather than their original internal efficient way to program with multimedia extensions is to have an functions. By measuring our kernel codes from within real expert programmer tune software using assembly language [20]. applications we could realistically include the effects of the shared Although this is more tedious and error prone than other methods resources of our test systems (e.g.
Recommended publications
  • Implementing Elliptic Curve Cryptography (A Narrow Survey)
    Implementing Elliptic Curve Cryptography (a narrow survey) Institute of Computing – UNICAMP Campinas, Brazil April 2005 Darrel Hankerson Auburn University Implementing ECC – 1/110 Overview Objective: sample selected topics of practical interest. Talk will favor: I Software solutions on general-purpose processors rather than dedicated hardware. I Techniques with broad applicability. I Methods targeted to standardized curves. Goals: I Present proposed methods in context. I Limit coverage of technical details (but “implementing” necessarily involves platform considerations). Implementing ECC – 2/110 Focus: higher-performance processors “Higher-performance” includes processors commonly associated with workstations, but also found in surprisingly small portable devices. Sun and IBM workstations RIM pager circa 1999 SPARC or Intel x86 (Pentium) Intel x86 (custom 386) 256 MB – 8 GB 2 MB “disk”, 304 KB RAM 0.5 GHz – 3 GHz 10 MHz, single AA battery heats entire building fits in shirt pocket Implementing ECC – 3/110 Optimizing ECC Elliptic Curve Digital Signature Algorithm (ECDSA) Random number Big number and Curve generation modular arithmetic arithmetic Fq field arithmetic General categories of optimization efforts: 1. Field-level optimizations. 2. Curve-level optimizations. 3. Protocol-level optimizations. Constraints: security requirements, hardware limitations, bandwidth, interoperability, and patents. Implementing ECC – 4/110 Optimizing ECC... 1. Field-level optimizations. I Choose fields with fast multiplication and inversion. I Use special-purpose hardware (cryptographic coprocessors, DSP, floating-point, SIMD). 2. Curve-level optimizations. I Reduce the number of point additions (windowing). I Reduce the number of field inversions (projective coords). I Replace point doubles (endomorphism methods). 3. Protocol-level optimizations. I Develop efficient protocols. I Choose methods and protocols that favor your computations or hardware.
    [Show full text]
  • Computer Architectures an Overview
    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
    [Show full text]
  • 2 the VIS Instruction Set Pdist Instruction
    The VISTM Instruction Set Version 1.0 June 2002 A White Paper This document provides an overview of the Visual Instruction Set. ® 4150 Network Circle Santa Clara, CA 95054 USA www.sun.com Copyright © 2002 Sun Microsystems, Inc. All Rights reserved. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED"AS IS" WITHOUT ANY EXPRESS REPRESENTATIONS OR WARRANTIES. IN ADDITION, SUN MICROSYSTEMS, INC. DISCLAIMS ALL IMPLIED REPRESENTATIONS AND WARRANTIES, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. This document contains proprietary information of Sun Microsystems, Inc. or under license from third parties. No part of this document may be reproduced in any form or by any means or transferred to any third party without the prior written consent of Sun Microsystems, Inc. Sun, Sun Microsystems, the Sun Logo, VIS, Java, and mediaLib are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. UNIX is a registered trademark in the United States and other countries, exclusively licensed through x/Open Company Ltd. The information contained in this document is not designed or intended for use in on-line control of aircraft, air traffic, aircraft navigation or aircraft communications; or in the design, construction, operation or maintenance of any nuclear facility. Sun disclaims any express or implied warranty of fitness for such uses.
    [Show full text]
  • SIMD-Swift: Improving Performance of Swift Fault Detection
    Master thesis SIMD-Swift: Improving Performance of Swift Fault Detection Oleksii Oleksenko 15. November 2015 Technische Universität Dresden Department of Computer Science Systems Engineering Group Supervisor: Prof. Christof Fetzer Adviser: MSc. Dmitrii Kuvaiskii Declaration Herewith I declare that this submission is my own work and that, to the best of my knowledge, it contains no material previously published or written by another person nor material which to a substantial extent has been accepted for the award of any other degree or diploma of the university or other institute of higher education, except where due acknowledgment has been made in the text. Dresden, 9. November 2015 Oleksii Oleksenko Abstract The general tendency in modern hardware is an increase in fault rates, which is caused by the decreased operation voltages and feature sizes. Previously, the issue of hardware faults was mainly approached only in high-availability enterprise servers and in safety-critical applications, such as transport or aerospace domains. These fields generally have very tight requirements, but also higher budgets. However, as fault rates are increasing, fault tolerance solutions are starting to be also required in applications that have much smaller profit margins. This brings to the front the idea of software-implemented hardware fault tolerance, that is, the ability to detect and tolerate hardware faults using software-based techniques in commodity CPUs, which allows to get resilience almost for free. Current solutions, however, are lacking in performance, even though they show quite good fault tolerance results. This thesis explores the idea of using the Single Instruction Multiple Data (SIMD) technology for executing all program’s operations on two copies of the same data.
    [Show full text]
  • Ultrasparc T1™ Supplement to the Ultrasparc Architecture 2005
    UltraSPARC T1™ Supplement to the UltraSPARC Architecture 2005 Draft D2.1, 14 May 2007 Privilege Levels: Hyperprivileged, Privileged, and Nonprivileged Distribution: Public Sun Microsystems, Inc. 4150 Network Circle Santa Clara, CA 95054 U.S.A. 650-960-1300 Part No.No: 8xx-xxxx-xx819-3404-05 ReleaseRevision: 1.0, Draft 2002 D2.1, 14 May 2007 ii UltraSPARC T1 Supplement • Draft D2.1, 14 May 2007 Copyright 2002-2006 Sun Microsystems, Inc., 4150 Network Circle • Santa Clara, CA 950540 USA. All rights reserved. This product or document is protected by copyright and distributed under licenses restricting its use, copying, distribution, and decompilation. No part of this product or document may be reproduced in any form by any means without prior written authorization of Sun and its licensors, if any. Third-party software, including font technology, is copyrighted and licensed from Sun suppliers. Parts of the product may be derived from Berkeley BSD systems, licensed from the University of California. UNIX is a registered trademark in the U.S. and other countries, exclusively licensed through X/Open Company, Ltd. For Netscape Communicator™, the following notice applies: Copyright 1995 Netscape Communications Corporation. All rights reserved. Sun, Sun Microsystems, the Sun logo, Solaris, and VIS are trademarks, registered trademarks, or service marks of Sun Microsystems, Inc. in the U.S. and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the U.S. and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc The OPEN LOOK and Sun™ Graphical User Interface was developed by Sun Microsystems, Inc.
    [Show full text]
  • Idisa+: a Portable Model for High Performance Simd Programming
    IDISA+: A PORTABLE MODEL FOR HIGH PERFORMANCE SIMD PROGRAMMING by Hua Huang B.Eng., Beijing University of Posts and Telecommunications, 2009 a Thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in the School of Computing Science Faculty of Applied Science c Hua Huang 2011 SIMON FRASER UNIVERSITY Fall 2011 All rights reserved. However, in accordance with the Copyright Act of Canada, this work may be reproduced without authorization under the conditions for Fair Dealing. Therefore, limited reproduction of this work for the purposes of private study, research, criticism, review and news reporting is likely to be in accordance with the law, particularly if cited appropriately. APPROVAL Name: Hua Huang Degree: Master of Science Title of Thesis: IDISA+: A Portable Model for High Performance SIMD Pro- gramming Examining Committee: Dr. Kay C. Wiese Associate Professor, Computing Science Simon Fraser University Chair Dr. Robert D. Cameron Professor, Computing Science Simon Fraser University Senior Supervisor Dr. Thomas C. Shermer Professor, Computing Science Simon Fraser University Supervisor Dr. Arrvindh Shriraman Assistant Professor, Computing Science Simon Fraser University SFU Examiner Date Approved: ii Declaration of Partial Copyright Licence The author, whose copyright is declared on the title page of this work, has granted to Simon Fraser University the right to lend this thesis, project or extended essay to users of the Simon Fraser University Library, and to make partial or single copies only for such users or in response to a request from the library of any other university, or other educational institution, on its own behalf or for one of its users.
    [Show full text]
  • HPC-Event-Return-Of-Vector-20160801
    The OrionX Constellation: Data Center High Performance Computing The Return of Vector Processing Shahin Khan Digital transformation, cloud computing and application elasticity, open source software, and new app areas like AI and IoT are driving a renaissance in system architecture. This is an area of interest and research for us at OrionX. Vector processing was an interesting topic to re-emerge recently. First during the International Supercomputing Conference (ISC), and again in various announcements in implicit and explicit ways. On the Monday of the ISC conference, a new leader on the TOP500 list was announced. The Sunway TaihuLight system uses a new processor architecture that is Single-Instruction-Multiple-Data (SIMD) with a pipeline that can do eight 64-bit floating-point calculations per cycle. 10,649,600 computing cores comprising 40,960 nodes produce 93 petaflop/s running the LINPACK benchmark. Later that day, at the “ISC 2016 Vendor Showdown”, NEC had a presentation about its project “Aurora”. This project aims to combine x86 clusters and NEC’s vector processors in the same high bandwidth system. NEC has a long history of advanced vector processors with its SX architecture. Among many achievements, it built the Earth Simulator, a vector-parallel system that was #1 on the TOP500 list from 2002 to 2004. At its debut, it had a substantial (nearly 5x) lead over the previous #1. Vector Processing and Parallelism Vector processing is a time-honored system architecture that started the supercomputing market, starting with the CDC STAR-100 system (STrings and ARrays, performing at 100 million floating point operations per second), and then led by the legendary Seymour Cray and his superb team.
    [Show full text]
  • Université Batna 2 – Mostefa Ben Boulaïd Thèse Doctorat En
    République Algérienne Démocratique et Populaire Ministère de l’Enseignement Supérieur et de la Recherche Scientifique Université Batna 2 – Mostefa Ben Boulaïd Faculté de Technologie Département de Génie Industriel Thèse Préparée au sein du laboratoire d’Automatique & Productique Présentée pour l’obtention du diplôme de : Doctorat en Sciences en Génie Industriel Option : Génie Industriel Sous le Thème : An Optimized Approach to Software Security via Malware Analysis Présentée par : OURLIS Lazhar Devant le jury composé de : M. ABDELHAMID Samir MCA Université de Batna 2 Président M. BELLALA Djamel MCA Université de Batna 2 Rapporteur Mme. BOUAME Souhila MCA Université de Batna 2 Examinateur M.DJEFFAL Abdelhamid MCA Université de Biskra Examinateur M.KAHLOUL Laid Prof Université de Biskra Examinateur M. BENMOHAMMED Mohamed Prof Université de Constantine 2 Examinateur Novembre 2020 To my parents and family Contents List of Figures. .I List of Tables. .II Program Listings. III Abbreviations. IV Publications. .V Acknowledgements. .VI Abstract. VII Chapter 1 Introduction ...................................................................................................................... 1 1.1 Motivation for the research ............................................................................................ 3 1.2 Thesis scope .................................................................................................................... 3 1.3 Thesis outline .................................................................................................................
    [Show full text]
  • 10Th Gen Intel® Core™ Processor Families Datasheet, Vol. 1
    10th Generation Intel® Core™ Processor Families Datasheet, Volume 1 of 2 Supporting 10th Generation Intel® Core™ Processor Families, Intel® Pentium® Processors, Intel® Celeron® Processors for U/Y Platforms, formerly known as Ice Lake July 2020 Revision 005 Document Number: 341077-005 Legal Lines and Disclaimers You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. Intel technologies' features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No computer system can be absolutely secure. Check with your system manufacturer or retailer or learn more at intel.com. Intel technologies may require enabled hardware, specific software, or services activation. Check with your system manufacturer or retailer. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps Copies of documents which have an order number and are referenced in this document may be obtained by calling 1-800-548- 4725 or visit www.intel.com/design/literature.htm.
    [Show full text]
  • SPARC Assembly Language Reference Manual
    SPARC Assembly Language Reference Manual Part No: E36858 July 2014 Copyright © 1993, 2014, Oracle and/or its affiliates. All rights reserved. This software and related documentation are provided under a license agreement containing restrictions on use and disclosure and are protected by intellectual property laws. Except as expressly permitted in your license agreement or allowed by law, you may not use, copy, reproduce, translate, broadcast, modify, license, transmit, distribute, exhibit, perform, publish, or display any part, in any form, or by any means. Reverse engineering, disassembly, or decompilation of this software, unless required by law for interoperability, is prohibited. The information contained herein is subject to change without notice and is not warranted to be error-free. If you find any errors, please report them to us in writing. If this is software or related documentation that is delivered to the U.S. Government or anyone licensing it on behalf of the U.S. Government, the following notice is applicable: U.S. GOVERNMENT END USERS. Oracle programs, including any operating system, integrated software, any programs installed on the hardware, and/or documentation, delivered to U.S. Government end users are "commercial computer software" pursuant to the applicable Federal Acquisition Regulation and agency-specific supplemental regulations. As such, use, duplication, disclosure, modification, and adaptation of the programs, including any operating system, integrated software, any programs installed on the hardware, and/or documentation, shall be subject to license terms and license restrictions applicable to the programs. No other rights are granted to the U.S. Government. This software or hardware is developed for general use in a variety of information management applications.
    [Show full text]
  • SPARC M7™ Supplement to the Oracle SPARC Architecture 2015
    SPARC M7™ Supplement to the Oracle SPARC Architecture 2015 Draft D1.0, 30 Jun 2016 Privilege Levels: Privileged and Nonprivileged Distribution: Public Part No.No: 950-____-00 ReleaseRevision: 1.0, Draft 2002 D1.0, 30 Jun 2016 Oracle Corporation 4150 Network Circle Santa Clara, CA 95054 U.S.A. 650-960-1300 2 SPARC M7 Supplement • Draft D1.0, 30 Jun 2016 Copyright © 2011, Oracle and/or its affiliates. All rights reserved. Oracle and Java are registered trademarks of Oracle and/or its affiliates. Other names may be trademarks of their respective owners. AMD, Opteron, the AMD logo, and the AMD Opteron logo are trademarks or registered trademarks of Advanced Micro Devices. Intel and Intel Xeon are trademarks or registered trademarks of Intel Corporation. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. UNIX is a registered trademark licensed through X/Open Company, Ltd. 4 SPARC M7 Supplement • Draft D1.0, 30 Jun 2016 Contents 1 SPARC M7 Basics. .9 1.1 Background . 9 1.2 SPARC M7 Overview . 10 1.3 SPARC M7 Components . 11 1.3.1 SPARC Physical Core . 11 1.3.1.1 Single-threaded and multi-threaded performance . 12 1.3.2 L3 Cache. 12 2Data Formats . 15 3Registers. 17 3.1 Floating-Point State Register (FSR) . .17 3.2 Ancillary State Registers (ASRs) . 17 3.2.1 Tick Register (TICK). 18 3.2.2 Program Counter (PC). 18 3.2.3 Floating-Point Registers State Register (FPRS) . 19 3.2.4 General Status Register (GSR) .
    [Show full text]
  • ASIC DESIGN of the OPENSPARC T1 PROCESSOR CORE By
    ASIC DESIGN OF THE OPENSPARC T1 PROCESSOR CORE By Mohamed Mahmoud Mohamed Farag A Thesis Submitted to the Faculty of Engineering at Cairo University in Partial Fulfillment of the Requirements for the Degree of MASTER OF SCIENCE in ELECTRONICS AND COMMUNICATIONS ENGINEERING FACULTY OF ENGINEERING, CAIRO UNIVERSITY GIZA, EGYPT 2013 I ASIC DESIGN OF THE OPENSPARC T1 PROCESSOR CORE By Mohamed Mahmoud Mohamed Farag A Thesis Submitted to the Faculty of Engineering at Cairo University in Partial Fulfillment of the Requirements for the Degree of MASTER OF SCIENCE in ELECTRONICS AND COMMUNICATIONS ENGINEERING Under the Supervision of Prof. Dr. Serag El-Din Habib Dr. Hossam A. H. Fahmy Professor of Electronics Associate Professor Electronics and Communications Electronics and Communications Department Department Faculty of Engineering, Cairo University Faculty of Engineering, Cairo University FACULTY OF ENGINEERING, CAIRO UNIVERSITY GIZA, EGYPT 2013 II ASIC DESIGN OF THE OPENSPARC T1 PROCESSOR CORE By Mohamed Mahmoud Mohamed Farag A Thesis Submitted to the Faculty of Engineering at Cairo University in Partial Fulfillment of the Requirements for the Degree of MASTER OF SCIENCE in ELECTRONICS AND COMMUNICATIONS ENGINEERING Approved by the Examining Committee ____________________________ Prof. Dr. El Sayed Mostafa Saad, External Examiner ____________________________ Prof. Dr. Ibrahim Mohamed Qamar, Internal Examiner ____________________________ Prof. Dr. Serag El-Din Habib, Thesis Main Advisor ____________________________ Dr. Hossam A. H. Fahmy, Thesis Advisor FACULTY OF ENGINEERING, CAIRO UNIVERSITY GIZA, EGYPT 2013 III Engineer’s Name: Mohamed Mahmoud Mohamed Farag Date of Birth: 29/12/1985 Nationality: Egyptian Insert photo here E-mail: [email protected] Phone: 01068823040 Address: 7 Ramzy Farag Street – Al Haram Registration Date: …./…./…….
    [Show full text]