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ASIC DESIGN of the OPENSPARC T1 PROCESSOR CORE By ASIC DESIGN OF THE OPENSPARC T1 PROCESSOR CORE By Mohamed Mahmoud Mohamed Farag A Thesis Submitted to the Faculty of Engineering at Cairo University in Partial Fulfillment of the Requirements for the Degree of MASTER OF SCIENCE in ELECTRONICS AND COMMUNICATIONS ENGINEERING FACULTY OF ENGINEERING, CAIRO UNIVERSITY GIZA, EGYPT 2013 I ASIC DESIGN OF THE OPENSPARC T1 PROCESSOR CORE By Mohamed Mahmoud Mohamed Farag A Thesis Submitted to the Faculty of Engineering at Cairo University in Partial Fulfillment of the Requirements for the Degree of MASTER OF SCIENCE in ELECTRONICS AND COMMUNICATIONS ENGINEERING Under the Supervision of Prof. Dr. Serag El-Din Habib Dr. Hossam A. H. Fahmy Professor of Electronics Associate Professor Electronics and Communications Electronics and Communications Department Department Faculty of Engineering, Cairo University Faculty of Engineering, Cairo University FACULTY OF ENGINEERING, CAIRO UNIVERSITY GIZA, EGYPT 2013 II ASIC DESIGN OF THE OPENSPARC T1 PROCESSOR CORE By Mohamed Mahmoud Mohamed Farag A Thesis Submitted to the Faculty of Engineering at Cairo University in Partial Fulfillment of the Requirements for the Degree of MASTER OF SCIENCE in ELECTRONICS AND COMMUNICATIONS ENGINEERING Approved by the Examining Committee ____________________________ Prof. Dr. El Sayed Mostafa Saad, External Examiner ____________________________ Prof. Dr. Ibrahim Mohamed Qamar, Internal Examiner ____________________________ Prof. Dr. Serag El-Din Habib, Thesis Main Advisor ____________________________ Dr. Hossam A. H. Fahmy, Thesis Advisor FACULTY OF ENGINEERING, CAIRO UNIVERSITY GIZA, EGYPT 2013 III Engineer’s Name: Mohamed Mahmoud Mohamed Farag Date of Birth: 29/12/1985 Nationality: Egyptian Insert photo here E-mail: [email protected] Phone: 01068823040 Address: 7 Ramzy Farag Street – Al Haram Registration Date: …./…./…….. Awarding Date: 6 / 1 / 2013 Degree: Master of Science Department: ELECTRONICS AND COMMUNICATIONS ENGINEERING Supervisors: Prof. Dr. Serag El-Din Habib Dr. Hossam A. H. Fahmy Examiners: Prof. El Sayed Mostafa Saad (External examiner) Prof. Ibrahim Mohamed Qamar (Internal examiner) Porf. Serag El-Din Habib (Thesis main advisor) Porf. Hossam A. H. Fahmy (Thesis advisor) Title of Thesis: ASIC Design Of The OpenSPARC T1 Processor Key Words: ASIC; SPARC; Layout; Processor; Design Summary: The objective of this thesis is to carry out an ASIC design of the OpenSPARC T1 processor core using the 130nm CMOS technology. Starting from the open-source RTL description of the OpenSPARC T1 processor core, several modifications like memory mapping, reducing the processor threads and suppressing the test pins were made in order to reduce the processor size to fit into a 4x4 mm2 die. The correct functionality of the modified RTL description of this processor was verified against over 500 test scripts given by SUN Inc. Next, to convert the design from the RTL form to its gate level equivalent the design was synthesized. Subsequently, the design was physically implemented using the Place and Route flow, including the normal steps like floorplanning, placement, optimization, clock tree synthesis (CTS) and routing. Finally, the design was verified by a series of verification and performance evaluation tests to guarantee its functionality and performance. The designed processor core supports two threads and runs at a 100MHz clock frequency. It occupies an area of 16 mm2, including pads. IV Acknowledgments First I thank ALLAH (God) for being to my side during all the time I spent working on this thesis, HE blessed me with the strength and guidance that I needed to complete it. I would like to give my sincere appreciation to my parents for always giving me the moral support that I needed to continue working on this thesis and always praying for me. I would like to give a very special thank you to my wife who stood to my side and withstood a lot of burden during my work on this project. I would like to thank my manager at work "Ahmed Gharieb" for his endless support and understanding. I would like also to thank my Mentor Graphics family. Special thanks to "Mohamed Ali" my previous manager for being there for me whenever I needed him. I would like to thank my suppervisors "Dr. Serag" and "Dr. Hossam" for their support, guidance and understanding that they gave me throughtout my research. Finally I acknowledge MOSIS for providing the PDK of the IBM 130nm CMOS process under the MEP account number 4960. Contents AcknowledgmentsV Table of contentsVI List of figures XII List of tablesXV List of symbols and abbreviations XVI Abstract XXV 1 Introduction1 1.1 SPARC architecture...................1 1.1.1 SPARC V8 vs V9.................2 1.1.2 SPARC-V9 Processor...............4 VII 1.1.3 SPARC-V9 Instructions.............4 1.1.4 SPARC-V9 Traps.................6 1.1.5 SPARC-V9 Data Formats............7 1.1.6 SPARC-V9 Registers...............8 1.1.7 SPARC-V9 Memory Models...........8 1.1.8 SPARC-V9 Operation.............. 11 1.2 Thesis Objective..................... 12 1.3 Thesis Map........................ 13 2 OpenSparc T1 15 2.1 OpenSPARC T1 architecture.............. 16 2.1.1 SPARC Core................... 19 2.1.2 Floating-Point Unit................ 22 2.1.3 CPU-Cache Crossbar............... 22 2.1.4 L2-Cache..................... 24 2.1.5 DRAM Controller................. 25 2.1.6 I/O Bridge.................... 26 2.1.7 J-Bus Interface.................. 26 2.1.8 Serial System Interface.............. 27 2.1.9 Electronic Fuse.................. 27 2.2 OpenSPARC T1 core................... 28 2.2.1 Instruction fetch unit (IFU)........... 30 VIII 2.2.2 Execution unit (EXU).............. 32 2.2.3 Load store unit (LSU).............. 34 2.2.4 Trap logic unit (TLU).............. 36 2.2.5 Stream processing unit (SPU).......... 38 2.2.6 Memory management unit (MMU)....... 39 2.2.7 Floating-point frontend unit (FFU)....... 41 2.3 OpenSPARC T1 design history............. 43 2.3.1 Xilinx FPGA design 1 [6]............ 43 2.3.2 Xilinx FPGA design 2 [6]............ 44 2.3.3 UltraSparc T1 (Niagara) release [6]....... 44 2.3.4 Commercial processors based on the UltraSparc architecture [1].................. 46 2.4 Proposed Design..................... 48 3 OpenSPARC T1 core Implementation 51 3.1 RTL preparation and functional verification...... 51 3.2 Synthesis.......................... 61 3.3 Design Floorplanning................... 63 3.4 Design Placement..................... 68 3.5 CTS............................ 71 3.6 Routing.......................... 73 3.7 Post Layout Verification................. 74 IX 4 Results 76 4.1 Timing results....................... 77 4.2 Physical results...................... 87 4.3 Design comparison.................... 93 4.3.1 Processor size................... 94 4.3.2 Processor speed.................. 96 5 Conclusion 98 5.1 Future work........................ 100 5.1.1 Tighten the design constraints.......... 101 5.1.2 Custom implement the IRF memory module.. 101 5.1.3 Optimize clock network.............. 101 5.1.4 Use smaller technology node........... 103 A Digital design ASIC Flow 104 A.1 RTL preparation..................... 105 A.2 RTL functionality Verification.............. 109 A.3 Logic Synthesis...................... 112 A.4 Gate Level functionality Verification.......... 115 A.5 Floorplaning........................ 116 A.6 Placement......................... 131 A.7 Clock Tree Synthesis................... 136 X A.8 Routing.......................... 142 A.9 Post layout verification.................. 145 References 148 XI List of Figures 1.1 Memory Models from Least Restrictive (RMO) to Most Restrictive (TSO) [2]................... 10 2.1 OpenSPARC T1 Processor Block Diagram [5]..... 18 2.2 SPARC Core Pipeline [5]................. 21 2.3 CCX Block Diagram [5]................. 24 2.4 SPARC Core Block Diagram [5]............. 28 2.5 Execution Unit Diagram [5]............... 33 2.6 LSU Pipeline Graph [5].................. 35 2.7 TLU Role With Respect to All Other Backlogs in a SPARC Core [5]...................... 37 2.8 MMU and TLBs Relationship [5]............ 40 2.9 Top-Level FFU Block Diagram [5]............ 42 2.10 Sun UltraSPARC T1 (Niagara 8 Core) [6]....... 46 XII 3.1 Processor blocks rough estimation [5].......... 64 3.2 Design Power Grid.................... 65 3.3 Macro placement..................... 67 3.4 Empty spaces used up by Macros............ 68 3.5 Macro Power Connection................. 69 3.6 Top blocks placement................... 70 4.1 Setup slack distribution................. 79 4.2 Hold slack distribution.................. 80 4.3 Worst setup timing path.................. 82 4.4 Worst hold timing path.................. 83 4.5 Area percentage distribution............... 87 4.6 Die area distribution.................... 88 4.7 Cell density histogram................... 89 4.8 UltraSPARC T1 processor core [8]............ 95 5.1 IRF block area highlighted................ 102 A.1 Digital ASIC Design Flow................ 105 A.2 Simulation VS Formal Verification [17]......... 111 A.3 Synthesis Stage...................... 114 A.4 Floorplan of the design [21]............... 122 A.5 Pad driven VS Core driven [22]............. 124 XIII A.6 Power grid of the design [21]............... 128 A.7 Example of macro placement [21]............ 130 A.8 Global router G-cells [21]................. 136 A.9 Tools used in design flow................. 147 XIV List of Tables 3.1 Reduction in the processor core............. 58 4.1 Setup and hold timing path groups........... 78 4.2 Worst 10 setup paths..................
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