Université Batna 2 – Mostefa Ben Boulaïd Thèse Doctorat En

Total Page:16

File Type:pdf, Size:1020Kb

Université Batna 2 – Mostefa Ben Boulaïd Thèse Doctorat En République Algérienne Démocratique et Populaire Ministère de l’Enseignement Supérieur et de la Recherche Scientifique Université Batna 2 – Mostefa Ben Boulaïd Faculté de Technologie Département de Génie Industriel Thèse Préparée au sein du laboratoire d’Automatique & Productique Présentée pour l’obtention du diplôme de : Doctorat en Sciences en Génie Industriel Option : Génie Industriel Sous le Thème : An Optimized Approach to Software Security via Malware Analysis Présentée par : OURLIS Lazhar Devant le jury composé de : M. ABDELHAMID Samir MCA Université de Batna 2 Président M. BELLALA Djamel MCA Université de Batna 2 Rapporteur Mme. BOUAME Souhila MCA Université de Batna 2 Examinateur M.DJEFFAL Abdelhamid MCA Université de Biskra Examinateur M.KAHLOUL Laid Prof Université de Biskra Examinateur M. BENMOHAMMED Mohamed Prof Université de Constantine 2 Examinateur Novembre 2020 To my parents and family Contents List of Figures. .I List of Tables. .II Program Listings. III Abbreviations. IV Publications. .V Acknowledgements. .VI Abstract. VII Chapter 1 Introduction ...................................................................................................................... 1 1.1 Motivation for the research ............................................................................................ 3 1.2 Thesis scope .................................................................................................................... 3 1.3 Thesis outline .................................................................................................................. 3 2 Malware Overview ........................................................................................................... 5 2.1 A Brief History of Malware ............................................................................................ 5 2.2 Malware definition ....................................................................................................... 16 2.3 Malware propagation vectors ...................................................................................... 17 2.4 Malware concealment strategies .................................................................................. 20 2.4.1 Encryption ............................................................................................................ 20 2.4.2 Stealth ................................................................................................................... 20 2.4.3 Packing ................................................................................................................. 21 2.4.4 Oligomorphism ..................................................................................................... 21 2.4.5 Polymorphism ...................................................................................................... 22 2.4.6 Metamorphism ..................................................................................................... 23 2.5 Malware obfuscation techniques .................................................................................. 23 2.6 Malware types .............................................................................................................. 25 2.7 Malware analysis ......................................................................................................... 30 2.7.1 Static analysis ....................................................................................................... 30 2.7.2 Dynamic analysis ............................................................................................... 300 2.7.3 Memory analysis (memory forensics) .................................................................. 31 2.8 Malware detection ........................................................................................................ 31 2.8.1 Signature-based detection .................................................................................... 32 2.8.2 Heuristic-based detection ..................................................................................... 36 3 Pattern-matching algorithms ........................................................................................ 37 3.1 Pattern-matching problem ........................................................................................... 37 3.2 Exact pattern-matching algorithms .............................................................................. 39 3.3 Brute force algorithm ................................................................................................... 39 3.4 The Boyer-Moore algorithm ......................................................................................... 40 3.4.1 The bad character heuristic .................................................................................. 41 3.4.2 The good suffix heuristic ...................................................................................... 43 3.5 The Aho-Corasick algorithm ........................................................................................ 47 3.5.1 Review of the AC algorithm ................................................................................ 49 3.5.2 Review of the AC algorithm using the next-move function ................................. 54 4 SIMD Implementation of the Aho-Corasick Algorithm using Intel® AVX2 ............ 57 4.1 Intel© SIMD extensions ................................................................................................ 59 4.1.1 MMX™ Technology ............................................................................................ 60 4.1.2 Streaming SIMD Extensions (SSE) ..................................................................... 61 4.1.3 Advanced Vector Extensions (AVX) ................................................................... 63 4.1.4 Test for AVX2 support ......................................................................................... 65 4.2 Vectorization: Data Parallelism .................................................................................. 68 4.3 Vectorization approaches (SIMD programming methods) .......................................... 69 4.4 Characteristics of SIMD operations ............................................................................ 71 4.5 SIMD Implementation of the Aho-Corasick Algorithm using Intel® AVX2 ................. 73 4.5.1 Vectorization of the Aho-Corasick Algorithm using Intel® AVX2 ..................... 73 4.5.2 Experimental results ............................................................................................. 76 5 Improving the Signature Scanner using an Optimized Aho-Corasick algorithm .... 80 5.1 Scanning for byte-stream signatures ............................................................................ 82 5.2 The signature scanner tool ........................................................................................... 85 5.3 Performance analysis ................................................................................................... 87 5.3.1 Performance according to the malware database ................................................. 88 5.3.2 Performance according to the malware signature size ......................................... 90 6 Conclusion ....................................................................................................................... 92 BIBLIOGRAPHY . 93 List of Figures Figure 2. 1: Aycock's classification of malware ...................................................................... 26 Figure 2. 2: Adleman’s classification of malware ................................................................... 26 Figure 2. 3: Microsoft malware classification ......................................................................... 27 Figure 2. 4: Malware detected by the MSRT by means of propagation ability ...................... 28 Figure 2. 5: Kaspersky Lab malware classification diagram................................................... 29 Figure 2. 6: Hexadecimal representation of a typical malware signature and the corresponding x86 code snippet .............................................................................................. 33 Figure 2. 7: Hexadecimal representation of a generic malware signature.............................. 34 Figure 2. 8: ClamAV signature for the Virut malware ........................................................... 34 Figure 3. 1: Application fields using pattern-matching ........................................................... 37 Figure 3. 2: The bad character shift heuristic .......................................................................... 41 Figure 3. 3: The good suffix .................................................................................................... 43 Figure 3. 4: The matching suffix occurs somewhere else in the pattern ................................. 44 Figure 3. 5: A partial of a good suffix occurs as a prefix of the pattern .................................. 44 Figure 3. 6: Pattern-matching machine for the set of keywords {these, this, the, set} ........... 50 Figure 3. 7: State transitions using the next-move function .................................................... 56 Figure 4. 1: Classification of parallel architectures ................................................................ 58 Figure 4. 2: Intel® SIMD extensions ....................................................................................... 59 Figure 4. 3: MMX data types..................................................................................................
Recommended publications
  • Software Analysis for Security
    Software Analysis for Security Spiros Mancoridis Department of Computer Science College of Engineering Drexel University Philadelphia, PA 19147, USA E-mail: [email protected] Abstract ware architecture to assure the system’s security. The qual- ity of a security architecture, however, also depends on the This is a survey of the processes, practices, and technolo- security of the applications that constitute the system. In gies that can help software maintenance engineers improve low security operating environments, such as most commer- the security of software systems. A particular emphasis is cial operating systems, it is assumed, albeit optimistically, placed on validating security architectures, verifying that that these applications are trustworthy. Therefore, it is im- the implementation of an architecture’s constituent appli- portant to articulate the practices to support the secure cod- cations adhere to secure coding practices, and protecting ing of applications and the tools for detecting malware. Se- software systems against malicious software. In addition to cure coding involves programming practices and run-time surveying the state-of-the-art, research challenges pertain- mechanisms that can be used to limit the vulnerabilityof ap- ing to software security are posed to the software mainte- plications to dangerous malware that exploit, for example, nance research community. buffer overflows, format string vulnerabilities, and integer vulnerabilities to attack computer systems. One approach to software security is to verify that (a) the security mechanisms used are trustworthy; (b) the security 1. Introduction architecture has been validated against the security policy; and (c) the software applications that constitute the system The goal of computer security is to protect computer as- are trustworthy (e.g., they have been developed using secure sets (e.g., servers, applications, web pages, data) from cor- coding practices, or they are not malware).
    [Show full text]
  • Implementing Elliptic Curve Cryptography (A Narrow Survey)
    Implementing Elliptic Curve Cryptography (a narrow survey) Institute of Computing – UNICAMP Campinas, Brazil April 2005 Darrel Hankerson Auburn University Implementing ECC – 1/110 Overview Objective: sample selected topics of practical interest. Talk will favor: I Software solutions on general-purpose processors rather than dedicated hardware. I Techniques with broad applicability. I Methods targeted to standardized curves. Goals: I Present proposed methods in context. I Limit coverage of technical details (but “implementing” necessarily involves platform considerations). Implementing ECC – 2/110 Focus: higher-performance processors “Higher-performance” includes processors commonly associated with workstations, but also found in surprisingly small portable devices. Sun and IBM workstations RIM pager circa 1999 SPARC or Intel x86 (Pentium) Intel x86 (custom 386) 256 MB – 8 GB 2 MB “disk”, 304 KB RAM 0.5 GHz – 3 GHz 10 MHz, single AA battery heats entire building fits in shirt pocket Implementing ECC – 3/110 Optimizing ECC Elliptic Curve Digital Signature Algorithm (ECDSA) Random number Big number and Curve generation modular arithmetic arithmetic Fq field arithmetic General categories of optimization efforts: 1. Field-level optimizations. 2. Curve-level optimizations. 3. Protocol-level optimizations. Constraints: security requirements, hardware limitations, bandwidth, interoperability, and patents. Implementing ECC – 4/110 Optimizing ECC... 1. Field-level optimizations. I Choose fields with fast multiplication and inversion. I Use special-purpose hardware (cryptographic coprocessors, DSP, floating-point, SIMD). 2. Curve-level optimizations. I Reduce the number of point additions (windowing). I Reduce the number of field inversions (projective coords). I Replace point doubles (endomorphism methods). 3. Protocol-level optimizations. I Develop efficient protocols. I Choose methods and protocols that favor your computations or hardware.
    [Show full text]
  • Computer Viruses and Malware Advances in Information Security
    Computer Viruses and Malware Advances in Information Security Sushil Jajodia Consulting Editor Center for Secure Information Systems George Mason University Fairfax, VA 22030-4444 email: [email protected] The goals of the Springer International Series on ADVANCES IN INFORMATION SECURITY are, one, to establish the state of the art of, and set the course for future research in information security and, two, to serve as a central reference source for advanced and timely topics in information security research and development. The scope of this series includes all aspects of computer and network security and related areas such as fault tolerance and software assurance. ADVANCES IN INFORMATION SECURITY aims to publish thorough and cohesive overviews of specific topics in information security, as well as works that are larger in scope or that contain more detailed background information than can be accommodated in shorter survey articles. The series also serves as a forum for topics that may not have reached a level of maturity to warrant a comprehensive textbook treatment. Researchers, as well as developers, are encouraged to contact Professor Sushil Jajodia with ideas for books under this series. Additional tities in the series: HOP INTEGRITY IN THE INTERNET by Chin-Tser Huang and Mohamed G. Gouda; ISBN-10: 0-387-22426-3 PRIVACY PRESERVING DATA MINING by Jaideep Vaidya, Chris Clifton and Michael Zhu; ISBN-10: 0-387- 25886-8 BIOMETRIC USER AUTHENTICATION FOR IT SECURITY: From Fundamentals to Handwriting by Claus Vielhauer; ISBN-10: 0-387-26194-X IMPACTS AND RISK ASSESSMENT OF TECHNOLOGY FOR INTERNET SECURITY.'Enabled Information Small-Medium Enterprises (TEISMES) by Charles A.
    [Show full text]
  • Computer Architectures an Overview
    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
    [Show full text]
  • 2 the VIS Instruction Set Pdist Instruction
    The VISTM Instruction Set Version 1.0 June 2002 A White Paper This document provides an overview of the Visual Instruction Set. ® 4150 Network Circle Santa Clara, CA 95054 USA www.sun.com Copyright © 2002 Sun Microsystems, Inc. All Rights reserved. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED"AS IS" WITHOUT ANY EXPRESS REPRESENTATIONS OR WARRANTIES. IN ADDITION, SUN MICROSYSTEMS, INC. DISCLAIMS ALL IMPLIED REPRESENTATIONS AND WARRANTIES, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. This document contains proprietary information of Sun Microsystems, Inc. or under license from third parties. No part of this document may be reproduced in any form or by any means or transferred to any third party without the prior written consent of Sun Microsystems, Inc. Sun, Sun Microsystems, the Sun Logo, VIS, Java, and mediaLib are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. UNIX is a registered trademark in the United States and other countries, exclusively licensed through x/Open Company Ltd. The information contained in this document is not designed or intended for use in on-line control of aircraft, air traffic, aircraft navigation or aircraft communications; or in the design, construction, operation or maintenance of any nuclear facility. Sun disclaims any express or implied warranty of fitness for such uses.
    [Show full text]
  • What Are Kernel-Mode Rootkits?
    www.it-ebooks.info Hacking Exposed™ Malware & Rootkits Reviews “Accessible but not dumbed-down, this latest addition to the Hacking Exposed series is a stellar example of why this series remains one of the best-selling security franchises out there. System administrators and Average Joe computer users alike need to come to grips with the sophistication and stealth of modern malware, and this book calmly and clearly explains the threat.” —Brian Krebs, Reporter for The Washington Post and author of the Security Fix Blog “A harrowing guide to where the bad guys hide, and how you can find them.” —Dan Kaminsky, Director of Penetration Testing, IOActive, Inc. “The authors tackle malware, a deep and diverse issue in computer security, with common terms and relevant examples. Malware is a cold deadly tool in hacking; the authors address it openly, showing its capabilities with direct technical insight. The result is a good read that moves quickly, filling in the gaps even for the knowledgeable reader.” —Christopher Jordan, VP, Threat Intelligence, McAfee; Principal Investigator to DHS Botnet Research “Remember the end-of-semester review sessions where the instructor would go over everything from the whole term in just enough detail so you would understand all the key points, but also leave you with enough references to dig deeper where you wanted? Hacking Exposed Malware & Rootkits resembles this! A top-notch reference for novices and security professionals alike, this book provides just enough detail to explain the topics being presented, but not too much to dissuade those new to security.” —LTC Ron Dodge, U.S.
    [Show full text]
  • SIMD-Swift: Improving Performance of Swift Fault Detection
    Master thesis SIMD-Swift: Improving Performance of Swift Fault Detection Oleksii Oleksenko 15. November 2015 Technische Universität Dresden Department of Computer Science Systems Engineering Group Supervisor: Prof. Christof Fetzer Adviser: MSc. Dmitrii Kuvaiskii Declaration Herewith I declare that this submission is my own work and that, to the best of my knowledge, it contains no material previously published or written by another person nor material which to a substantial extent has been accepted for the award of any other degree or diploma of the university or other institute of higher education, except where due acknowledgment has been made in the text. Dresden, 9. November 2015 Oleksii Oleksenko Abstract The general tendency in modern hardware is an increase in fault rates, which is caused by the decreased operation voltages and feature sizes. Previously, the issue of hardware faults was mainly approached only in high-availability enterprise servers and in safety-critical applications, such as transport or aerospace domains. These fields generally have very tight requirements, but also higher budgets. However, as fault rates are increasing, fault tolerance solutions are starting to be also required in applications that have much smaller profit margins. This brings to the front the idea of software-implemented hardware fault tolerance, that is, the ability to detect and tolerate hardware faults using software-based techniques in commodity CPUs, which allows to get resilience almost for free. Current solutions, however, are lacking in performance, even though they show quite good fault tolerance results. This thesis explores the idea of using the Single Instruction Multiple Data (SIMD) technology for executing all program’s operations on two copies of the same data.
    [Show full text]
  • Quantifying Complexity and Code Reuse in Malware Development Alejandro Calleja, Juan Tapiador, and Juan Caballero
    1 The MalSource Dataset: Quantifying Complexity and Code Reuse in Malware Development Alejandro Calleja, Juan Tapiador, and Juan Caballero Abstract—During the last decades, the problem of malicious platforms as soon as these acquired a substantial user base, and unwanted software (malware) has surged in numbers and such as the recent case of smartphones [7]. sophistication. Malware plays a key role in most of today’s cyber attacks and has consolidated as a commodity in the underground The surge in number, sophistication, and repercussion of economy. In this work, we analyze the evolution of malware malware attacks has gone hand in hand with much research, from 1975 to date from a software engineering perspective. We both industrial and academic, on defense and analysis tech- analyze the source code of 456 samples from 428 unique families niques. The majority of such investigations have focused on and obtain measures of their size, code quality, and estimates of the development costs (effort, time, and number of people). Our binary analysis, since most malware samples distribute in results suggest an exponential increment of nearly one order of this form. Only very rarely researchers have access to the magnitude per decade in aspects such as size and estimated effort, source code and can report insights gained from its inspection. with code quality metrics similar to those of benign software. (Notable exceptions include the analysis of the source code of We also study the extent to which code reuse is present in our 4 IRC bots by Barford and Yegneswaran [8] and the work of dataset.
    [Show full text]
  • Ultrasparc T1™ Supplement to the Ultrasparc Architecture 2005
    UltraSPARC T1™ Supplement to the UltraSPARC Architecture 2005 Draft D2.1, 14 May 2007 Privilege Levels: Hyperprivileged, Privileged, and Nonprivileged Distribution: Public Sun Microsystems, Inc. 4150 Network Circle Santa Clara, CA 95054 U.S.A. 650-960-1300 Part No.No: 8xx-xxxx-xx819-3404-05 ReleaseRevision: 1.0, Draft 2002 D2.1, 14 May 2007 ii UltraSPARC T1 Supplement • Draft D2.1, 14 May 2007 Copyright 2002-2006 Sun Microsystems, Inc., 4150 Network Circle • Santa Clara, CA 950540 USA. All rights reserved. This product or document is protected by copyright and distributed under licenses restricting its use, copying, distribution, and decompilation. No part of this product or document may be reproduced in any form by any means without prior written authorization of Sun and its licensors, if any. Third-party software, including font technology, is copyrighted and licensed from Sun suppliers. Parts of the product may be derived from Berkeley BSD systems, licensed from the University of California. UNIX is a registered trademark in the U.S. and other countries, exclusively licensed through X/Open Company, Ltd. For Netscape Communicator™, the following notice applies: Copyright 1995 Netscape Communications Corporation. All rights reserved. Sun, Sun Microsystems, the Sun logo, Solaris, and VIS are trademarks, registered trademarks, or service marks of Sun Microsystems, Inc. in the U.S. and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the U.S. and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc The OPEN LOOK and Sun™ Graphical User Interface was developed by Sun Microsystems, Inc.
    [Show full text]
  • Idisa+: a Portable Model for High Performance Simd Programming
    IDISA+: A PORTABLE MODEL FOR HIGH PERFORMANCE SIMD PROGRAMMING by Hua Huang B.Eng., Beijing University of Posts and Telecommunications, 2009 a Thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in the School of Computing Science Faculty of Applied Science c Hua Huang 2011 SIMON FRASER UNIVERSITY Fall 2011 All rights reserved. However, in accordance with the Copyright Act of Canada, this work may be reproduced without authorization under the conditions for Fair Dealing. Therefore, limited reproduction of this work for the purposes of private study, research, criticism, review and news reporting is likely to be in accordance with the law, particularly if cited appropriately. APPROVAL Name: Hua Huang Degree: Master of Science Title of Thesis: IDISA+: A Portable Model for High Performance SIMD Pro- gramming Examining Committee: Dr. Kay C. Wiese Associate Professor, Computing Science Simon Fraser University Chair Dr. Robert D. Cameron Professor, Computing Science Simon Fraser University Senior Supervisor Dr. Thomas C. Shermer Professor, Computing Science Simon Fraser University Supervisor Dr. Arrvindh Shriraman Assistant Professor, Computing Science Simon Fraser University SFU Examiner Date Approved: ii Declaration of Partial Copyright Licence The author, whose copyright is declared on the title page of this work, has granted to Simon Fraser University the right to lend this thesis, project or extended essay to users of the Simon Fraser University Library, and to make partial or single copies only for such users or in response to a request from the library of any other university, or other educational institution, on its own behalf or for one of its users.
    [Show full text]
  • HPC-Event-Return-Of-Vector-20160801
    The OrionX Constellation: Data Center High Performance Computing The Return of Vector Processing Shahin Khan Digital transformation, cloud computing and application elasticity, open source software, and new app areas like AI and IoT are driving a renaissance in system architecture. This is an area of interest and research for us at OrionX. Vector processing was an interesting topic to re-emerge recently. First during the International Supercomputing Conference (ISC), and again in various announcements in implicit and explicit ways. On the Monday of the ISC conference, a new leader on the TOP500 list was announced. The Sunway TaihuLight system uses a new processor architecture that is Single-Instruction-Multiple-Data (SIMD) with a pipeline that can do eight 64-bit floating-point calculations per cycle. 10,649,600 computing cores comprising 40,960 nodes produce 93 petaflop/s running the LINPACK benchmark. Later that day, at the “ISC 2016 Vendor Showdown”, NEC had a presentation about its project “Aurora”. This project aims to combine x86 clusters and NEC’s vector processors in the same high bandwidth system. NEC has a long history of advanced vector processors with its SX architecture. Among many achievements, it built the Earth Simulator, a vector-parallel system that was #1 on the TOP500 list from 2002 to 2004. At its debut, it had a substantial (nearly 5x) lead over the previous #1. Vector Processing and Parallelism Vector processing is a time-honored system architecture that started the supercomputing market, starting with the CDC STAR-100 system (STrings and ARrays, performing at 100 million floating point operations per second), and then led by the legendary Seymour Cray and his superb team.
    [Show full text]
  • 10Th Gen Intel® Core™ Processor Families Datasheet, Vol. 1
    10th Generation Intel® Core™ Processor Families Datasheet, Volume 1 of 2 Supporting 10th Generation Intel® Core™ Processor Families, Intel® Pentium® Processors, Intel® Celeron® Processors for U/Y Platforms, formerly known as Ice Lake July 2020 Revision 005 Document Number: 341077-005 Legal Lines and Disclaimers You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. Intel technologies' features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No computer system can be absolutely secure. Check with your system manufacturer or retailer or learn more at intel.com. Intel technologies may require enabled hardware, specific software, or services activation. Check with your system manufacturer or retailer. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps Copies of documents which have an order number and are referenced in this document may be obtained by calling 1-800-548- 4725 or visit www.intel.com/design/literature.htm.
    [Show full text]