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Opensparc T1 OpenSPARC T1 Raju Joshi Sun Microsystems, Inc. Agenda • Changing Marketplace driving CMT • UltraSPARC T1 • OpenSPARC T1 Details • OpenSPARC Community 2 Mapping Workloads to System Requirements Highly Threaded Search Data Warehousing Web Proxy Caching Meteorology/Climate Simulation Web Data Analysis J2EE Appl Servers Web Serving Nuclear Simulation/Weapons Modeling Streaming Media OLTP Database Security Datata File Server Bioinformatics Seismic Analysis, ERP (SAP R3) Directory Reservoir Modeling Application Compilation Storage Thermodynamics Batch Compute Grid Network Intensive HPC Application Genomics Compute Intensive HPC Application Compute EAI Servers Structural Analysis Electronic Design Simulation Workgroup Application Development Financial Risk/Portfolio Analysis Monte Carlo Simulation Commercial Technical Single Threaded Single Threaded 3 Attributes of Commercial Workloads Web Services Client Server Data Warehouse TIER1 TIER2 TIER3 SAP 2T SAP 3T DSS Attribute Web App Serv Data (DB) (TPC-H) (Web99) (JBB) (TPC-C) Application Web Server OLTP ERP ERP DSS Category Server Java Instruction-level Parallelism Low Low Low Medium Low High Thread-level Parallelism High High High High High High Instruction/Data Working Set Large Large Large Medium Large Large Data Sharing Low Medium High Medium High Medium 4 Memory Bottleneck Relative Performance 10000 CPU Frequency 2x Every 2 Years DRAM Speeds 1000 100 Gap 10 2x Every 6 Years 1 1980 1985 1990 1995 2000 2005 Source: Sun World Wide Analyst Conference Feb. 25, 2003 5 Typical Complex High Frequency Processor Time Saved Thread C M C M C M Time Memory Latency Compute Thread C M C M C M Time Memory Latency Compute HURRY UP AND Note: Up to 75% Cycles Waiting for WAIT! Memory 6 Chip Multithreading (CMT) Thread 4 C M C M C M Thread 3 C M C M C M Thread 2 C M C M C M Thread 1 C M C M C M Time Memory Latency Compute 7 CMT – Multiple Multithreaded Cores Thread 4 Thread 3 Core 8 Thread 2 Thread 1 Thread 4 Thread 3 Core 7 Thread 2 Thread 1 Thread 4 Thread 3 Core 6 Thread 2 Thread 1 Thread 4 Thread 3 Core 5 Thread 2 Thread 1 Thread 4 Thread 3 Core 4 Thread 2 Thread 1 Thread 4 Thread 3 Core 3 Thread 2 Thread 1 Thread 4 Thread 3 Core 2 Thread 2 Thread 1 Thread 4 Thread 3 Core 1 Thread 2 Thread 1 Time Memory Latency Compute 8 Four Converging Trends Network Computing Is Moore’s Law Thread Rich A fraction of the die can TM already build a good processor Web services, Java core; how am I going to use a applications, database billion transistors? transactions, ERP . Worsening Growing Complexity Memory Latency of Processor Design It’s approaching 1000s Forcing a rethinking of of CPU cycles! Friend or foe? processor architecture – modularity, less is more, time-to-market 9 Mapping Workloads to System Requirements Highly Threaded Search Data Warehousing Web Proxy Caching Meteorology/Climate Simulation Web Data Analysis J2EE Appl Servers Web Serving Nuclear Simulation/Weapons Modeling Streaming Media OLTP Database UltraSPARC T1 Workload Security Datata File Server Bioinformatics Seismic Analysis, ERP (SAP R3) Directory Reservoir Modeling e Anpvpleicaltoionp Ceompilation Storage Thermodynamics Batch Compute Grid Network Intensive HPC Application Genomics Compute Intensive HPC Application Compute EAI Servers Structural Analysis Electronic Design Simulation Workgroup Application Development Financial Risk/Portfolio Analysis Monte Carlo Simulation Commercial Technical Single Threaded Single Threaded 10 UltraSPARC T1 Processor • SPARC V9 implementation DDR-2 DDR-2 DDR-2 DDR-2 SDRAM SDRAM SDRAM SDRAM • Up to eight 4-way multi- threaded cores for up to 32 simultaneous threads • All cores connected through a 134.4GB/s crossbar switch L2$ L2$ L2$ L2$ FPU • High-bandwidth 12-way associative Xbar 3MB Level-2 cache on chip C1 C2 C3 C4 C5 C6 C7 C8 • 4 DDR2 channels (23GB/s) • Power : < 80W Sys I/F Buffer Switch • ~300M transistors Core • 378 sq. mm die 1 of 8 Cores BUS 11 OpenSPARC T1 • Open Source of UltraSPARC T1 > 64 Bit, 32 Thread CPU design, and it's FREE ! • Includes > Chip RTL design > Verification environment > Verification test suites > Synthesis scripts > SPARC Architecture simulator > Documentation • Website: > http://www.opensparc.net • Licensed under GPLv2 12 OpenSPARC T1: Centre for Innovation Applications CoolTools Universities Multiple OS porting Implementation FPGA, ASIC, Custom Architecture EDA Companies and Performance Micro-Architecture and Bus Interfaces 13 OpenSPARC T1 – Specifications • UltraSPARC Architecture 2005 - ISA specification • UltraSPARC T1 specific ISA supplement • HyperVisor API for ports to Multiple OSs 14 OpenSPARC T1 – Hardware Engineering • Chip Design/Verification Package Includes > Chip RTL design > Verification environment > Verification test suites > Synthesis scripts for all RTL with exception of some RAM models > SPARC Architecture simulator > Documentation > External Bus Specification > Megacell Specification > Design & Verification User's Guide > Data Sheet 15 OpenSPARC T1 – Software Engineering and Architects • Architecture and Performance Modeling Package includes: > SAM - SPARC Architecture Model > SAS - Instruction accurate SPARC Architecture Simulator (Includes Source code) > Solaris Images for simulation: Solaris 10, Hypervisor, OBP images > Legion – SPARC system simulation model for Software Developers > Documentation 16 OpenSPARC T1: EDA tools Overview • Verification Environment > Highly automated Design and Verification environment > Configurable : select > one core without I/O > full chip with 8 cores and I/O > Co-simulation with SPARC Architecture Simulator (Instruction level) > Supports regressions running on many machines • Front end Design/Verification Tools > Design: Verilog RTL > Testbenches: Verilog, PLI in C/C++ > Optional Vera – Monitors, Vera Object Coverage > Synthesis using Synopsys Design Compiler or Synplicity for FPGA • Systems supported > SPARC CPU based systems with Solaris 9 or Solaris 10 17 CoolTools for UltraSPARC T1 • Sun Studio 11 Compiler and tools > Dprofile – data space profiling > Cool Threads Programming > Auto-parallelizing C, C++, Fortran compilers > OpenMP – Parallel Programming API for MP • Java Platform • MediaLib > Libraries for Media applications – Video, Audio, Signal Processing, etc. > Performance tuned for UltraSPARC T1 • System Tuning tools > CoolThread Selection Tool 18 OpenSPARC Community Sharing Creates Communities Communities Create Markets GOALS > Increase participation in processor architecture > Eliminate barriers > Improve collaboration and cooperation > Enable community members to build new designs > Encourage innovation > Foster new products to market HELP OUR COMMUNITY GROW > Check out our general forum > Send us ideas > Collaborate with the community > Join our mailing list and community > Expand the eco-system: > Add OpenSource Test Technology and tools for OpenSPARC T1 to www.opensparc.net 19 About the Community: opensparc.net Clustermaps for http://opensparc.net Innovation will happen everywhere Innovation Happens Everywhere 20 64 bit, 32 threads, www.opensparc.frneete Get the code. Start innovating. Multi-threaded algorithms and applications, Operating Systems, System Architecture, EDA Tools/Methodology, Circuit implementations, Compiler Tools, System Modeling, System on a Chip, Debug tools, Performance analysis and benchmarking Summary • Future of Processor design is CMT • OpenSPARC T1 will drive innovations in many areas • Join the OpenSPARC Community and Contribute to http://www.opensparc.net 22 OpenSPARC T1 Raju Joshi E-mail: [email protected] Sun Microsystems, Inc..
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