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Ppc440x5 CPU Core User's Manual Preliminary

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Ppc440x5 CPU Core User's Manual Preliminary Title Page PPC440x5 CPU Core User’s Manual Preliminary SA14-2613-03 July 15, 2003 ® Copyright and Disclaimer © Copyright International Business Machines Corporation 2003 All Rights Reserved Printed in the United States of America July 2003 The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both. IBM IBM Logo CoreConnect PowerPC PowerPC logo PowerPC Architecture RISCTrace RISCWatch Other company, product, and service names may be trademarks or service marks of others. The information contained in this document is subject to change or withdrawal at any time without notice and is being provided on an "AS IS" basis without warranty or indemnity of any kind, whether express or implied, including without limitation, the implied warranties of non-infringement, merchantability, or fitness for a particular purpose. Any products, services, or programs discussed in this document are sold or licensed under IBM's standard terms and conditions, copies of which may be obtained from your local IBM representative. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. Without limiting the generality of the foregoing, any performance data contained in this document was determined in a specific or controlled environment and not submitted to any formal IBM test. Therefore, the results obtained in other operating environments may vary significantly. Under no circumstances will IBM be liable for any damages whatsoever arising out of or resulting from any use of the document or the information contained herein. While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. Note: This document contains information on products in the sampling and/or initial production phases of development. This information is subject to change without notice. Verify with your IBM field applications engineer that you have the latest version of this document before finalizing a design. IBM Microelectronics Division 1580 Route 52, Bldg. 504 Hopewell Junction, NY 12533-6351 The IBM home page can be found at http://www.ibm.com The IBM Microelectronics Division home page can be found at http://www.ibm.com/chips title.fm. July 15, 2003 User’s Manual Preliminary PPC440x5 CPU Core Contents Figures ..........................................................................................................................................15 Tables ............................................................................................................................................19 About This Book ..........................................................................................................................23 1. Overview .................................................................................................................................. 27 PPC440x5 Features ............................................................................................................................... 27 The PPC440x5 as a PowerPC Implementation ..................................................................................... 29 PPC440x5 Organization ......................................................................................................................... 30 Superscalar Instruction Unit ............................................................................................................ 30 Execution Pipelines ......................................................................................................................... 31 Instruction and Data Cache Controllers ........................................................................................... 31 Instruction Cache Controller (ICC) .............................................................................................. 31 Data Cache Controller (DCC) ...................................................................................................... 32 Memory Management Unit (MMU) .................................................................................................. 32 Timers .............................................................................................................................................. 34 Debug Facilities ............................................................................................................................... 34 Debug Modes .............................................................................................................................. 34 Development Tool Support .......................................................................................................... 35 Core Interfaces ....................................................................................................................................... 35 Processor Local Bus (PLB) ............................................................................................................. 36 Device Control Register (DCR) Interface ........................................................................................ 36 Auxiliary Processor Unit (APU) Port ................................................................................................ 36 JTAG Port ........................................................................................................................................ 37 2. Programming Model ............................................................................................................... 39 Storage Addressing ................................................................................................................................ 39 Storage Operands ........................................................................................................................... 39 Effective Address Calculation .......................................................................................................... 41 Data Storage Addressing Modes ................................................................................................ 41 Instruction Storage Addressing Modes ....................................................................................... 41 Byte Ordering .................................................................................................................................. 42 Structure Mapping Examples ...................................................................................................... 43 Instruction Byte Ordering ............................................................................................................. 44 Data Byte Ordering ...................................................................................................................... 45 Byte-Reverse Instructions ........................................................................................................... 46 Registers ................................................................................................................................................ 47 Register Types ................................................................................................................................ 51 General Purpose Registers ......................................................................................................... 51 Special Purpose Registers .......................................................................................................... 51 Condition Register ....................................................................................................................... 52 Machine State Register ............................................................................................................... 52 Device Control Registers ............................................................................................................. 52 Instruction Classes ................................................................................................................................. 52 Defined Instruction Class ................................................................................................................. 53 Allocated Instruction Class .............................................................................................................. 53 Preserved Instruction Class ............................................................................................................. 54 ppc440x5TOC.fm. Contents July 15, 2003 Page 3 of 573 User’s Manual PPC440x5 CPU Core Preliminary Reserved Instruction Class ............................................................................................................. 55 Implemented Instruction Set Summary ................................................................................................. 55 Integer Instructions ......................................................................................................................... 56 Integer Storage Access Instructions ........................................................................................... 56 Integer Arithmetic Instructions .................................................................................................... 57 Integer Logical Instructions ........................................................................................................
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