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(12) United States Patent (10) Patent No.: US 6,599,816 B2 Sueoka Et Al

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(12) United States Patent (10) Patent No.: US 6,599,816 B2 Sueoka Et Al USOO65998 16B2 (12) United States Patent (10) Patent No.: US 6,599,816 B2 Sueoka et al. (45) Date of Patent: Jul. 29, 2003 (54) METHOD OF MANUFACTURING SILICON 6,162,708 A 12/2000 Tamatsuka et al. ......... 438/503 EPITAXIAL WAFER FOREIGN PATENT DOCUMENTS (75) Inventors: Kouji Sueoka, Ashiya (JP); Masanori JP 10-229093 8/1998 ......... HO1 L/21/322 Akatsuka, Osaka (JP); Yasuo Koike, JP 11-1894.93 7/1999 Kashima (JP) JP 2000-6828O 3/2000 (73) Assignee: Sumitomo Metal Industries, Ltd., OTHER PUBLICATIONS Osaka (JP) “Solid State Phenomena” vol. 57–58 (1997), pp. 53–62 By S. Sadamitsu et al. (*) Notice: Subject to any disclaimer, the term of this sk - patent is extended or adjusted under 35 cited by examiner U.S.C. 154(b) by 0 days. Primary Examiner-George Fourson Assistant Examiner Khiem Nguyen (21) Appl. No.: 09/800,514 74) Attorney,y, AgAgent, or Firm-Armstrong,9. Westerman & (22) Filed: Mar. 8, 2001 Hattori, LLP (65) Prior Publication Data (57)57 ABSTRACT US 2001/0021574 A1 Sep. 13, 2001 A method is designed to manufacture a Silicon epitaxial p. 13, wafer exhibiting Sufficient gettering capability from the (30) Foreign Application Priority Data initial Stage of the device process. Specifically, the method is to manufacture the Silicon wafer with a nitrogen concen Mar. 9, 2000 (JP) ....................................... 2000-065112 tration of at least 1x10' atoms/cm and an OXygen concen (51) Int. Cl." .............................................. H01L 21/322 tration of 10-18x10" atoms/cm by annealing at a tem (52) U.S. Cl. ................ 438/471; 438/143,438/509 perature of 800-1,100° C. after epitaxial growth treatment, (58) Field of Search .......................... 48/503, 502, 471, satisfying the following equation (a), 48/916, 505, 509, 143, FOR 144 s33-((T-800)/100) (a) (56) References Cited wherein T( C.) is temperature, and t(hr) is time, thereby U.S. PATENT DOCUMENTS manufacturing a high yield Semiconductor device. 5,961,713 A * 10/1999 Wijaranakula ................. 117/2 6 Claims, 2 Drawing Sheets OOO w IG Capability, Not Exhibita w Y. Lx D 0. 6- 1 O 7 S IG Capability oS Exhibit Example of Invention td - O v O a. Comparative N Example (4) w \ f OO Os, Comparative - 3 O Example (2) s Y. S. O O \, CO Ety Comparative s xample (3) Example (1) O 6 7 8 9 O O O O O O Density of Oxide Precipitates (/cm) U.S. Patent Jul. 29, 2003 Sheet 1 of 2 US 6,599,816 B2 F.G. 1 OOO IG Capability, Not Exhibit Y. Lx D = 1 O7 e IG Capability Y, oS Exhibit N Y. Example of Invention C O a. Comparative fC OO Exampleple (4)(4 Comparative . 3 Example (2) \, S. O O CO Comparative Comparative Example (3) Example (1) O O Density of Oxide Precipitates (/cm) U.S. Patent Jul. 29, 2003 Sheet 2 of 2 US 6,599,816 B2 FIG 2 Sc. O e C c .9 O t Not Observed v (4) Example of (1) (2) (3) Invention Comparative Examples US 6,599,816 B2 1 2 METHOD OF MANUFACTURING SILICON silicon) or well diffusion layer. The DZ layer serves as a EPITAXIAL WAFER device active region, thereby providing a reduction in crystal defects. However, according to higher density of integration, a TECHNICAL FIELD high-energy ion implantation method has been used to form well diffusion layer, and when the device proceSS is carried The present invention relates to a method of manufactur out at a lower temperature than 1,000 C. in order to ing a Silicon epitaxial wafer, used as a Substrate for circuit manufacture device with shallower junction depth, oxygen devices Such as LSI (large Scale integrated circuit), having a is not diffused sufficiently, and thus, the DZ layer is not Silicon epitaxial film formed thereon, and more particularly, formed satisfyingly. With this reason, it has become difficult to a method of manufacturing a Silicon epitaxial wafer to to SuppreSS crystal defects in the device active region. exhibit Sufficient gettering capability from the initial Stage of Accordingly, the oxygen concentration of the Substrate device manufacturing process by heat treatment under pre was reduced, but the result was unsatisfactory Since the determined condition after epitaxial growth treatment. crystal defects could not be Suppressed Sufficiently, and the performance of the wafer was deteriorated by oxygen reduc BACKGROUND OF THE INVENTION 15 tion. Therefore, an epitaxial wafer on which Si epitaxial layer including few crystal defects on the Silicon Slice to be AS the high integration trend of Silicon Semiconductor wafer Substrate was grown has been developed and has been integrated circuit devices has been rapidly progressed, a used in highly integrated devices. silicon wafer from which devices are formed is subjected to However, since a high temperature treatment of 1,050-1, increasingly Severe specifications. In a device active region 200 C. is applied to the process of forming an epitaxial of the highly integrated devices, Since the existence of layer on the Surface of the wafer, the oxide precipitation crystal defects or metal impurities other than a dopant within the wafer is significantly Suppressed during continu increases leakage current in the P/Njunction or degrade gate ing device process. This phenomenon was reported that in oxide film characteristics of MOS devices, the crystal usual cases except for the case of a wafer with a high doping defects or the metal impurities is Subject to more rigorous 25 concentration of boron (for example, the case of a resistivity limitation than before. <20 m G2cm), it became remarkable, and thus, gettering Conventionally, a wafer produced by Slicing a Silicon effect for metal contamination could not be expected (S. Single crystal obtained through the Czochralski method has Sadamitsu et al., Solid State Phenomena Vol. 57–58 (1997) been used for highly integrated devices. Generally, this p. 53–62). wafer contains over-Saturated interstitial oxygen at a con AS described in the above, when an epitaxial wafer is centration of 10–18x10"7 atoms/cm. Although oxygen is adopted for a highly integrated device, gettering effect for effective for enhancing the Strength of a wafer by preventing metal contamination by a high temperature treatment during generation of dislocation or for providing gettering effect, epitaxial growth treatment cannot be expected. As a oxygen is well known to deposit in the form of an oxide and consequence, a Silicon Single crystal doped with a nitrogen to induce crystal defects Such as dislocations or Stacking 35 concentration of at least 10" atoms/cm was suggested for faults due to heat histories during production of a device. a Substrate of an epitaxial wafer (for example, Japanese The oxide precipitates and the crystal defects generated Patent Laid-Open No. 11-189493). within a wafer sufficiently away from the device active When the Suggested Silicon Single crystal is used, in case region are allowed to enjoy the function of intrinsic gettering of an epitaxial wafer which was sliced from the above (hereinafter referred to as “IG”) having the effect of getter 40 Silicon Single crystal and conducted with film-forming on ing metal contamination. Therefore, it is understood that in the Surface, the oxide precipitates can exist in a density of order to manufacture a high yield device, the existence of the about 10/cm at a previous step before the device process oxide precipitates or the crystal defects within a wafer is because the oxygen doped during crystal-producing Step can indispensable. Hereinafter, the ability that a silicon wafer Serve to promote oxide precipitation. Further, those oxide exhibits IG function is called “IG capability”. 45 precipitates grow in accordance with the device process, and The inventors Suggested the IG capability evaluation form Sufficient density and size for gettering, for example, method even taking micro-oxide-precipitates that were hard thereby satisfying the above equation (b). Therefore, when to be observed in the past into consideration. This IG the Suggested Silicon Single crystal is used, an epitaxial capability evaluation method is based on the calculation wafer with the excellent IG capability can be obtained in result from the size distribution of oxide precipitates by a 50 accordance with the device process. calculator simulation using Fokker-Planck equation (refer to However, even if an epitaxial wafer is sliced from a Japanese Patent Application No. 10-2366.62). Specifically, Silicon Single crystal doped with nitrogen, it is difficult to this method is to evaluate whether the following equation (b) obtain an epitaxial wafer with the density and the size of the is Satisfied or not, oxide precipitates Satisfying the above equation (b) before 55 the device process. With this reason, there is a problem that LXD's 10x107 (b) it is easily influenced by metal contamination because it is difficult to obtain the sufficient IG capability in the initial wherein L(nm) is the diagonal length of oxide precipitates, Stage of the device process. and D(/cm) is the precipitate density. If the above equation SUMMARY OF THE INVENTION is Satisfied, the excellent IG capability can be obtained. 60 On the other hand, a DZ (denuded Zone) layer which is With the foregoing insufficient IG capability problem in free of crystal defects and which has a thickness of about the initial Stage of the device process in the above-described tens of (um is formed near the wafer surface by diffusion of epitaxial wafer in View, the present invention is aimed at to oxygen to the outside, Since the wafer is heat-treated at a provide a method of manufacturing a Silicon epitaxial wafer, high temperature of 1,100–1,200 C.
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