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United States Patent [191 Patent Number: 5,279,987 Lechaton Et A1 US005279987A United States Patent [191 Patent Number: 5,279,987 Lechaton et a1. Date of Patent: Jan. 18, 1994 [54] FABRICATING PLANAR Autodoping from Arsenic Buried Layer by Selective COMPLEMENTARY PA'I'I‘ERNED Epitaxy Capping”, IEEE Electron Device Letters, vol. SUBCOLLECI‘ORS WITH SILICON 11, No. 3, Mar. 1990, 123-125. EPITAXIAL LAYER Y. Kobayashi, et al., Entitled “High Performance LSI [75] Inventors: John S. Lechaton; Shaw-Ning Mei; Performance Technology: SST CBI-CMOS”, IEDM, Dominic J. Schepis, all of 1988, pp. 760-763. Wappingers Falls; Mithkal M. T. Ishii, et al., Entitled “Silicon Epitaxial Wafer with Smadi, Beacon, all of N.Y. Abrupt Interface by Two-Step Epitaxial Growth Tech nique”, J. Electrochemical Soc., vol. 122, No. 11, 1975, [73] Assignee: International Business Machines pp. 1523-1531. Corporation, Armonk, N.Y. T. J. Donahue, et al., Entitled “Low Temperature Sili [21] Appl. No.: 785,656 con Epitaxy Deposited by Very Low Pressure Chemi [22] Filed: Oct. 31, 1991 cal Vapor Deposition”, J. Electrochem. Soc., vol. 133, No. 8, Aug. 1986, pp. 1697-1701. [51] Int. 01.5 ........................................... H01L 21/20 H-R. Chang, Entitled “Autodoping in Silicon Epi [52] U.S. Cl. ...................................... .. 437/95; 437/59; taxy”, The Journal of Electrochemical Society, vol. 437/108; 148/DIG. 25 132, No. 1, pp. 219-224, Jan. 1985. [58] Field of Search ..................... .. 437/54, 59, 95, 97, 437/108, 112, 161, 952; l48/DIG. 7, DIG. 15, Primary Examiner—-Brian E. Hearn DIG. 25, DIG. 9 Assistant Examiner-C. Chaudhari Attorney, Agent, or Firm—Jeffrey L. Brandt; Harold [56] References Cited Huberfeld U.S. PATENT DOCUMENTS [57] ABSTRACT 3,716,422 2/1973 Ing et al. ............................. .. 437/97 4,578,128 3/1986 Mundt et a1. .. ..... .. 437/95 A process, compatible with bipolar and CMOS silicon 4,579,609 4/1986 Reif et a1. ..... .. 437/95 device manufacturing for fabricating complementary 4,696,701 9/1987 Sullivan ........ .. 437/95 buried doped regions in a silicon substrate. An N+ 4,830,973 5/1989 Mastroianni 437/31 doped region (12) is formed in the silicon substrate by 4,859,626 8/1989 Wise ............. .. 437/95 known methods of arsenic doping and drive in. This is 4,894,349 1/1990 Saito et a1. 437/95 followed by depositing a ?rst thin epitaxial silicon cap FOREIGN PATENT DOCUMENTS layer (14), under conditions of minimum N+ autodop 0320070 12/1988 European Pat. Off. ing. Part thickness of this ?rst epilayer is converted to 0148620 6/1988 Japan ................................ 437/95 oxide (18), and the oxide is patterned to provide aper tures in an area where it is desired to form a P+ region. OTHER PUBLICATIONS A P source material (20) is deposited and a drive in IBM Technical Disclosure Bulletin, by D. J. Fleming, anneal is used to dope the silicon with P in the areas of et al., Entitled “Prevention of Audodoping During the oxide aperture opening. Subsequent to drive in, the Silicon Epitaxial Deposition” vol. 20, No. 3, Aug. 1977, dopant source layer and the oxide mask is removed by pp. 1083-1084. IBM Technical Disclosure Bulletin, Entitled “Low wet etching. An oxide is regrown on the surface, includ Temperature Fabrication Process for High-Perfor ing the P+ region (22), and subsequently the oxide mance MOSFETs,” vol. 30, No. 9, Feb. 1988, pp. layer is stripped in dilute hydro?uoric acid. Next a 450-451. second epitaxial silicon layer (28) is deposited to make Tzu-Yin Chiu, et al., “Non-Overlapping Super Sel up the total epi thickness to a desired value, using pro f-Aligned BiCMOS with 87ps Low Power ECL”, cess conditions of minimum P doping. IEDM, 1988, pp. 752-755. Tzu-Yin Chiu, et al., Entitled “Suppression of Lateral 8 Claims, 3 Drawing Sheets US. Patent Jan. 18, 1994 Sheet 1 of 3 5,279,987 FIG. 3 \ \ \\\\\\\\\\\\ \ \- ~ 12 ' \ \ \\ \ \ 2334" FIG. g2, // ' ‘ Si US. Patent Jan. 18, 1994 Sheet 2 of 3 5,279,987 85018 _ CONCENTRATION ( /CM‘X) 85017.. FIG- 7 550 TEMPERATURE750 850 950 ( c) 1150 AUTODOPlNG OF ARSENIC AND BORON BORON 1019 II‘IITI‘T[Till CONCENTRATION ( /CM3) T018 I 5103 1104 1.5104 2104 HG 8D X X X X US. Patent Jan. 18, 1994 Sheet 3 of 3 5,279,987 1021. 1020 ;- ARSENIC ______ 19 '_ 'fu ‘ 1O : II, CONCENTRATION ‘ ; < m ‘0 1s 5; g I 10 17 ' {I l I 1016 h x103 1104 1.5X104 HQ 88 DEPTH IN ANGSTROM 1020 1019 IIIIIlllll CONCENTRATION < m W8 5x105 1x104 DEPTH IN ANGSTROM FIG. 8C 5,279,987 1 2 ing in low autodoping of both boron and arsenic is FABRICATING PLANAR COMPLEMENTARY dif?cult. PA'ITERNED SUBCOLLECTORS WITH SILICON The epitaxial deposition of silicon has been exten EPITAXIAL LAYER sively discussed in the literature, especially the process conditions such as precleans, temperature, pressure, CROSS-REFERENCE TO RELATED ?ow and gases, and their effect on growth rates and the APPLICATIONS epitaxy ?lm properties. Another area wherein autodoping is an important This application is related to co-pending application factor is in the manufacture of complementary bipolar Ser. No. 59,377, ?led Oct. 18, 1988. and BiCMOS devices, for which highly doped pat FIELD OF THE INVENTION terned regions of both N and P type are required in the manner described herein above. US. Pat. No. 4,830,973 The present invention relates generally to manufac to Mastroianni, for example, shows methods and means turing semiconductor devices and more particularly to for forming merged bipolar and MOS devices, but fails forming patterned complementary doped regions useful 15 to teach how to avoid the autodoping when both N and as sub-collectors for complementary bipolar or merged P doped regions are simultaneously present and sub complementary bipolar complementary MOS (c-BiC jected to an epitaxial deposition process. MOS) devices. Chiu et al., (IEDM 1988, p752; also, IEEE Electron Dev. Let. 1990, p123) teaches the fabrication of a self BACKGROUND OF THE INVENTION aligned BiCMOS device by deposition of a thin epitaxy A necessary step in the fabrication of high perfor silicon cap layer selectively over an arsenic doped re mance complementary bipolar or c-BiCMOS transistors gion, followed by non-selective deposition of an epitax is the formation of highly doped co-planar sub-collector ial layer to desired thickness. Next, a boron doped re regions of both N and P type, with an epitaxial silicon gion is formed by implantation through the epitaxy layer disposed thereover. A major problem in the depo 25 layer. However, the Chiu et al. process suffers from the sition of a silicon epitaxial layer over a highly doped disadvantage that it is limited to implantation method sub-collector region is the evaporative loss of dopants for doping, and hence can not achieve very high boron from the region into the CVD chamber, and the resul concentration (greater than 10*19 atoms/cc). Boron tant unwanted doping of areas adjacent to the region. concentration by implantation is usually restricted to This problem, referred to as autodoping, has been ad 5 X 10‘18 atoms/cc to avoid damage to the crystal, dressed extensively in the prior art. The avoidance of whereas higher concentrations are typically desirable. autodoping is more dif?cult when both N and P type In addition the structure, consisting of the doped re regions are simultaneously present, because of their gions with an epitaxial silicon overlayer, resulting from different autodoping responses under the same epitaxial this Chiu et a1. process, is non-planar. process conditions. 35 Thus the present invention recognizes that it would The prior art relating to autodoping discusses the be particularly valuable in the art, especially as it relates to the formation of complementary circuits, to provide need for a suitable cap layer to reduce the out diffusion a planar device, tightly spaced and highly doped N and of the dopants, and describes various process steps for P regions, desirably with an epitaxy silicon overlayer, forming such a cap layer. A typical cap layer is a thin and a method of fabricating such a device with low layer of epitaxial silicon with low dopant concentration autodoping from the dopant regions. and high resistivity. See for example US. Pat. No. 4,696,701 to Sullivan. OBJECTS OF THE INVENTION Depending on the desired results, the temperature of Accordingly an object of the present invention is to deposition for epitaxial silicon can be selected to be low 45 provide a method of fabricating complementary, (approximately 600 C), medium (approxi- mately 800 C) closely spaced, highly doped regions on a substrate with or high (approximately 1050), and pressure used is typi an epitaxial silicon over-layer of device quality. cally reduced (approximately 100 torr) or atmospheric. It is a further object of this invention to provide such A high vacuum can be used in combination with a low a method with minimal autodoping effects. temperature to improve ?lm quality. 50 It is yet another object of this invention to provide A study on autodoping by H. R. Chang reported the such a method that yields an essentially planar struc difference in the behavior of autodoping between N ture. type impurities such as arsenic and antimony, and P It is yet another object of this invention to provide a type impurities such as boron (The Journal of Electro process compatible with semiconductor device process chemical Society, Vol. 132, No. l, ppg. 219-224, Au ing, especially processing of complementary bipolar gust 1986). The study found that the autodoping of and BiCMOS devices. boron (P dopant) became worse at high temperature It is yet another object of the present invention to and at slow deposition rates of epitaxial silicon.
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