Shining More Light in Epitaxial Thin-Film Silicon Solar Cells

Total Page:16

File Type:pdf, Size:1020Kb

Shining More Light in Epitaxial Thin-Film Silicon Solar Cells Close Shining more light in epitaxial thin-film silicon solar cells Els Parton, Kris Van Nieuwenhuysen, Izabela Kuzma-Filipek, Jan Van Hoeymissen, Maria Recaman, Sivaramakrishnan Radhakrishnan Hariharsudan, Frédéric Dross, Jef Poortmans, Imec, Leuven, Belgium Thin-film epitaxial silicon solar cells are an attractive mid-term future alternative for standard bulk silicon solar cells, but the concept might also be relevant for Si-based photodetectors with improved long-wavelength responsivity. They incorporate much of the process knowledge and advantages of bulk silicon solar cells, but on a potentially cheaper substrate. This article will describe the points of interest and how to solve process problems that are specific to the concept of epitaxial cells. Epitaxial silicon solar cells are based on a thin high-quality epitaxial layer on top of a highly-doped, inactive silicon substrate. Solar cell processing, although with its own specificities, can be similar to what is used for standard double-side contacted bulk silicon solar cells; therefore epitaxial silicon solar cells are also referred to as wafer-equivalent (EpiWE) [1]. A cross-section of a typical epitaxial silicon solar cell can be found in Fig. 1. Figure 1. Cross-section of a typical epitaxial silicon solar cell with an epitaxial stack consisting of a BSF, a p-type active base and an n-type emitter. Depending on the quality of the epitaxial layer, a thickness of 20µm is usually considered as optimal for reducing the cost per Wp. Such a very thin active layer limits light absorption, resulting in a reduced cell performance. Therefore, implementation of a very specific light confinement structure is needed. For example, a light confinement structure consisting of a textured front surface and a porous silicon (PSi) intermediate reflector can be introduced [2]. Porous silicon reflector The role of the PSi reflector is to boost the absorption in the active epitaxial layer of low energy photons, thus increasing the charge carrier generation and resulting in higher short-circuit currents of the cell. The reflector is located at the substrate-epi interface, as can be seen in Fig. 1, and is etched electrochemically into the highly-doped substrate. A very good control of the porosity and the etching depth is needed to form a reflective stack of PSi multi-layers with alternating high and low porosity. The refractive index of the layer is changed, but the optical thickness is kept constant. By applying the quarter wavelength principle, it's possible to create constructive interference of the reflected light for a certain selected wavelength range (Bragg effect). Different types of these "Bragg reflectors" are evaluated. Reflection of the light over 90% for the targeted wavelength range can be obtained in this way (Fig. 2) [3]. Figure 2. Total reflection of an epitaxial silicon solar cell with different types of porous silicon Bragg reflectors at the epi-surface interface. For the wavelength interval between 850nm to 1000nm, a reflection over 90% is obtained. Epitaxial active layers After etching a reflector, the wafers are ready for deposition of the active layers. Layers are grown epitaxially on top of the PSi reflector. Therefore it is crucial that the top-surface is closed before growth starts. This is realized by applying a high-temperature bake, done in situ, just before the epitaxial growth. During this bake, the pore structure changes from columnar to large closed voids with a very thin dense layer at the surface (Fig. 3). Optical properties remain almost identical, but the latter structure makes it possible to grow a very high quality epitaxial stack. Chemical-vapor-deposition (CVD) epitaxial growth is done at an atmospheric pressure at high temperature (1130°C) with trichlorosilane as silicon precursor: this makes it possible to obtain very high growth rates around 4µm/min. Boron doping is used for p-type regions. For n-type regions, arsine (instead of phosphorus which is more common in solar applications), is used for n-type doping to limit the out-diffusion at this high temperature. The CVD process as it is used nowadays is an expensive process, but it allows for the demonstration of the potential of the concept maximum freedom in the doping profile of the epitaxial stack that is applied [4]. Also, n-type and p-type regions can be designed as desired and therefore, a complete stack consisting of a back surface field (BSF), base, emitter, and front surface field can be grown in situ. POCl3 emitter formation and the extensive cleans before and after emitter formation can be avoided. Several cell concepts with varying epitaxial stacks can be assessed. In this article, we will concentrate on two cell concepts: a p- type-base solar cell and an n-type-base solar cell. Figure 3. Reorganization of the porous silicon stack (left: as grown; right: after reorganization) occurs during the high temperature bake in situ just before epitaxial growth of the active layers. Optical properties of the PSi stack remain unaffected. Textured front surface After epitaxial growth, which results in a very smooth top surface, roughening or 'texturing' of the front surface is done. To obtain this texturing, processes that are identical to those used for bulk silicon solar cells can be considered, but silicon removal of the expensive epitaxial stack must be limited to a minimum. Two different texturing processes were applied on the epitaxial layers: plasma texturing [5] and formation of random pyramids [6]. Figure 4. SEM pictures of epitaxial layers after application of the two types of front-surface texturing methods that can be applied for epitaxial silicon solar cells: plasma texturing (left) and random pyramids (right). Plasma texturing has the advantage of being a dry process that is applied on one side. It can be tuned to obtain a reflectance below 16% at a wavelength of 600nm by removing only 1µm of silicon. Moreover, the process is independent of the crystal orientation, which makes it possible to process all kinds of substrates including multi- or even polycrystalline silicon. The resulting textured surface is fractal, which makes it difficult to passivate it efficiently. Figure 4 (left) shows a SEM picture of the epitaxial surface after plasma texturing. Random pyramids are formed by wet etching in an alkaline solution (NaOH). Lower reflectivity can be obtained compared to plasma texturing, but the process can only be used on monocrystalline substrates (and therefore only for the demonstration of the potential of the concept), and a layer of around 4µm of silicon is removed on average during the formation of the pyramids. The main advantage of this process is the smoothness of the structures that are formed: at microscopic level, the surface is smooth (Fig. 4, right) and deposition of additional layers and/or passivation of this surface are easier than for plasma-textured surfaces. Other steps of the solar cell process are identical to standard processes used for bulk silicon solar cells. In this article, we will describe two solar cell concepts: a p-type base solar cell in combination with plasma textured front surface, and an n-type base solar cell in combination with a random pyramid textured front surface. p-type base solar cells with plasma textured front In Fig. 5 (left), a cross-section of a p-type base solar cell is depicted. A porous silicon Bragg reflector is etched in highly-doped substrates. Two types of substrates are used: high-quality (but still highly- boron-doped) monocrystalline substrates to demonstrate the potential of the concept, and low-quality multi-crystalline substrates (from upgraded-metallurgic-grade Si), considered as potentially low-cost. After high-temperature anneal, an epitaxial stack is grown. A highly-doped (1E19 at/cm3) boron layer of 2µm acts as a BSF, and is followed by the active base (boron-doped 1E16 at/cm3) of 20µm. The switch to n-type doping is made in situ and an emitter is formed by only adding a few seconds to the whole process. This is an arsine-doped region of 2µm with a doping concentration of 1E18 at/cm3. Figure 5. Cross-section of a p-type base solar cell with plasma textured front surface (left) and an n-type base solar cell with a random pyramid textured front surface (right). Plasma texturing is performed on this substrate, removing 1µm average of the original 2µm-thick epitaxial emitter. A shallow front surface field is obtained by POCl3 diffusion. As with bulk silicon solar cells, front-surface passivation and anti-reflection coating are obtained by deposition of a silicon nitride layer. Jsc Voc FF Eff. Type of solar cell [mA/cm2] [mV] [%] [%] Epitaxial solar cell on mono-Si substrate with Cu-plated contacts. 31.7 634 80.8 16.2 (best efficiency) Epitaxial solar cell on UMG silicon substrate and 30.6 613 78.1 14.7 screenprinted metal contacts For wafers on high-quality material, metallization is done with copper plating. For cells on low- quality multi-crystalline substrates, the metallization is realized with screen printing. The most important solar cell parameters for these two kinds of cells are summarized in the table. On mono-crystalline substrates, a record efficiency of 16.2% is obtained [6]. For low-cost substrates, with cells realized with processes that are fully compatible with standard industrial bulk solar cell processes, a 14.7% efficiency is obtained [7]. The efficiencies obtained on epitaxially-grown "wafer equivalent" substrates are getting one step closer to the standard bulk silicon technology. n-type cells with random pyramids In Fig. 5 (right), a cross-section of an n-type base solar cell is shown. The porous silicon reflector formation and reorganization is identical to the p-type base solar cell concept.
Recommended publications
  • Epitaxial Wafer Equivalent Solar Cells with Overgrown Sio2 Reflector
    Vailable online at www.sciencedirect.com Energy Procedia 27 ( 2012 ) 38 – 44 SiliconPV: April 03-05, 2012, Leuven, Belgium Epitaxial wafer equivalent solar cells with overgrown SiO2 reflector M. Drießen*, S. Janz, S. Reber Fraunhofer Institute for Solar Energy Systems (ISE), Heidenhofstr. 2, 79110 Freiburg, Germany Abstract Crystalline silicon thin film solar cells, based on the epitaxial wafer equivalent, require a reflecting interlayer between substrate and active layers to increase the generated current and reach similar efficiencies as wafer based solar cells. With the epitaxial lateral overgrowth technique, a reflecting dielectric layer can be implemented. In this paper results of solar cells with overgrown, patterned SiO2 films are shown. A beneficial optical effect due to the interlayer and also a reduced effective diffusion length within the epitaxially grown silicon layer are observed. Cells with reflecting interlayer and non-optimized absorber layer thicknesses therefore exhibit lower efficiencies than cells without SiO2. Slightly higher currents are observed with textured front sides. Significantly increased effective diffusion lengths and cell performances can be reached with non-merged active silicon layers. Reasons might be the avoidance of defects generated at merging points and of unpassivated surface areas in voids remaining where two growth fronts merge. © 2012 PublishedPublished by by Elsevier Elsevier Ltd. Ltd. Selection Selection and and peer-review peer-review under under responsibility responsibility of the of scienti the scientificfi c committee of thecommittee SiliconPV of 2012the SiliconPV conference. 2012 conference Keywords: Epitaxial wafer-equivalent; light trapping; epitaxial lateral overgrowth 1. Introduction The aim of crystalline silicon thin film (cSiTF) solar cells is to reduce the consumption of pure silicon and with this the price per wattpeak of solar cells.
    [Show full text]
  • United States Patent [191 Patent Number: 5,279,987 Lechaton Et A1
    US005279987A United States Patent [191 Patent Number: 5,279,987 Lechaton et a1. Date of Patent: Jan. 18, 1994 [54] FABRICATING PLANAR Autodoping from Arsenic Buried Layer by Selective COMPLEMENTARY PA'I'I‘ERNED Epitaxy Capping”, IEEE Electron Device Letters, vol. SUBCOLLECI‘ORS WITH SILICON 11, No. 3, Mar. 1990, 123-125. EPITAXIAL LAYER Y. Kobayashi, et al., Entitled “High Performance LSI [75] Inventors: John S. Lechaton; Shaw-Ning Mei; Performance Technology: SST CBI-CMOS”, IEDM, Dominic J. Schepis, all of 1988, pp. 760-763. Wappingers Falls; Mithkal M. T. Ishii, et al., Entitled “Silicon Epitaxial Wafer with Smadi, Beacon, all of N.Y. Abrupt Interface by Two-Step Epitaxial Growth Tech nique”, J. Electrochemical Soc., vol. 122, No. 11, 1975, [73] Assignee: International Business Machines pp. 1523-1531. Corporation, Armonk, N.Y. T. J. Donahue, et al., Entitled “Low Temperature Sili [21] Appl. No.: 785,656 con Epitaxy Deposited by Very Low Pressure Chemi [22] Filed: Oct. 31, 1991 cal Vapor Deposition”, J. Electrochem. Soc., vol. 133, No. 8, Aug. 1986, pp. 1697-1701. [51] Int. 01.5 ........................................... H01L 21/20 H-R. Chang, Entitled “Autodoping in Silicon Epi [52] U.S. Cl. ...................................... .. 437/95; 437/59; taxy”, The Journal of Electrochemical Society, vol. 437/108; 148/DIG. 25 132, No. 1, pp. 219-224, Jan. 1985. [58] Field of Search ..................... .. 437/54, 59, 95, 97, 437/108, 112, 161, 952; l48/DIG. 7, DIG. 15, Primary Examiner—-Brian E. Hearn DIG. 25, DIG. 9 Assistant Examiner-C. Chaudhari Attorney, Agent, or Firm—Jeffrey L. Brandt; Harold [56] References Cited Huberfeld U.S.
    [Show full text]
  • Low Cost High Efficiency Screen Printed Solar Cells
    LOW COST HIGH EFFICIENCY SCREEN PRINTED SOLAR CELLS ON CZ AND EPITAXIAL SILICON A Dissertation Presented to The Academic Faculty by Chia-Wei Chen In Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy in the School of Electrical and Computer Engineering Georgia Institute of Technology May 2016 Copyright © 2016 by Chia-Wei Chen LOW COST HIGH EFFICIENCY SCREEN PRINTED SOLAR CELLS ON CZ AND EPITAXIAL SILICON Approved by: Dr. Ajeet Rohatgi, Advisor Dr. Gee-Kung Chang School of Electrical and Computer School of Electrical and Computer Engineering Engineering Georgia Institute of Technology Georgia Institute of Technology Dr. Thomas K. Gaylord Dr. Shreyes N. Melkote School of Electrical and Computer School of Mechanical Engineering Engineering Georgia Institute of Technology Georgia Institute of Technology Dr. Bernard Kippelen School of Electrical and Computer Engineering Georgia Institute of Technology Date Approved: March 7, 2016 This thesis work is dedicated to my parents, Qing-Yan Chen and Men-lan Shaw, my sister Chia-Yu (Christy) Chen, and my beautiful fiancée Yu-Jung (Ruby) Lin, for their encouragement, support and, love. ACKNOWLEDGEMENTS First of all, I would like to express my gratitude to God for all the guidance in this journey. I am always encouraged after going to Him every time when trouble comes. Why are you downcast, O my soul? Why so disturbed within me? Put your hope in God, for I will yet praise him, my Savior and my God. -Psalm 42:5 I would like to express my sincere gratitude to my advisor Dr. Rohatgi for support- ing me, discussing with me and guiding me in the research.
    [Show full text]
  • Epitaxial Wafer of Multiple Periodic Layer for Midwavelength Infrared Detectors with High Sensitivity
    NEW AREAS Epitaxial Wafer of Multiple Periodic Layer for Midwavelength Infrared Detectors with High Sensitivity Suguru ARIKATA*, Takashi KYONO, Katsushi AKITA, Kenichi MACHINAGA, Hiroshi INADA and Yasuhiro IGUCHI ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Midwavelength infrared (MWIR: 3-5 µm) detectors with high sensitivity and fast response are strongly demanded for hazardous gas detection and satellite observation. In recent years, InAs/GaSb superlattices (SLs) have been a subject of intense study as the absorption region of the MWIR detector. Although organometallic vapor phase epitaxy (OMVPE) is advantageous for mass production compared with molecular beam epitaxy (MBE), the number of reports on the OMVPE growth of InAs/GaSb SLs is limited. In this work, we fabricated high-quality 100-period InAs/GaSb SLs on GaSb substrates by OMVPE. MWIR detectors with 100-period SLs showed a dark current density of 2 × 10-4 A/cm2 at -50 mV and 77 K, and an external quantum efficiency of 15% at 3.5 µm and 20 K. These results indicate that the InAs/GaSb SLs could offer excellent structural and electrical properties for high-performance MWIR detectors. ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    [Show full text]
  • New Efficiency Frontiers with Wafer-Bonded Multi-Junction Solar Cells
    Presented at the 29th European PV Solar Energy Conference and Exhibition, 22-26 September 2014, Amsterdam, The Netherlands NEW EFFICIENCY FRONTIERS WITH WAFER-BONDED MULTI-JUNCTION SOLAR CELLS Thomas N. D. Tibbits1§, Paul Beutel§, Matthias Grave§, Christian Karcher§, Eduard Oliva§, Gerald Siefer§, Alexander Wekkeli§, Michael Schachtner§, Frank Dimroth§, Andreas W. Bett§, Rainer Krause*, Matteo Piccin*, Nicolas Blanc*, Miguel Muñoz-Rico*, Chantal Arena*, Eric Guiot*, Cédric Charles-Alfred*, Charlotte Drazek*, Fabienne Janin*, Laura Farrugia*, Bertrand Hoarau*, Jocelyne Wasselin*, Aurélie Tauzin#, Thomas Signamarcheix#, Thomas Hannappel¤, Klaus Schwarzburg¤, Anja Dobrich¤ §Fraunhofer Institute for Solar Energy Systems ISE, Heidenhofstraße 2, 79110 Freiburg, Germany * SOITEC S.A., Parc Technologique des Fontaines, 38190 Bernin, France #CEA LETI MINATEC campus, 17 rue des Martyrs, 38054 Grenoble, France ¤Helmholtz-Zentrum Berlin HZB, Hahn-Meitner-Platz 1, 14109 Berlin, Germany [email protected] ABSTRACT: Triple-junction (3J) solar cells will soon be history. The next generation of multi-junction (MJ) devices are now reaching efficiencies far beyond the record levels of 3J cells on Germanium. In this paper we present results of a 4J wafer-bonded solar cell with bandgaps 1.88 / 1.45 // 1.10 / 0.73 eV measured with an improved efficiency of 46.5% at 324x by Fraunhofer ISE. Design for cost has, from the outset, been a priority with the development of engineered substrates to replace costly and low yielding InP substrates, a product building on Soitec’s proprietary SmartCut® technology. Wafer bonding enables the electro-mechanical combination of lattice and thermal expansion mismatched materials with electrically conductive, transparent bonds, enabling concentrator solar cells to be built from high quality 2J GaInP/GaAs absorbers lattice-matched to GaAs bonded to high quality 2J GaInPAs/GaInAs absorbers lattice matched to InP that operate well at high concentration.
    [Show full text]
  • Solar Cells with 20% Efficiency and Lifetime Evaluation of Epitaxial
    Available online at www.sciencedirect.com ScienceDirect Energy Procedia 92 ( 2016 ) 785 – 790 6th International Conference on Silicon Photovoltaics, SiliconPV 2016 Solar cells with 20 % efficiency and lifetime evaluation of epitaxial wafers Marion Drießena*, Diana Amiria, Nena Milenkovica, Bernd Steinhausera, Stefan Lindekugela, Jan Benicka, Stefan Reberb, Stefan Janza aFraunhofer Institute for Solar Energy Systems, Heidenhofstr. 2, 79110 Freiburg, Germany bnow with NexWafe GmbH, Hans-Bunte-Str. 19, 79108 Freiburg, Germany Abstract We present n-type epitaxially grown wafers deposited in a reactor that allows a process transfer to inline high-throughput reactors. Those wafers exhibit an effective lifetime of up to 1720 μs locally for a phosphorous concentration of 2·1015 cm-3 and a wafer thickness of about 100 μm. In these wafers the most detrimental defects are stacking faults with polycrystalline silicon inclusions. Comparing two samples with stacking faults densities differing by one order of magnitude revealed a difference in average effective minority carrier lifetime of also one order of magnitude (reduction from more than 1500 μs down to 111 μs for the defective sample). A solar cell fabricated from a 200 μm thick epitaxial wafer of low stacking fault density and a phosphorous concentration of 3·1016 cm-3 reaches an independently confirmed efficiency of 20 %, an open circuit voltage of up to 658 mV, a short circuit current density of up to 39.6 mA/cm2 and a fill factor of up to 76.9 %. Differences between this cell and FZ references can be attributed to a reduced bulk lifetime caused by the high doping concentration and most probably additional recombination due to polycrystalline silicon inclusions in stacking faults, although their amount is comparably low.
    [Show full text]
  • High-Quality 6-Inch Sic Epitaxial Wafer “Epiera”
    ELECTRONICS High-Quality 6-inch SiC Epitaxial Wafer “EpiEra” Keiji WADA*, Takemi TERAO, Takaya MIYASE, Tsutomu HORI, Hideyuki DOI, and Masaki FURUMAI ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Power devices have been essential to significantly advance efficient electric power use mainly for a future electric network society that will use versatile energy sources such as renewable energy resources and electric vehicles. SiC power devices are expected to be a key for power conversion systems to cut back electric power loss. To achieve large chip dies used in high current ratings, the wafer size of SiC substrates has increased, requiring precisely controlled fabrication processes. The epitaxial layer used for the drift region in a device structure strongly influences the device performance, entailing to the requirement of epitaxial defects reduction as well as the precise control of doping concentration and thickness for stable chip production. We have successfully demonstrated an extensive defect-free epitaxial layer with an excellent doping concentration and thickness uniformity on a 150- mm diameter 4H-SiC substrate. ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    [Show full text]
  • Advanced Algaas/Gaas Heterostructures Grown by MOVPE
    crystals Article Advanced AlGaAs/GaAs Heterostructures Grown by MOVPE Maxim A. Ladugin 1,*, Irina V. Yarotskaya 1, Timur A. Bagaev 1, Konstantin Yu. Telegin 1, Andrey Yu. Andreev 1, Ivan I. Zasavitskii 2, Anatoliy A. Padalitsa 1 and Alexander A. Marmalyuk 1 1 Sigm Plus Co., 3 Vvedenskogo str., Moscow 117342, Russia; [email protected] (I.V.Y.); [email protected] (T.A.B.); [email protected] (K.Y.T.); [email protected] (A.Y.A.); [email protected] (A.A.P.); [email protected] (A.A.M.) 2 Lebedev Physical Institute, Russian Academy of Sciences, 53 Leninskii prosp., Moscow 119991, Russia; [email protected] * Correspondence: [email protected]; Tel.: +7-495-333-33-25 Received: 21 April 2019; Accepted: 29 May 2019; Published: 14 June 2019 Abstract: AlGaAs/GaAs heterostructures are the base of many semiconductor devices. The fabrication of new types of devices demands heterostructures with special features, such as large total thickness (~20 µm), ultrathin layers (~1 nm), high repeatability (up to 1000 periods) and uniformity, for which a conventional approach of growing such heterostructures is insufficient and the development of new growth procedures is needed. This article summarizes our work on the metalorganic vapour-phase epitaxy (MOVPE) growth of AlGaAs/GaAs heterostructures for modern infrared devices. The growth approaches presented allow for the improved output characteristics of different emitting devices such as multi active region lasers, epitaxially integrated via highly doped tunnel junctions (emission wavelength λ ~ 1 µm), quantum cascade lasers (λ ~10 µm) and THz laser (λ ~100 µm), based on short-period superlattice with 500–2000 layers.
    [Show full text]
  • Semiconductors That Are Known As the III-V Stock Chart Materials
    Emphasized parts from me Home - About motorola - Products and Services - ShopSearch Motorola Inc. (ticker: MOT, exchange: New York Stock Exchange) News Release - 4-Sep-2001 Motorola Creates Revolutionary Semiconductor Materials; Potential to Transform Overview Economics of Communications and Semiconductor Industries Board of Directors and Senior Management SCHAUMBURG, Ill., Sept. 4 /PRNewswire/ -- Motorola, Inc. (NYSE: MOT) announced today that Motorola Labs Stock Quote scientists are the first to successfully combine the best properties of workhorse silicon technology with the speed and optical capabilities of high-performance compound semiconductors that are known as the III-V Stock Chart materials. Financial Reports The discovery, which solves a problem that has been vexing the semiconductor industry for Financial History nearly 30 years, opens the door to significantly less expensive optical communications, high- frequency radio devices and high-speed microprocessor-based subsystems by potentially Stock Trading Statistics eliminating the current cost barriers holding back many advanced applications. For SEC Filings consumers, the technology should result in smarter electronic products that cost less, perform better and have exciting new features. The technology will change the economics and Recent Press Releases accelerate the development of new applications, such as broadband "fiber" cable to the home, streaming video to cell phones and automotive collision avoidance systems. Archived Press Releases Presentations Other potential markets include data storage, lasers for such consumer products as DVD players, medical equipment, radar, automotive electronics, lighting, and photovoltaics. Until Audio Archives now, there has been no way to combine light-emitting semiconductors with silicon integrated circuits on a single chip, and the need to use discrete components has compromised the Brokerage Firm Equity Research Analysts cost, size, speed and efficiency of high-speed communications equipment and devices.
    [Show full text]
  • GALLIUM by Deborah A
    GALLIUM By Deborah A. Kramer Domestic survey data and tables were prepared by Carolyn F. Crews, statistical assistant. Gallium imports, which had fallen significantly from 2001 electricity consumed by the incandescent lamps they replace, to 2002, began to recover in 2003, increasing by 8% from the and they last much longer, allowing for additional savings level in 2002. An upturn in the wireless communications market through reduced maintenance costs. Exit signs were identified and a growing U.S. economy helped to propel the increase as another important niche application, where an estimated in gallium consumption. Gallium arsenide (GaAs) wafers, 80% of U.S. exit signs now use LEDs. LEDs also have made however, continued to be manufactured in such countries as inroads into mobile applications, such as brake and signal lights China, the Republic of Korea, and Taiwan, and imports of on automobiles, buses, and trucks. To date, 41 million gallons undoped GaAs wafers into the United States increased by 89% per year of gasoline and 142 million gallons per year of diesel from the level in 2002. Gallium nitride (GaN) continued to fuel have been saved because of LED use on these vehicles. be the focus of research and development activities. Some (Fuel savings were calculated based on the lower accessory load new devices with GaN components were introduced in 2003, on the engine.) If all automobiles, buses, and trucks were to but significant commercial shipments of GaN were expected convert to LED lighting, 1.4 billion gallons per year of gasoline to begin in 2004, particularly with the introduction of digital and 1.1 billion gallons per year of diesel fuel could be saved video disk (DVD) recorders with GaN laser diodes.
    [Show full text]
  • III-V Multi-Junction Solar Cells
    Chapter 18 III-V Multi-Junction Solar Cells Gui jiang Lin, Jingfeng Bi, Minghui Song, Jianqing Liu, Weiping Xiong and Meichun Huang Additional information is available at the end of the chapter http://dx.doi.org/10.5772/50965 1. Introduction Photovoltaic is accepted as a promising technology that directly takes advantage of our planet’s ultimate source of power, the sun. When exposed to light, solar cells are capable of producing electricity without any harmful effect to the environment or devices. Therefore, they can generate power for many years (at least 20 years) while requiring only minimal maintenance and operational costs. Currently the wide-spread use of photovoltaic over oth‐ er energy sources is impeded by the relatively high cost and low efficiency of solar cells [1]. III-V multi-junction solar cells, as a new technology, offer extremely high efficiencies com‐ pared with traditional solar cells made of a single layer of semiconductor material [2]. The strong demand for higher efficiency photovoltaic has recently attracted considerable interest in multi-junction solar cells based on III-V semiconductors [3]. Depending on a particular technology, multi-junction solar cells are capable of generating approximately twice as much power under the same conditions as traditional solar cells made of silicon. Unfortu‐ nately, multi-junction solar cells are very expensive, so they are mainly used in high per‐ formance applications such as satellites at present. However, in our opinion, with the concentrator technology, the tandem cell will play a role in the future energy market. The state-of-the-art high efficiency III-V solar cells utilize a triple junction structure which con‐ sists of the Ge bottom sub-cell (0.67 eV) formed on the Ge substrate homogeneously, the Ga0.99In0.01As middle sub-cell (1.36 eV), and the lattice matched (LM) Ga0.5In0.5P top sub-cell (1.86 eV) [4,5].
    [Show full text]
  • United States Patent [19] [11] Patent Number: 6,043,509 Kurihara Et Al
    US006043509A United States Patent [19] [11] Patent Number: 6,043,509 Kurihara et al. [45] Date of Patent: Mar. 28, 2000 [54] LIGHT-EMITTING DIODE HAVING 5,061,643 10/1991 Yagi ............ .. 438/46 MOISTURE-PROOF CHARACTERISTICS 5,093,696 3/1992 Kinoshita .... .. 372/46 AND HIGH OUTPUT POWER 5,491,350 2/1996 Unno et al. ............................. .. 257/99 [75] Inventors: T00ru Kurihara; Toshiya Toyoshima; FOREIGN PATENT DOCUMENTS Seiji Mizuniwa; Masahiro Noguchi, 5-63235 3/1993 Japan . all of Ibaraki-ken, Japan 5-243611 9/1993 Japan . 6-252444 9/1994 Japan . [73] Assignee: Hitachi Cable, Ltd., Tokyo, Japan 7-30150 1/1995 Japan . 7-38150 2/1995 Japan . [21] Appl. No.: 09/201,835 Primary Examiner—Minh Loan Tran [22] Filed: Dec. 1, 1998 Attorney, Agent, or Firm—McDermott, Will & Emery Related US. Application Data [57] ABSTRACT ALight-emitting diode having improved moisture resistance Division of application No. 08/766,867, Dec. 13, 1996, Pat. characteristics comprises a p-type gallium arsenide substrate No. 5,888,843. and four epitaxial layers of AlxGa1_xAs (22, 23, 24 and 25). Int. Cl.7 ................................................... .. H01L 29/06 These epitaxial layers comprises an intervening layer (22) of US. Cl. ............................... .. 257/13; 257/94; 257/96; p-type Alx1Ga1_x1As, a cladding layer (23) of p-type 257/103 Alx2Ga1_x2As, an active layer (24) of Alx3Ga1_x3As, and a Field of Search ................................ .. 257/12, 13, 94, Window layer (25) of Alx4Ga1_x4As so as to form a double 257/96, 103, 79 hetero structure, Where X1, X2, X3 and X4 represent miXed crystal ratios of aluminum to arsenic of the layers, References Cited respectively, and meet the condition that: U.S.
    [Show full text]