G. M. Amdahl G. A. Blaauw F. P. Brooks, Jr.,

Architecture of the IBM System / 360

Abstract: The architecture* of the newly announced IBM System/360 features four innovations:

1. An approach to storage which permits and exploits very large capacities, hierarchies of speeds, read- only storage for microprogram control, flexible storage protection, and simple program relocation.

2. An input/output system offering new degrees of concurrent operation, compatible channel operation, data rates approaching 5,000,000 characters/second, integrated design of hardware and , a new low-cost, multiple-channel package sharing main-frame hardware, new provisions for device status infor- mation, and a standard channel interface between and input/output devices.

3. A truly general-purpose machine organization offering new supervisory facilities, powerful logical pro- cessing operations, and a wide variety of data formats.

4. Strict upward and downward machine-language compatibility over a line of six models having a per- formance range factor of 50.

This paper discusses in detail the objectives of the design and the rationale for the main features of the architecture. Emphasis is given to the problems raised by the need for compatibility among central process- ing units of various size and by the conflicting demands of commercial, scientific, real-time, and logical in- formation processing. A tabular summary of the architecture is shown in the Appendices.

Introduction The design philosophies of the new general-purpose ma- Thesection that followsdescribes the objectives of chine organization for the IBM System/360 are discussed the new system design, i.e., that it serve as a base for new in this paper.? In addition to showing the architecture* technologies and applications, that it be general-purpose, of the new family of data processing systems,we point out efficient, and strictly program compatible in all models. the various engineering problems encounteredin attempts The remainder of the paper is devoted to the design to make the system design compatible, at the program problems faced, the alternatives considered, and the deci- level, for large and small models. The compatibility was sions made for data format, data and instruction codes, to extend not only to models of any size but also to their storage assignments, and input/output controls. various applications-scientific, commercial, real-time,and Design objectives so on. The new architecture builds upon but differs from the de- The term architecture is used here to describe the attributes of a system as seen by the programmer, i.e., the conceptual structure and signs that have graduallyevolved since1950. The evolution functimal behavior, as distinct from the organization of the data flow and controls, the logical design, and the physical implementation. of the had included, besides major technological iAdditional details concerning the architecture, engineering design, improvements,several important systemsconcepts and programming, and application of the IBM System/360 will appear in a series of articles in the IBM Systems Journal. developments : 87

IBM JOURNAL APRIL 1964 1. Adaptation to business data processing. 5. The input/output channel and the input/output control program had to be designed for each other. 2. Growing importance of the total system, especially the input/output aspects. 6. Machinesystems had to be capable of supervising themselves,without manual intervention, for both real- 3. Universaluse of assemblyprograms, compilers, and time and multiprogrammed, or time-shared, applications. other metaprograms. To realize this capability requires: a comprehensive inter- 4. Development of magnetic recording on tapes, drums, ruption system, tamper-proof storage protection, a pro- and disks. tected supervisor program, supervisor-controlled program switching, supervisor control of all input/output (includ- 5. Hundred-fold expansion of storage capacities. ing unit assignment), nonstop operation (no HALT), easy 6. Adaptation for real-time systems. program relocation, simple writing of read-only or un- modified programs, a timer, and interpretive consoles. During this period most new computer models, from the point of view of their logical structure, were improved, 7. It mustbe possible and straightforward to assemble enlarged, or technologically recast versionsof the machines systems with redundant I/O, storages, and CPU’s so that developed in the early 1950’s. IBM products are not the system can operate when modules fail. atypical; the evolution has gone from IBM 701 to 7094, 8. Storage capacitiesof more than the commonly available 650 to 7074, from 702 to 7080, and from 1401 to 7010. 32,000 words would be required. The system characteristics to be described here, how- ever, are a new approach to logical structure and function, 9. Certain types of problems require floating-point word designed for the needs of the next decadeas a coordinated length of more than 36 . set of data processing systems. 10.As CPU’s becomeincreasingly reliable, built-in Advanced concepts thorough checking against hardware malfunction is im- perative for all systems, regardless of application. It was recognized from the start that the design had to embody recent conceptual advances, and hence, if neces- 11.Since the largestservicing problem is diagnosis of sary, be incompatible with existing products.To this end, malfunction,built-in hardware fault-locating aids are the following premises were considered: essential to reducedown-times. Furthermore, identifka- tion of individual malfunctions and of individual invalidi- 1.Since develop into families,any proposed ties in program syntax would haveto be provided. design would haveto lend itselfto growth and to suacessor machines. Open-ended design The new design had to provide a dependable base for a 2. Input/output (I/O) devices make systems specifically decade of customer planning and customer programming, useful for given applications. A general methodwas needed and continuing laboratory developments, whether in tech- for using 1/0 devices differing in data rate, access, and nology, application and programming techniques, system function. configuration, or special requirements. Thevarious circuit, storage, and input/output tech- 3. The real value of an information system is properly nologies used in a system changeat different times, causing measured by answers-per-month, not bits-per-microsecond. corresponding changes in their relative speeds and costs. The former criterion required specific advances to increase To take advantage of these changes, it is desirablethat the throughput for a given internal speed, to shorten turn- designpermit asynchronous operation ofthese compo- around time for a given throughput, and to make the nents with respectto each other. wholecomplex of machines and programmingsystems Changing application and programmingtechniques easier to use. would require open-endedness in function. Current trends had to be extrapolated and their consequences anticipated. 4. The functions of the central processing unit (CPU) This anticipation could be achieved by direct provision, proper are specific to its application only a minor fraction e.g., by increasing storage capacities and by using multiple- of the time. The functions required by the system for its CPU systems, various new 1/0 devices, and time shar- own operation, e.g., compiling, input/output management, ing. Anticipation mightalso take the form of general- and the addressing of and within complex data structures, ization of function, as in code-independent scan and use a major share of time. These functionshad to be made translation facilities, or it might consist of judiciously re- efficient, and need not be different in machines designed serving spare bits, operation codes, and blocks ofoperation 88 for different applications. codes, for new modes, operations, or sets of operations.

AMDAHL, BLAAUW AND BROOKS Changing requirements for system configuration would would easily perform such logical functions as code trans- demand not only such approaches as a standard interface lation and message assembly, communications lines would between 1/0 devices and control unit, but alsocapabilities be attached directly to the 1/0 channel via a control unit for a machine to directly sense, control, and respond to that would perform only assembly and the elec- other equipment modules via pathsoutside the normal trical line-handling functions. data routes. These capabilities permit the construction of supersystems that can be dynamically reconfigured under Eficient performance program control, to adapt more precisely to specialized The basic measure of a good design is high performance functions or togive graceful degradation. in comparison to other designs having the same cost. This In many particular applications, some special (and often measure cannot be ignored in designing a compatible line. minor) modification enhances the utility of the system. Hence each individual model and systems configuration These modifications (RPQs), which may correct some in the line would have to be competitive with systems that shortsightedness of the original design, often embody are specialized in function, performance level or both. operations not fully anticipated. In any event, a good That this goal is feasible in spite of handicaps introduced general design would obviatecertain modifications and by the compatibility requirement was due to the especially accommodate others. important cost savings that would be realized due to General-purpose function compatibility. The machine design would have to provide individual system configurations for large and small, separate and Intermodel compatibility mixed applications as found in commercial, scientific, real- The design had to yield a range of models with internal time, data-reduction, communications, language, and logi- performance varying from approximately that of the IBM cal data processing. The CPU design would have to be 1401 to well beyond that of the IBM 7030 (STRETCH).As facile for each of these applications. Special facilities such already mentioned, all models would have to be strictly as decimal or floating-point arithmetic might be required program compatible, upward and downward, at the pro- only for one or another application class and would be gram bit level. offered as options, but they would have to be integral, The phrase “strictly programcompatible” requires a from the viewpoint of logical structure, with the design. more technically precise definition. Here it means that a In particular,the general-purpose objective dictated that: valid program, whose logic will not depend implicitly upon time of execution and which runs upon configuration A, 1. Logical power of great generality would have to be will also run on configuration B if the latter includes at provided, so that all combinations of bits in data entities least the required storage, at least the required 1/0 de- would be allowed and might be manipulated with oper- vices, and at least the required optional features. Invalid ations whose power and utility depend upon the general programs, i.e., those which violate the programming nature of representations rather than upon any specific manual, are not constrained to yield the same results on selection of them. all models. The manual identifies not only the results of 2. Operations would have to be code-independent except, all dependable operations, but also those results of ex- of course, where code definition is essential to operation, ceptional and/or invalid operations that are not depend- as in arithmetic. In particular, all bit combinations should able. Programs dependent on execution-time will operate be acceptable as data; no combination should exert any compatibly if the dependence is explicit, and, for example, control function when it appears in a data stream. if completion of an 1/0 operation or the timer are tested. Compatibility would ensure that the user’s expanding 3. The individual bit would have to be separately manip- needs be easily accommodated by any model. Compati- ulatable. bility would also ensure maximum utility of programming 4. The general addressing system would have to be able support prepared by the manufacturer, maximum sharing to refer to small units of bits, preferably the unit used for of programs generated by the user, ability to use small characters. systems to back up large ones, and exceptional freedom in configuring systems for particular applications. Further, theimplications of general-purpose CPU design It required a new concept and mode of thought to make for communications-oriented systems indicated a radical the compatibility objective even conceivable. In the last departure from current systems philosophy. The conven- few years, many computer architects had realized, usually tional CPU, for example, is augmented by an independent implicitly, that logical structure (as seen by the program- stored-program unit (such as the IBM 7750 or 7740) to mer) and physical structure (as seen by the engineer) are handle all communications functions. Since the new CPU quite different. Thus each may see registers, counters, etc., 89

ARCHITECTURE OF THE 1[BM SYSTEM/360 that to the other are not at all real entities. This was not The design decisions so in the computers of the 1950’s. The explicit recognition Certain decisions for the architectural designbecame of the duality of structure opened the way for the com- mileposts, because they (a) established prominent charac- patibility within System/360. The compatibility require- teristics of the System/360,(b) resolved problems con- ment dictated that the basic architecture had to embrace cerning the compatibility objective, thus illuminating the different technologies, different storage-circuit speedratios, essential differences between small models and large, or different data path widths, and different data-flow com- (c) resolved problems concerning the general-purpose ob- plexities. The basic machine structure and implementation jective, thus illuminating the essential differences among at the variousperformance levels are shown in Fig. 1. applications. The sections that followdiscuss these de-

Figure l Machine structure and implementation.

STORAGE - CAPACITY8-BITBYTES WIDTH BITS CYCLE IK=1024 EXCLUDINGPARITY I 1 -PS ADDRESSES 8-64K 8 2.0 16 - 256 K 16 2.5 32 - 256 K 32 2.0 128 - 512 K 64 2.0 256 - 512 K 64 1.0 70 256 - 512 K 64 -1.0 I +

INSTRUCTIONS #t

4 I I CONTROL DATAFLOW

WIDTH BITS CIRCUIT DELAYCIRCUIT BITS WIDTH MODEL TYPE MODEL CYCLE EXCLUDINGPARITY PERLEVEL, ns

30 REAOONLY STORE 1.0 INDEXEDADDRESSES 30 a 30 40 REAO ONLY STORE 0.625 40 8 30 50 REAO ONLYSTORE 0.5 30 50 32 60 REAO ONLYSTORE 0.25 60 64 IO 62 REAOONLY STORE 62 64 IO 70 CONVENTIONALCIRCUITS 70 64 5

I GENERALREGISTERS FLOATING POINT REGISTERS

WIDTH BITS CYCLEWIDTHBITS I MODEL 1 TYPE 1 EXCLUDINGPARITY 1 ps 1 MAINSTORE CORE ARRAY CORE ARRAY TRANSISTORREGISTERS 64 - 64 - 90

AMDAHL,BLAAUW AND BROOKS cisions, the problemsfaced, the alternativesconsidered, Good data were unavailable on the distribution of and the reasons for the outcome. required precision by the number of problems or running time. Indeed, accurate measures could not be acquired on Data format such coarse parameters as frequency of double-precision Thedecision on basic format (whichaffected character operation on 36-bit and 48-bitmachines. The question size, word size,instruction field, number of index registers, became whether to force all problems to the longer 48-bit input-output implementation, instruction set layout, stor- word, or whether to provide 64 to take care of precision- age capacity,character code, etc.)was whether data length sensitive problems adequately, and either 32 or 36 to give modulesshould go as 2" or 3.2".Even though many faster speed and better coding efficiency for the rest. The matters of format were considered in the basicchoice, choice was made for the IBM System/360 to have both we will for convenience treat the major components of 64- and 32-bit length floating point. This choice offersthe the decision as if they were independent. user the option of making the speed/space vs precision Character size, 6 us 4/8. In character size, the funda- trade-off to best suit his requirements.The user of the large mental problem is that decimal digits require 4 bits, the models is expected to employ 64-bit words most of the alphanumeric characters require 6bits. Three obvious time. The user of the smaller models will find the 32-bit alternatives were considered - 6 bits for all, with 2 bits length advantageous in most ofhis work. All floating- wasted on numeric data; 4 bits for digits, 8 for alpha- point models have both lengths and operate identically. numeric, with 2 bits wasted on alphanumeric; and 4 bits Hexadecimalfloating-point radix. With no conflcts in for digits, 6 for alphanumeric, which would require adop- questions of large vs small machines, base 16 was selected tion of a12-bit module as the minimumaddressable for floating point. Studies by Sweeney' show that the fre- element. The 7-bit character, which incorporated a binary quency of pre-shift, overflow,and precision-loss post-shift recoding of decimal digit pairs, was also briefly examined. on floating-point addition are substantially reducedby this The 4/6 approach was rejected because (a)it was desired choice. He has shown that, compared with base2, the per- to have the versatility and power of manipulating character centage frequencyof occurrence of overflow is 5 versus 20, streams and addressingindividual characters, evenin pre-shift is 43 versus 58, and precision-loss post-shift is models where decimal arithmetic is not used, (b) limiting 11versus 18. Thus speedis noticeably enhanced. Also, the alphabetic character to 6 bits seemed short-sighted, simpler shifting paths, with fewer logic levels, will accom- and (c) the engineeringcomplexities of this approach plish a higher proportion of all required pre-shifting in a might well cost morethan the wasted bits in the character. single pass. For example, circuits shifting 0, 1, 2, 3, or 4 The straight-6 approach, used in the IBM 702-7080 and binaryplaces cover 82% of the base2 pre-shifts. Sub- 1401-7010 families, as well as in other manufacturers' stantially simpler circuits shifting 0, 1, or 2 hexadecimal systems,had the advantages of familiarusage, existing places cover 93% of all base 16 pre-shifts. This simplifica- 1/0 equipment, simple specificationof field structure, and tion yields higher speed for the large models and lower commensurability with a 48-bit floating-point word and a cost for the small ones. 24-bit instruction field. The most substantial disadvantage of adopting base 16 The 4/8 approach, usedin the IBM 650-7074 family is the shift in bit usage from exponent to fraction. Thus, and elsewhere, had greater coding efficiency, spare bits in for a given range and a given minimum precision, base 16 the alphabetic set (allowing the set to grow), and commen- requires 2 fewer exponent bits and 3 more fraction bits surability with a 32/64-bit floating-point word and a 16- than does base 2. Alternatively and equivalently, rounding bit instruction field. Most important of these factors was and truncation effects are 8times as large for a given coding efficiency, which arises from the fact that the use fraction length. For the 64-bit length, this is no problem. of numeric data in business records is more than twice as For the 32-bit length, withits 24-bit fraction, the minimum frequent as alphanumeric.This efficiencyimplies, for a precision is reduced to the equivalent of 21 bits. Because given hardware investment,better use of core storage, the 64-bit length was available for problems where the faster tapes, and more capacious disks. minimum precision cramped the user, the greater speed Ffoating-pointword length, 48 us 32/64. For large and simplicity of base 16 was chosen. models addition time goes up slowly with word length, Significance arithmetic. Many schemes yielding an esti- and multiplication time rises almost linearly. For small, mate of the significance of computed results have been serial models, addition time rises linearly and multiplica- proposed. One such scheme, a modified form of unnor- tion as the square of word length. Input/output time for malized arithmetic, was for atime incorporated in the data files rises linearly. Large machines moreoften require design. The scheme was finally discarded when simulation high precision; small machines more urgently requireshort runs showed this mode of operation to cost about one operands. For this aspect of the basic format problem, hexadecimaldigit of actual significancedeveloped, as then, definite conflicts arose because of compatibility. comparedwith normalized operation. Furthermore, the 91

ARCHITECTURE OF THE IBM SYSTEM/360 significance estimate yielded for a given problem varied length fields in storage; for example, it distinguishes IBM substantially with the test data used. 702-7080 arithmetic from that of the IBM 1401-7010 Sign representations. For the fixed-point arithmetic family. system, which is binary,the two’s complement representa- The large models readily afford registers or local stores tion for negative numbers was selected. The well-known and get a speedenhancement from usingthese as ac- virtues of this system are the uniquerepresentation cumulators. For the small model, using core storage for of zero and the absence of recomplementation.These logical registers, addition to an is no faster substantial advantages are augmented by several properties than addition to a programmer-specified location.Addition especially useful in address arithmetic, particularly in the of twoarbitrary operands and storage of the result becomes large models, where address arithmetic has its own hard- LOAD, ADD, STORE, however, and this operation is ware. With two’s complement notation, this indexing substantially slower for the small models than the MOVE, hardware requires no true/complement gates and thus ADD sequence appropriate to storage-storage operation. works faster. In the smaller, serial models, the fact that Business arithmetic operations (as hand coded and es- high-order bits of address arithmetic can be elided with- pecially as compiled from COBOL) often take this latter out changing the low-orderbits also permits a gainin form and rarelyoccur in strings where intermediate speed. The same truncation property simplifiesdouble- results are profitablyheld in accumulators. In address precision calculations. Furthermore, for table calculation, arithmetic and floating-point arithmetic, quite the opposite rounding or truncation to an integer changes all variables is true. in the same direction, thus giving a moreacceptable Field specification: word-marks versus length. Variable- distribution than does an absolute-value-plus-sign repre- length fields canbe specified in thedata via delimiter sentation. characters or word-marks, or in the instruction via specifi- The established commercial rounding convention made cation ef field length or start-finish limits. For business the useof complement notation awkwardfor decimal data, the word-mark has some slight advantagein storage data; therefore, absolute-value-plus-sign is used here. In efficiency: one extra bit per 8-bit character would cost floating point, the engineering virtues of normalizing only less than 4 extra length bits per 16-bit address. Further- high-orderzeros, and of having all zerosrepresent the more, instructions, and hence addresses, usually occupy smallest possible number, decided the choice in favor of most core storage space in business computers. However, absolute-value-plus-sign. the word-mark approach implies the use of word-marks on Variable- versus fixed-length decimal fields. Since the instructions, too, and here the cost iswithout compensating fields of business records vary substantiallyin length, cod- function. The same is true of all fixed-field data, an im- ing efficiency (and hence tape speed, file capacity, CPU portant considerationin a general-purposedesign. On speed, etc.) can be gained by operating directly on vari- balance, storage efficiency is about equal; the field speci- able-length fields. This is easy for serial-by-byte machines, fication was put in the instruction to allow all data combi- and the IBM 1401-7010 and 702-7080 families are among nations to bevalid and to giveeasier and more direct those so designed. A less flexible structure is more appro- programming,particularly since it providesconvenient priate for a more parallel machine,and the IBM 650-7074 addressing of parts of fields. Length was chosen over limit familyis among those designedwith fixed-word-length specification to simplify program relocation and instruc- decimal arithmetic. tion modification. As one would expect,the storage efficiency advantage of ASCZZus BCD codes. The selection of the 8-bit char- the variable data format is diminishedby the extra instruc- acter size in 1961 proved wise by 1963, when the American tion information required for length specification. While Standards Association adopted a 7-bit standard character the fixed format is preferable for the larger machines, the code for information interchange(ASCII). This 7-bit variable format was adopted because (a) the small com- code is now under final considerationby the International mercial users are numerous and only recently trained in Standards Organizationfor adoption as an interna- variable-formatconcepts, and (b) the largecommercial tional standards recommendation. The question became system is usually 1/0 limited; hence the internal perform- “Why not adopt ASCII as the only internal codefor ancedisadvantage of the variable format ismore than System/360?’ compensated by the gain in effective tape rate. The reasonsagainst such exclusive adoption was the Decimal accumulators versus storage-storageoperation. widespread use of the BCD code derived from and easily A closely related question involving large/small models translated to the IBM card code. To facilitate use of both concerned the use of an accumulator as one of the oper- codes, the central processingunits are designedwith a ands on decimal arithmetic, versus the use of storage high degree of code independence, with generalized code locations for all operands and results. This issue is per- translation facilities, and with program-selectable BCD or 92 tinent even after a decision has been made for variable- ASCII modes for code-dependent instructions. Neverthe-

AMDAHL,BLAAUW AND BROOKS Figure 2a Extended binary-coded-decimal (BCD)interchange code.

00 01 10 11 00 01 10 11 1000 01 11

Figure 2b 8-bit representation of the 7-bit American Standard Code for Information Interchange (ASCII).

x5 L 4321 00 0111 10 00 01 10 11 00 01 10 11 1000 01 11 OOOO NULL 0001 SOM 0010 EOA 0011 €OM

0100 EQT

0101 WRU 0110 RU 0111 BELL 1000 BKSP 1001 HT 1010 LF 1011 VT 1100 FF 1101 CR 1110 so 1111 SI I 0- -1 93

ARCHITECTURE OF THE: IBM SYSTEM/360 less, a choice had to be made for the code-sensitive 1/0 tions with explicit, but truncated, addresses which specify devices and for the programming support, and the solution only the fast registers. was to offer both codes, fully supported, as a user option. 4. In any practical implementation, the depth of the stack Systems with either option will, of course, easily read or has a limit. The register housekeeping eliminated by the write 1/0 media with the other code. The extended BCD pushdown organization reappears as management of a interchange code and an 8-bit representation of the 7-bit finite-depth stack and as specificationof locations of ASCII are shown in Fig. 2. submerged data for TOP’S and SWAP’S. Further, when Boundary alignment. A majorcompatibility problem part of a stack must be dumpedto make room for new concerned alignmentof field boundaries. Different models full data, it is the bottom part, notthe active part, which were to have different widths of storage and data flow, should be dumped. and therefore each modelhad a different setof preferences. For the 8-bit wide model the characters might have been 5. Subroutine transparency, i.e., the ability to use a sub- aligned on character boundaries,with no further con- routine recursively, is one of the apparent advantages of straints. In the 64-bit wide model it might have been pre- the stack.However, the disadvantage is that the trans- ferred to have no fields splitbetween different 64-bit parency does not materialize unless additional independ- double-words. The general rule adopted (Fig. 3) was that ent stacks are introduced for addressing purposes. each fixed field must begin at a multiple of its field length, and variable-length decimaland character fields are uncon- 6. Fitting variable-length fields into a fixed-width stack is strained and are processedserially in allmodels. All awkward. models must insure that programmers will adhere to these In the final analysis, the stack organization would have rules.This policing is essential to prevent the useof been about break-even for a system intended principallyfor technically invalid programs that might work beautifully scientific computing. Here the general-purpose objective on small models but not on large ones. Such an outcome weighed heavily in favor of the more flexible addressed- would undermine compatibility. The general rule, which register organization. has very few and very minor exceptions, is that invalidities Full us truncated addresses. From the beginning, the defined in the manual are detected in the hardware and major challenge of compatibility layin storage addressing. cause an interruption. This type of interruption is distinct It wasclear that largemodels would require storage from an interruption caused by machinemalfunctions. capacitiesin the millionsof characters. Small (serial) models would requireshort addresses to conserve precious Instruction decisions core spaceand instruction fetch time. Some help was given by the decision to use register addressing, which reduces Pushdown stack us addressed registers. Serious considera- tion was given to a design based on a pushdown accumu- address appearances in the instruction stream by a factor lator or stack.’ Thisplan was abandoned infavor of approaching 2. An early decision had dictated that all addresses had to severalregisters, each explicitly addressed. Since the be indexable, and that a mechanism had to be provided advantages of the pushdown organization are discussed in the literature: it suffices here to enumerate the disad- for making all programs easily relocatable. The indexing vantages which prompted the decision to use an addressed- technique had fully proved its worth in current ~ystems.~ register organization: This technique suggested that abundant address size could be attained through a full-sized , used as a 1. The performance advantage of a pushdownstack organi- base. This approach, coupled with a truncated address in zation is derived principally from the presence of several the instruction, gives consequentgains in instruction fast registers, not from the way they are used or specified. density. The base-register approach was adopted, and 2. The fraction of “surfacings” of data in the stack which then augmented, for some instructions, with a second level are “profitable,”i.e., what wasneeded next, is about of indexing. Now the question was: How much capacity was to be one-half in generaluse, because of the occurrence of madedirectly addressable, and howmuch addressable repeated operands (both constants and common factors). only via base registers? Some early uses of base register This suggests the use of operations such as TOP and SWAP, techniqueshad been fairlyunsuccessful, principally whichrespectively copy submerged data to the active be- causeof awkward transitions between direct and base positions and assist in clearing submerged data when the information is no longer needed. addressing. It wasdecided to commit the systemcom- pletely to a base-register technique; the direct part of the 3. With TOP’s and SWAP’s counted, the substantial in- address, the displacement, was made so small (12 bits, struction density gained by the widespread use of implicit or 4096 characters) that direct addressing is a practical 94 addresses is about equalled by that of the same instruc- programming technique only on very small models. This

AMDAHL, BLAAUW AND BROOKS DOUBLE WORD D

WORD WORD >

HALFWDRD -rHALNVDRD .I BYTE- -BYTE" rsyTE-"r

I LONG FLOATING-POIAT NUMBER I I I I 56 FRACTION L' 1I 71

I I ZONEDDECIMAL NUMBER ""_ I I I 4 4 4 4 4 +[""j +[""j """ ""_ DIGIT ZONE DIGIT SIGN DIGIT I I FIXED-LENGTHLOGICAL INFORMATION I LOGICALDATA

0 31

VARIABLE-LENGTHLOGICAL INFORMATION """ I 8 I 8 CHARACTER CHARACTER CHARACTER """ """_

INSTRUCTIONS BY FORMATTYPE RR FORMAT I 8 4 4 OP CODE RI R2 L I 0 7 II 15

?X FORMAT 8 4 4 4 12 OP CODE RI x2 62 02

RS FORMAT 8 4 4 4 12 OP CODE RI R3 62 02

SI FORMAT 8 8 4 12 DP CODE I2 BI Dl 0 7 15 19 31 SS FORMAT I 8 4 4 12 4 4 12 OP CODE LI L2 BI Dl 82 02 0 7 II 15 19 31 35 47

Figure 3 Boundary alignment of formats. 95

ARCHITECTURE OF THE IBM SYSTEM/360 commitment implies that all programs are location-inde- gaps in the addressing sequence. pendent,except for constants used to load the base Separate us universal accumulators. There are several registers. Thus, all programs can easily be relocated. This advantages of having fixed- and floating-point arithmetic commitment also implies that the programming support use the samelogical (as opposed to physical)registers. effectively and efficiently handles the mechanics of base- There are some less obvious disadvantages which weighed register use. The assembler automatically constructs and in favor of separate accumulator sets. First, in a given assigns base-plus-displacement addresses as it constructs register specification (4 bits, in our case) the use of sepa- the symbol table. The compilers not only do this, but also rate sets permits more registers to be specified because of allocate base registers to give efficient programs. the information implications of the operation code. Sec- Decimal us binary addressing. It wasdecided to use ond, in the largemodels instruction execution and the binary rather than decimaladdressing, because (a) as- preparation of later instructions are doneconcurrently sembly programsremove the userone level from the in separate units. To use a single register set would couple address, thus reducing the importance of familiar usage, these closely, and reduce the asynchronous concurrency (b) binary addressing is more efficient in the ratio 3.32/ that can be attained. Historically,index registers have 4.00, and (c) table exploitation is easier and more gen- been separated from fixed-point registers, limiting analy- eral because any datum can be made into or added to sis of register allocation to index quantities only. Inte- a binary address, yielding a valid address. This decision, gration of these facilities bringsthe full power of the fixed- however, represented some conflict withpast approaches. point arithmetic operation set to bear upon indexing Machines for purely business applications had often used computations. The advantages of the integration appear decimaladdressing (in the ancestral machine of the throughout programexecution (even compiler and as- family). Most business computers now have binary ad- sembly execution), whereasthe register allocation burdens dressing or have evolved to mixed-radix addressing. only compilation and assembly. Multiple accumulators. An extrapolation of technologi- cal trends indicated the probable availability of small, Znput/output system high-speed storage. Consequently, the design uses a sub- The method of input/output control would have been a stantial number of logically identifiable registers, which major compatibility problemwere it not for the recognition are physicallyrealized in core storage, local high-speed of the distinction between logical and physical structures. storage, or transistors, according to the model. There are Smallmachines use CPU hardware for 1/0 functions; sixteen32-bit general-purpose registers and four64-bit largemachines demand several independent channels, floating-point registers in the logicaldesign, with room capable of operating concurrently with the CPU and with for expansionto eight floating-point registers. Surprisingly each other. Such large-machine channels often each con- enough, the multiple-registerdecision was not a large- tain more components than an entire small system. small conflict. Each model has an appropriate (and differ- Channel instructions. The logicaldesign considers the ent) mechanization of the same logical design. channel as an independently operating entity. The CPU Storage hierarchies. Technologypromises to yield a program starts the channel operation by specifying the continuingspectrum of storage systemswhose speed beginning of a channel program and the unit to be used. variesinversely with capacity for equal cost-per-bit. Of The channel instructions, specialized for the 1/0 function, equal significance, problem requirements naturally follow specify storage blocks to be read or written, unit oper- a matching pattern - small quantities of data are used ations, conditional and unconditional branches within the with great frequency,medium quantities withmedium channel program, etc. When the channel program ends, frequency, and very large quantities with low frequency. the CPU program is interrupted, and complete channel Thesefacts promise substantial performance/cost ad- and device status information are available. vantages if storage hierarchies can be effectively used. An especially valuable feature is command chaining, the It wasdecided to accept the engineering,architec- ability of successive channel instructions to give a sequence tural, and programmingdisciplines required for stor- ofdifferent operations to the unit, such as SEARCH, age-hierarchyuse. The engineermust accommodate in READ, WRITE, READ FOR CHECK. This feature per- one systemseveral storage technologies,with separate mits devices to be reinstructed in very short times, thus speeds, circuits, power requirements, busing needs, etc., substantially enhancing effective speed. all requiring asynchronous operation of all storage with Standardinterface. The generalization of the com- respect to the CPU. The system programmer must contend municationbetween the central processing unit and an withawkward boundaries within total storage capacity input/output device has yielded a channel which presents and must allocate usage. He must devise addressing for a standard interface to the device control unit. This inter- very largecapacities, block transfers, and means of face was achieved by making the channel design trans- 96 handling, indexing acrossand providing protection across parent, passing not only data, but also control and status

AMDAHL, BLAAUWAND BROOKS information between storage and device. AU functions to large-capacity storage, and the machine-language com- peculiar to the device are placed in the control unit. The patibility among the six models. interface requires a total of 29 lines and is made inde- The contributions discussed in this paper may be sum- pendent of time through the use of interlocking signals. marized as follows : Implementation. In small models, the flow of data and 1. The relative independence of logical structureand control information is time-shared between the CPU and physical realizationpermits efficient implementation at the channel function. When a byte of data appears from an various levels of performance. 1/0 device, the CPUis seized, dumped, used and restored. Although the maximum data rate handled is lower (and 2. Tasks thatare common to operating a system for the interference with CPU computation higher) than with mostapplications require a complement of instructions separate hardware, the function is identical. and system functions that may serve as a base for the Once the channel becomes a conceptualentity, using addition of application-oriented functions. time-shared hardware, one may have a large number of 3. Theformats, instructions, register assignment, and channels at virtually no cost save the core storage space over-all functions such as protection and interruption of for the governing control words. This kind of multiplex a computer can be so defined that they apply to many channel embodies up to 256 conceptual channels, all of levels of performance and that they permit diverse special- which may be concurrently operating, when the total data ization for particular applications. rate is within acceptable limits. The multiplexing consti- tutes a major advance for communications-based systems. It is hoped that the discussions of these design features will shed some light on the present and future needs of Conclusion data processing system organization. This paper has shown how the design features were chosen for the logical structureof the six models that com- Appendices prise the IBM System/360. The rationale has been given The design resulting from the decision process sketched For the adoption of the data formats, the instruction set, above is tabulated in five appendices showing formats, md the input/output controls. The main features of the dataand instruction codes, storage assignments and new machine organization are its general-purpose utility interruptionaction. (Appendices I through 5 appear on For many types of data processing, the new approaches the following four pages.)

Acknowledgments References

beimplementation of System/360 depends upon diverse 1. D. W. Sweeney,.. “An-! malysis of Floating-Poir ItAddition and Shifting,” to be published in the ZBM-Systems Journal. ievelopments by many colleagues. The most important of 2. See, for example, R. S. Barton, “A New Approach to the hese developments were glass-encapsulated semi-inte- Functional Design of a Digital Computer,” Proc. WJCC 19, rated semiconductorcomponents, printed circuit back- 393-396 (1961). 3. F. P. Brooks, Jr., “RecentDevelopments in Computer )anels and interconnections, new memories, read-only Organization,” Adcances in Electronics 18, 45-64 (1963). torages and microprogram techniques, new 1/0 devices, 4. G. A. Blaauw, “Indexing,” in Planning a Computer System, rnd a new level and approach to software support. W. Buchholz, ed., McGraw-Hill Book Company Inc., 1962, pp. 150-178. The scope of the compatibility objective and of the whole ;ystem/360 undertaking was largely due to B. 0. Evans, Jata Systems Division Vice-President-Development. Received January 21, 1964 97

ARCHITECTURE OF THE IBM SYSTEM/360 rg OD m Appendix I All operation codes are shown in the following table. Appendix 2 continued !i The 8-bit codes are grouped by the main classes, such as fixed-point from addressableregisters and storage. The PSW is storedupon arithmetic, floating-point arithmeticand logical operations. The interruption. TheChannel Command Word controls input/output 5 codes are furthermore grouped according to the five main instruc- operation and sequencing. The commands which may be given to m : tion formats RR (register-register), RX (register-indexed storage loca- thechannel are listed as part of the table.The ChannelAddress E tion), RS (register-storage), SI (storage-immediate information) and Word is used to initiate input/output sequencing. The Channel Status SS (storage-storage). Wordindicates the channel status at thecompletion of an input/ output operation or, when specified, during an 1/0 operation.

OPERATIONCODES CONTROL WORD FORMATS

FORMAT RR RR RR RR FIXED-POINT Baseand Index Registers

CLASSBRANCHING AN0 FULLWOROI FLOATING-POINTFLOATING-POINT ~~ SI~~~LI~LLGANDE&AL LQNG %NE1 rO-O-O-O-O-O-O-O-O-O-1-1-1-1-1-1-1-1-1-1-2-2-2-2-2-2-2-2-2-2-3-3~ I I I x xx x ooooxxxx xxxx ooolxxxx ooloxxxx oollxxxx I i I ADDRESS BASE OR INDEX I I I I 0000 LOAD POSITIVE LOADPOSITIVE LOADPOSITIVE L0-1-2-3-4-5-6-7-8-9-0-1-2-3-4-5-6-7-B-9-0-1-2-3-4-5-6-7-8-9-0-1J 0001 LOAD NEGATIVE LOADNEGATIVE LOADNEGATIVE 0010 LOAD AN0TEST LOADAN0 TEST LOADAN0 TEST 0 - 7 Ignored 0011 LOAO COMPLEMENT LOADCOMPLEMENT LOAOCOMPLEMENT 8 - 31 Baseaddress or index 0100 SET PROGRAM MASK AN0 HALVE HALVE 0101 BRANCHAN0 LINK COMPARE LOGICAL 0110 BRANCH ON COUNT OR 0111 BRANCH/CONOITION EXCLUSIVE OR 1000 SETKEY LOAO LOAD LOAO 1001 INSERTKEY COMPARE COMPARE COMPARE 1010 SUPERVISORCALL A00 ADDN ADO N 1011 SUBTRACT SUBTRACTN SUBTRACTN 1100 MULTIPLY MULT I PLY MULTIPLY 1101 DIVIDE OIVIOE DIVIDE 1110 ADO LOGICAL ADO U ADO U -3-3-3-3-3-3-3-3-4-4-4-4-4-4-4-4-4-4-5-5-5-5-5-5-S-5-5-5-6-6-6-61 1111 SUBTRACTLOGICAL SUBTRACT U SUBTRACTU Ill I I INS T R U C TIO N ADDRESSINSTRUCTION I I F O RM A T RX FORMAT RX RX RX FIXED-POINT FIXED-POINT CLASS HALFWORO FULLWORDFLOATING-POINT FLOATING-POINT 0 - 7 Systemmask AY!LEEANSHLJ1P?G AUQ5rnL LPY4 SnmI 0 MultiplexorchanneL mask I SelectorchanneL 1 mask xxxx olooxxxx ololxxxx OAlOXXXX olllxxxx 2 Selectorchannel 2 mask 3 SelectorchanneL 3 mask S T OR E STORE STORE 0000 STORESTORE STORE 4 Selectorchannel 4 mask 0001 LOADADDRESS 5 Selectorchannel 5 mask 0010 STORECHARACTER 6 Selectorchannel 6 mask 001 1 INSERTCHARACTER 7 External mask 0100 EXECUTE AN0 8 - 11 Protectionkey 0101 BRANCHAN0 LINK COMPARE LOGICAL 12 ASCIImode(A) 0110 BRANCH ONCOUNT OR 13 Machinecheck mask (M) 0111 BRANCH/CONOITlON EXCLUSIVE OR 14 wait state (w) 1000 LOAD LOAD LOAD LOAO 15 Problemstate (P) I001 COMPARE COMPARE COMPARE COMPARE 16 - 31 Interruptioncode 1010 ADO ADD A00N ADO N 32 - 33 InstructionLength code (ILC) 1011 SUBTRACT SUBTRACT SUBTRACTN SUBTRACTN 34 - 35 Conditioncode (CC) 1100 MULTIPLY MULT IPLY MULTIPLY MULTIPLY 36 - 39 Programmark 1101 DIVIDE OIVIOE DIVIDE 36 Fixed-pointoverflow mask 1110 CONVERT-DECIMAL ADO LOGICAL ADDU A00U 37 DecimaloverfLou mask 1111 CONVERT-BINARY SUBTRACTLOGICAL SUBTRACTU SUBTRACTU 38 ExponentunderfLow mask 39 Significancemask Appendix I continued Appendix 2 continued

FO R M A T RS.SI FORMAT RSsSI ChannelCommand Word BRANCHING, FIXED-POINT. CLASSSTATUS SWITCHING LOGICAL. AND ~O-O-O-O-O-O-O-O-O-O-1-1-1-1-1-1-1-1-1-1-2-2-2-2-2-2-2-2-2-2-3-3~- """"-"_AND SHIFTING lNeL!lLoUlPuI I I I I COMMAND CODE I DATA ADDRESS I xxxx loooxxxx loolxxxx loloxxxx 1OllXXXX LO-1-2-3-4-5-6-7-8-9-0-1-2-3-4-5-8-7-8-9-0-~-2-3-4-5-6-7-~-9-0-~J---I I I

0000 SETSYSTEM MASK STORE MULTIPLE 0001 TEST UNDERMASK -r3-3-3-3-3-3-3-3-4-4-4-4-4-4-4-4-4-4-5-5-5-5-5-5-5-5-5-5-6-6-6-6~ 0010 LOAD PSW MOVE I I I I I 0011 DIAGNOSE I FLAGS IO 0 01 I COUNT I 0100 WRITEDIRECT AN0 I I I I I 0101 REA0DIRECT COMPARE LOGICAL "~2-3-4-5-6-7-8-9-0-1-2-3-4-5-6-7-0-9-0-1-2-3-4-5-6-7-8-9-0-1-2-3J 0110 BRANCH/HIGH OR 0111 BRANCH/LOW-EQUAL EXCLUSIVE OR 0 - 7 Commandcode 1000 SHIFTRIGHT SL LOA0MULTIPLE 8 - 31 Dataaddress 1001 SHIFTLEFT SL 32 - 36 Command flags 1010 SHIFT RIGHT S 32 Chaindata flag 1011 SHIFT LEFT S 33 Chaincommand flag 1100 SHIFT RIGHTDL START I/O 34 Suppresslength indication flag 1101 SHIFT LEFTDL TEST 1/0 35 Skipflag 1110 SHIFT RIGHT D HALT 1/0 36 Program-controlledinterruption flag 1111 SHIFT LEFT D TESTCHANNEL 37 - 39 Zero 40 - 47 Ignored 48 - 63 Count FORMAT 5s CLASS oEZlMAL ChannelAddress Word rO-O-O-O-O-O-O-O-O-O-1-1-1-1-1-1-1-1-1-1-2-2-2-2-2-2-2-2-2-2-3-~, xxxx llooxxxx lll0xxxx 1lllXXXX I I I 0000 I KEY 10 0 0 01 COMMAND ADDRESS I 0001 MOVE NUMERIC MOVE W OFFSET L0-1-2-3-4-5-6-7-8-9-0-1"3-4-5-6-7-8-9-0-1-2-3-4-5-6-7-8-9-~-~JI I I I 0010 MOVE PACK 0011 MOVE ZONE UNPACK 0100 AND 0 - 3 Protectionkey 0101 COMPARE LOGICAL 4 - 7 Zero 0110 OR 8 - 31 Commandaddress 0111 EXCLUSIVE OR 1000 ZEROAND ADD 1001 COMPARE ChannelStatus Word 1010 ADO 1011 SUBTRACT r0-0-0-0-0-0-0-0-0-0-~-1-1-1-~-1-~-~-1-1-2-~-2-~-~-~~~-~-~~~~3~3,~~~ 1100 TRANSLATE MULTIPLY I I I 1101 TRANSLATEAND TESl DIVIDE I KEY IO 0 0 01 COMMAND ADDRESS I 1110 EDIT IL0-1-2-3-4-5-6-7-8-9-0-1-2-3-4-5-6-7-8-9-0-1-2-3-4-5-6-7-~-g-0-~~-- I I I 1111 EDIT AND MARK

"r3~3"3"3"3"3"3~3"4-4"4"4-4-4-4-4-4-4-5-5-5-5-5-~-5-5-5-5~~-~-~-6, * Legend N = Normalized U = Unnormalized I I I I STATUS I SL = logicalSingle S = Single COUNT I E DL = Double logical D = Double --~2-3-4--5"&7-8-9-O--1-2-3-4--5-6-7-B-9-O-~-~-3-4-~-~-7-~-g-~-~-~-~JI I I m3 n 0 - 3 Protectionkey e 4 - 7 Zero s 8 - 31 Commandaddress m Appendix 2 The formatsof all controlwords required for CPU and 32 - 47 Status 32 Attention % channel operation are shown in the following table. Thebase and 33 Statusmodifier 1 34 Control unit end index registers provide 24 bits of address and are specified by the 35 Busy 1 36 Channelend B and X fields of instructions.The Program Status Word controls 37 Deviceend 38 Unitcheck E instructionsequencing and indicatesthe complete CPU status apart 39 Unitexception VJ 40 Program-controlledinterruption 2 (continued overleaf) 1 F -.w m d 0 rg 9 d 6 8 -F m Appendix 2 continued Appendix 4 continued

41 Incorrectlength LSSSEd i 42 Programaheck 43 Protectioncheck avallablaUnlt and channel available 44 Channeldata check busy Unit or channel busy 5 45 Channelcontrol check carry A carryout ofthe sign position occurs m 46 Interfacecontrolcheck complete Last result byte nonzero 47 Chainingcheck CSW ready Channel status word ready for test or interruption 48 - 63 Count CSW stored Channel status word stored equal. Operandscompareequal E F FuLlword g zero Result is greater than zero Appendix 3 All permanently assigned storage locations are shown in H Halfword haltedData transmission stopped. Unit inhalt-reset mode this table. These locations are addressed by the CPU and 1/0 chan- high Flrst operand compares high incomplete Nonzero result byte; not last nels during initial program loading, during interruptions and in L precision Long 1 zero Result is less than zero order to update the timer. During initial program loading 24 bytes LOW First operand compares low mixedSelected bits are both zero and one are read from a specified input device into locations 0 to This notoper Unlt or channelnot operational 23. notworking Unit or channelnot working information is subsequently used as CCW's to specify the locations not zero Result is not all Zero one Selected bits are one sverflowResultoverftows of further input information and as a PSW to control CPU operation S Short precision stopped Data transmlssion stopped after the loading operation is completed. During an interruption the working Unit or channel working current PSW is stored in the "old" location and the PSW from the zero Result or selected bits are zero

"new" location is obtained as the next PSW. The timer is counted lscn

downand provides an whenzero is passed. All perma- The conditlon code also may be changed by LOA0PSW. SET SYSTEM MASK. nently assigned locations may also be addressed by the program. DIAGNOSE. and by an Interruption..

Appendix 5 All interruptions which may occur are shown in the fol- PERMANENT STORAGE ASSIGNMENT lowing table.Indicated here arethe code in the old PSW which AOPBESS CENGIY EuREQsE identifies the source of the interruption, the mask bits which may be 0 0000 0000 double word Initial program Loading PSW 8 0000 1000 double word Initial program loading CCWl used to prevent an interruption, and the manner in which instruction 16 0001 0000 double word Initlal program loadlng CCW2 24 0001 1000 doubleword External old PSW execution is affected. The instruction to be performed next if the in- 32 0010 0000 doubleword Supervisor call old PSW 40 0010 1000 double word Program old PSW terruption had not occurred is indicated in theinstruction address 48 0011 0000 double word Machine old PSW 56 00111000 double word Input/output old PSW 64 0100 0000 doubleword Channel status word field of the old PSW. The length of thepreceding instructions, if 72 0100 1000 word Channel address word 76 0100 1100 word Unused available, is shown in the instruction length code, ILC, as is further 80 0101 0000 Timerword 84 01010100 word Unused detailed in the table. 88 0101 1000 double word External new PSW 96 0110 0000 double word Supervisor call new PSW 104 0110 1000 doubleword Program new PSW INTERRUPTION ACTION 112 0111 0000 doubleword Machine new PSW 120 0111 1000 doubleword Input/output new PSW INTERRUPTIONSOURCE INTERRUPTION CODE MASK ILC INSTRUCTION 128 1000 0000 Diagnosticscan-outarea* IPPNIIF~eLIQN------PBI-BIls"srLS- "- I=euf&uf& (old PSW 56. new PSW 120. priority 4) The size of the dlagnostic scan-out area depends upon the particular Multiplexor channel 00000000 aaaaeaaa 0 x complete model and 1/0 channels. Selector channel 1 00000001 aaaaaaaa 1 x complete SeLector channel 2 00000010 aaaaaaaa 2 x complete Appendix 4 All instructions which set the condition code (bits 32 and Appendix 5 continued Selectorchannel 3 00000011aaaaaaaa 3 x complete 33 of the PSW) are listed in the following table. All other instructions Selectorchannel 4 00000100aagaaaaa 4 x complete Selectorchannel 5 00000101aaaaaaaa 5 x complete leave the condition code unchanged. Theeondition code determines Selectorchannel 6 00000110aaaaaaaa 6 x complete

the outcome of a BRANCH ON CONDITION instruction. The four-bit mask e~sgrsm(old PSW 40.new PSW 104.priority 2)

contained in this instruction specifies which code settings will cause Operation 00000000 00000001 1.2.3 suppress Privilegedoperation 00000000 00000010suppress 1.2 the branch to be taken. Execute 00000000 00000011 2 suppress Protection 00000000 00000100suppress/terminate0.2.3 Addressing 00000000 00000101011.2.3 suppre4s/terminate Specification 00000000 00000110 1.2.3 suppress Data terminate 000000002.3 00000111 Fixed-pointoverflow 00000000 0000100036 1.2 complete CONDITION CODE SETTING Fixed-pointdivide 00000000 00001001 1.2 suppress/complete Decimaloverflow 00000000 00001010 37 3 complete Decimaldivide 00000000 00001011 3 suppress Q -2 a Exponentoverflow 00000000 00001100 1.2 terminate Exponentunderflow 00000000 0000110138 1.2 complete ElX+P-PQini-&iihm.S*iS Significance 00000000 0000111039 1.2 complete ADO H/F zepo 1 zero g zero overflow Floating-pointdivide 00000000 00001111suppress1.2 ADD LOGICAL zero not zero zero.cart-y carry COMPARE H/F equal LOW high " Bgeqrvlgnr Call(old PSW 32.new PSW 96. priority2)

LOAD AND TEST zero 1 zero g zero " . LOAD COMPLEMENT zero 1 zero g zero overflow Instructionbits 00000000 rrrrrrrr 1 complete LOADNEGATIVE zero 1 zero " " LOA0POSITIVE " zero g zero overflow -External"""_ (old PSW 24. new PSW 88. priority 3) SHIFTLEFT DOUBLE zero 1 zero g zero overflow SHIFTLEFT SINGLE zero 1 zero g zero overflow Externalsignal 1 00000000 xxxxxxxl 7 x complete SHIFTRIGHT DOUBLE zero 1 zero g zero " Externalsignal 2 00000000 xxxxxxlx 7 x complete SHIFTRIGHT SINGLE zero 1 zero g zero " Externalsignal 3 00000000 xxxxxlxx 7 x complete SUBTRACT H/F zero 1 zero g zero overflow Externalsignal 4 00000000 xxxxlxxx 7 x complete SUBTRACT LOGICAL " notzero zeroscarry carry Externalsignal 5 00000000 xxxlxxxx 7 x complete Externalsignal 6 00000000 xxlxxxxx 7 x complete -Dqcimal """_" Arithm&j= Interruptkey oooooooo XlxxxxxX 7 X complete ADO DECIMAL zero 1 zero goverflow zero Timer 00000000 1xxxxxxx 7 x complete COMPARE DECIMAL equal low high " SUBTRACT DECIMAL zero L zero g overflowzero MachineCheck (old PSW 48.new PSW 112,priority 1) ZEROADD AND zero L zero overflowg zero Machinemalfunction 00000000 00000000 13 x terminate FlQntinS=el?inlt-Arithmmtlc ADO NORMALIZEDS/L zero 1 zero g zero overflow Lrams! ADD UNNORMALIZED S/L zero 1 zero g zero overflow COMPARE S/L equal Low high " a Deviceaddress bits LOAD AND TESTS/L zero L zero g zero " r Bitsof R1 and R2 field of SUPERVISORCALL LOAD COMPLEMENTzero S/L 1 zero g zero " x Unpredictable LOADNEGATIVE S/L zero L zero " " L O A D POSITIVE S/L zeroPOSITIVELOAD S/L " g zero " SUBTRACT NORMALIZEDS/L Zero 1 zero g zero overflow b !a SUBTRACTUNNORMALIZEO S/Lzero 1 zero g zero overflow Q Ll?alS*l-Q2SCStiQEi =i AND zero notzero " " INSTRUCTIONLENGTH RECORDING nrn COMPAREequal LOGICAL LOW high " EDIT zero 1 zero g zero " 2 EDIT ANDMARK zero 1 zero g zero " INSTRUCTION PSW INSTRUCTIONBITS INSTRUCTION INSTRUCTION EXCLUSIVE OR zero notzero " " L%t?4ln_cQo€""a~~"""-~~~~-Q=~"""-L~t?4l~""""-FQ~~~~ OR zero notzero " " TEST UNDER MASK zero mixed " one % TRANSLATE AND TEST zero incomplete complete " 0 00 Notavailable a2 1 01 halfword00 One RR Ineut=ol?teut-Qet~atinllE 012 10 Two halfwords RX HALT 1/0 haltedworking not stoppedopernot 2 10 10 Two halfwords RS or SI - START 1/0 available CSW storedbusy notoper 11 11 Threehalfwords SS 3 TEST CHANNEL workingnot CSW readyworkingoper not k TEST 1/0 available CSWoper workingstored not v)