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Sensors: Sensing and Data Acquisidon
Sensors: Sensing and Data Acquisi3on Prof. Yan Luo For UMass Lowell 16.480/552 Sensors: Sensing and Data Acquisi3on 1 Prof. Yan Luo, UMass Lowell Outline • Sensors • Sensor interfacing • Sensor data conversion and acquisi3on • PIC microcontroller programming • Lab 1: Sensor design and data acquisi3on (a light intensity sensor) Sensors: Sensing and Data Acquisi3on 2 Prof. Yan Luo, UMass Lowell Basic Principle of Sensors • Transducer: a device that converts energy from one form to another • Sensor: converts a physical parameter to an electric output – Electric output is desirable as it enables further signal processing. • Actuator: coverts an electric signal to a physical output Sensors: Sensing and Data Acquisi3on 3 Prof. Yan Luo, UMass Lowell Sensors • Cameras • Analog sensors • Accelerometer - Con3nuously varying output • Rate gyro • Digital sensors • Strain gauge - on/off • Microphone - Pulse trains (freq convey measurement) • Magnetometer • Chemical sensors • Op3cal sensors Sensors: Sensing and Data Acquisi3on 4 Prof. Yan Luo, UMass Lowell Example: Photoresistor • Or Light Dependent Resistor (LDR) – Resistance decreases with increasing light intensity – Made of semiconductor – Photons absorbed cause electrons to jump into conduc3on band Sensors: Sensing and Data Acquisi3on 5 Prof. Yan Luo, UMass Lowell Interfacing with Sensors • Interface circuitry • ADC • Interfaces of the embedded system • SoVware drivers and APIs Sensors: Sensing and Data Acquisi3on 6 Prof. Yan Luo, UMass Lowell Example voltage divider circuit Vcc R2 V=Vcc x R1/(R1+R2) V R1 Sensors: Sensing and Data Acquisi3on 7 Prof. Yan Luo, UMass Lowell Analog-Digital Converter (ADC) • Types of ADC – Integrang ADC • Internal voltage controlled oscillator • slow – Successive approximaon ADC • Digital code driving the analog reference voltage – Flash ADC • A bank of comparators • Fast Sensors: Sensing and Data Acquisi3on 8 Prof. -
"Firefly" Z80 General-Purpose Retro Computing Platform
"FIREFLY" Z80 GENERAL-PURPOSE RETRO COMPUTING PLATFORM THREE FARTHING LABS http://www.threefarthing.com Page 1 of 13 PREFACE A project has to have a name and this one wound up being called "Firefly" as it©s the culmination of a wirewrap board begun several years ago while binge-watching the series of the same name. That board, in turn, was a redesign of a single board computer I created in 1998, creatively named the "SBCZ1." All three of these projects were begun as a chance to tinker with a processor I first met hands- on in 1984, the ZiLOG Z-80, though it was long-established by that time and dominated the business computer market. It was the CPU of preference behind most CP/M machines and CP/M was what I wanted to tinker with again, from the ground up ± not in some cozy emulator. When I began preparing to design the board I looked around on the Internet and found many excellent Z80 projects, including kit options. The choice was made to "roll my own" for numerous reasons. In the SBCZ1 I had most of a good design and wanted to retain a lot of hard work (done before I had Internet access, mind you). There were also specific reasons for wanting "to stay within ZiLOG canon" and work with a particular hardware configuration. I saw no kits that did just what I wanted in the way that I wanted. There was also a desire to maintain modularity and be extensible but not require a proliferation of modules for what I considered core functionality, yet great restraint was employed to keep "core functionality" spartan. -
Efficient Automated Code Partitioning for Microcontrollers with Switchable
Efficient Automated Code Partitioning for Microcontrollers with Switchable Memory Banks MICHAL CISZEWSKI and KONRAD IWANICKI, University of Warsaw 114 Switching active memory banks at runtime allows a processor with a narrow address bus to access memory that exceeds ranges normally addressable via the bus. Switching code memory banks is regaining interest in microcontrollers for the Internet of Things (IoT), which have to run continuously growing software, while at the same time consuming ultra-small amounts of energy. To make use of bank switching, such software has to be partitioned among the available banks and augmented with bank-switching instructions. In contrast to the augmenting, which is done automatically by a compiler, today the partitioning is normally done manually by programmers. However, since IoT software is cross-compiled on much more powerful machines than its target microcontrollers, it becomes possible to partition it automatically during compilation. In this article, we thus study the problem of partitioning program code among banks such that the resulting runtime performance of the program is maximized. We prove that the problem is NP-hard and propose a heuristic algorithm with a low complexity, so that it enables fast compilation, and hence interactive software development. The algorithm decomposes the problem into three subproblems and introduces a heuristic for each of them: (1) Which pieces of code to partition? (2) Which of them to assign to permanently mapped banks? and (3) How to divide the remaining ones among switchable banks? We integrate the algorithm, together with earlier ones, in an open-source compiler and test the resulting solution on synthetic as well as actual commercial IoT software bases, thereby demonstrating its advantages and drawbacks. -
Zilog Developer Studio II
Z8 Encore!® Microcontroller Zilog Developer Studio II Product Brief PB009708-1010 Zilog Developer Studio II ZDS II Products Integrated for the Z8 Encore! Assembler ez8asm Introduction Compiler ez8cc Zilog Developer Studio II (ZDS II) Integrated Linker ez8link Development Environment is a complete stand- Librarian ez8lib alone system that provides a state-of-the-art devel- opment environment. Based on standard Windows Simulator Yes user interfaces, ZDS II integrates a language-sensi- Flash Loader Yes tive editor, project manager, C-Compiler, assem- Host Communication RS-232, USB, Ethernet bler, linker, librarian, and source-level symbolic debugger to provide a development solution specif- Figure 1 illustrates a typical display interface ically tailored to the Z8 Encore! line of microcon- showing many of the features of ZDS II. trollers. Figure 1. ZDS II’s Easy-To-Use Interface ZiLOG Worldwide Headquarters • 1590 Buckeye Drive • Milpitas, CA 95035 Telephone: 408.513.1500 • Fax: 408.365.8535 • www.zilog.com Zilog Developer Studio II for the Z8 Encore!® Microcontroller Product Brief 2 Easy-To-Use Interface • Download, Execute, Debug, and Analyze ZDS II provides a standard user interface with • Language-sensitive editor intuitive, easy-to-use controls commonly found in • Print the disassembly, call stack, symbol, ® Windows -based environments. The system con- memory and register window outputs for tains an integrated set of windows, document future reference views, menus, and toolbars to create, test and refine applications without having to alternate • Symbolic source-level debugging for C and between different systems. assembly languages • Online Help Flexible and Adaptable Design • Full-featured assembler and linker Capabilities • Interleaved source and disassembly Designed to use the multithreading capability of the host operating system, multiple operations can • Makefile generation be performed efficiently and easily with ZDS II. -
Oral History Panel on the Development and Promotion of the Zilog Z8000 Microprocessor
Oral History Panel on the Development and Promotion of the Zilog Z8000 Microprocessor Moderator: Michael Slater Panelists: Federico Faggin Bernard Peuto Masatoshi Shima Ralph Ungermann Recorded: April 27, 2007 Mountain View, California CHM Reference number: X4022.2007 © 2007 Computer History Museum Michael Slater: We have with us today [April 27, 2007] four people who were involved in its [Zilog Z8000 microprocessor] creation: Ralph Ungermann, Bernard Peuto, Federico Faggin, and Masatoshi Shima. We’ve heard about the backgrounds from Shima-san, Federico and Ralph in the previous tape [oral history by the Z80 team], so we’ll start with Bernard. Could you tell us about your educational background, your experience before you came to this project? Bernard Peuto: Yes. I was born in France where I got an engineering education in radio and in computers in 1967 and 1968. I came to Berkeley to do a Ph.D. In 1969, I had my Master of Arts from Berkeley in computer science and I passed my prelim. I went back to do my military duties and then I came back and got a Ph.D. in computer science in 1974. My dissertation was about memory protection, which will come back as a subject later. As my first job I joined Amdahl Corporation from 1973 to 1976. The reason I joined Amdahl Corporation was that Charlie Bass was sharing an office with me when he was an assistant professor at Berkeley and I was a Ph.D. student and Charlie Bass had a good friend of his that was working at Fujitsu so through that connection I was hired as a computer architect at Amdahl Corporation. -
Microprocessors in the 1970'S
Part II 1970's -- The Altair/Apple Era. 3/1 3/2 Part II 1970’s -- The Altair/Apple era Figure 3.1: A graphical history of personal computers in the 1970’s, the MITS Altair and Apple Computer era. Microprocessors in the 1970’s 3/3 Figure 3.2: Andrew S. Grove, Robert N. Noyce and Gordon E. Moore. Figure 3.3: Marcian E. “Ted” Hoff. Photographs are courtesy of Intel Corporation. 3/4 Part II 1970’s -- The Altair/Apple era Figure 3.4: The Intel MCS-4 (Micro Computer System 4) basic system. Figure 3.5: A photomicrograph of the Intel 4004 microprocessor. Photographs are courtesy of Intel Corporation. Chapter 3 Microprocessors in the 1970's The creation of the transistor in 1947 and the development of the integrated circuit in 1958/59, is the technology that formed the basis for the microprocessor. Initially the technology only enabled a restricted number of components on a single chip. However this changed significantly in the following years. The technology evolved from Small Scale Integration (SSI) in the early 1960's to Medium Scale Integration (MSI) with a few hundred components in the mid 1960's. By the late 1960's LSI (Large Scale Integration) chips with thousands of components had occurred. This rapid increase in the number of components in an integrated circuit led to what became known as Moore’s Law. The concept of this law was described by Gordon Moore in an article entitled “Cramming More Components Onto Integrated Circuits” in the April 1965 issue of Electronics magazine [338]. -
The Ultimate C64 Overview Michael Steil, 25Th Chaos Communication Congress 2008
The Ultimate C64 Overview Michael Steil, http://www.pagetable.com/ 25th Chaos Communication Congress 2008 Retrocomputing is cool as never before. People play Look and Feel C64 games in emulators and listen to SID music, but few people know much about the C64 architecture A C64 only needs to be connected to power and a TV and its limitations, and what programming was like set (or monitor) to be fully functional. When turned back then. This paper attempts to give a comprehen- on, it shows a blue-on-blue theme with a startup mes- sive overview of the Commodore 64, including its in- sage and drops into a BASIC interpreter derived from ternals and quirks, making the point that classic Microsoft BASIC. In order to load and save BASIC computer systems aren't all that hard to understand - programs or use third party software, the C64 re- and that programmers today should be more aware of quires mass storage - either a “datasette” cassette the art that programming once used to be. tape drive or a disk drive like the 5.25" Commodore 1541. Commodore History Unless the user really wanted to interact with the BA- SIC interpreter, he would typically only use the BA- Commodore Business Machines was founded in 1962 SIC instructions LOAD, LIST and RUN in order to by Jack Tramiel. The company specialized on elec- access mass storage. LOAD"$",8 followed by LIST tronic calculators, and in 1976, Commodore bought shows the directory of the disk in the drive, and the chip manufacturer MOS Technology and decided LOAD"filename",8 followed by RUN would load and to have Chuck Peddle from MOS evolve their KIM-1 start a program. -
Z80 Bank-Switching Scheme An101
Z80 BANK-SWITCHING SCHEME AN101 1. INTRODUCTION 1. Scope: This Application Note gives a description of a circuit design allowing the classic Z80 microproces- sor to access expanded memory, beyond the 64K bytes made readily available by its 16 address lines, A0 through A15. 2. Z80 microprocessor: Though it has been over 20 years since the introduction of the Z80, this family of microprocessors still finds application in new designs. This is because the Z80 is still cost-effective for many 8-bit applications; because many users have a large library of tested code for the Z80; and because the parts are readily available from several manufacturers, easing supply concerns that apply to sole-sourced processors. 3. Applicable chips: This Application Note applies to the classic Z80 microprocessor. It can also be applied to the newer Z84C15, which comprises a Z80 CPU, a clock generator, four Z80 CTC channels, two Z80 SIO channels, DMA, chip select signals, and glue logic in a 100-pin quad flat pack. However this external bank-switching circuitry is not necessary for members of the Z80180 family, which have a built-in MMU (memory management unit) on-chip. 2. DESIGN GOALS 1. Program memory: We wanted to expand program memory space to 128K bytes for our application. We needed to support in-circuit reprogramming, so we chose the AMD 29F010 flash memory device. This +5 volt part does not require a +12 volt power supply for programming. After the flash chip is initially programmed at the factory with the bootstrap loader and the current application code, it can later be reprogrammed in the field over the RS-232 serial port. -
Introduction to PIC 18 Microcontrollers
Mod-5: PIC 18 Introduction 1 Module 5 Contents: Overview of PIC 18, memory organisation, CPU, registers, pipelining, instruction format, addressing modes, instruction set, interrupts, interrupt operation, resets, parallel ports, timers, CCP. Features of the PIC18 microcontroller 8-bit CPU 2 MB program memory space 256 bytes to 1KB of data EEPROM Up to 3968 bytes of on-chip SRAM 4 KB to 128KB flash program memory Sophisticated timer functions that include: input capture, output compare, PWM, real- time interrupt, and watchdog timer Serial communication interfaces: SCI SPI I2C and CAN Background debug mode (BDM) 10-bit A/D converter Memory protection capability Instruction pipelining Operates at up to 40 MHz crystal oscillator Overview of the PIC18 MCU Microchip has introduced six different lines of 8-bit MCUs over the years: 1. PIC12XXX: 8-pin, 12- or 14-bit instruction format 2. PIC14000: 28-pin, 14-bit instruction format (same as PIC16XX) 3. PIC16C5X: 12-bit instruction format 4. PIC16CXX: 14-bit instruction format 5. PIC17: 16-bit instruction format 6. PIC18: 16-bit instruction format Each line of the PIC MCUs supports different number of instructions with slightly different instruction formats and different design in their peripheral functions. This makes products designed with a different family of PIC MCUs incompatible. The members of the Muhammed Riyas A.M, Assistant Professor,Department of E.C.E, M.C.E.T Pathanamthitta Mod-5: PIC 18 Introduction 2 PIC18 family share the same instruction set and the same peripheral function design and provide from eight to more than 80 signal pins. -
Microcontrollers Apnote AP0821
查询AP0821供应商 捷多邦,专业PCB打样工厂,24小时加急出货 Microcontrollers ApNote AP0821 o additional file APXXXX01.EXE available C5xx / 80C5xx In-System FLASH Programming The following approach describes the proceeding for in-system reprogramming of an external (5V-only) FLASH code memory by using the internal ROM code. Due to the ´Havard Architecture´, an additional external logic (PLD) is used for a software switching mechanism between code and data memory. K. Scheibert / Siemens HL MC AT Semiconductor Group 08.96, Rel. 01 C5xx / 80C5xx In-System FLASH Programming 1 Memory Organization............................................................................................. 4 2 Hardware Description............................................................................................. 5 3 Functional Description of the ROM Software Routine ........................................ 7 AP0821 ApNote - Revision History Actual Revision : Rel.01 Previous Revison: Rel. none Page of Page of Subjects changes since last release) actual Rel. prev. Rel. Semiconductor Group 2 of 7 AP0821 08.96 C5xx / 80C5xx In-System FLASH Programming In-System FLASH Programming with hardware implemented bank switching capability The following information concerns all microcontrollers of the C5xx / SAB 80C5xx family which use an internal ROM mask in combination with an external code FLASH memory. The external FLASH memory can be used as reprogrammable code memory for the application software. This application focuses on SIEMENS 8-bit microcontroller derivatives with internal code memory (ROM) sizes of 8/16 Kbyte in maximum because of the overlapped code memory area of the FLASH memory of 8/16 Kbyte cannot be used: • C501-1R • C502-2R • C504-2R • C511(A)-R • C513(A)-R/-2R • C515-1R • SAB 80C535 • SAB 80C537 This application note describes the proceeding for the in-system reprogramming of application software by using special application hardware for memory bank switching and software programming service routines in the internal mask programmable ROM for external FLASH memories (5V-only). -
The Triumphant March of the 6502.Pdf
INFOTAINMENT THE 6502 The Triumphant March 30-year old design still inspires thousand Roelf Sluman Are eight-bit processors something from the past or is it still possible to do some- thing useful with them? Elektor Electronics went looking and discovered that the good-old 6502, in a world of threaded computing and dual-core processors, still has a following of faithful fans. In the 1970’s and 80’s three 8-bit processors dominated elegant 8-bit processor. Many thousands of enthusiasts the market: the 6809 from Motorola, the Z80 from Zilog across the whole world still work daily with the 6502 and the 6502 from MOS. By far the most popular of and make it do things that were not considered possible these three was the in 1975. 6502: its low cost (when introduced, the 6502 set you back about 25 dol- Price war History lars) and the advanced The 6502 processor cele- design for its time made When the 6502 was introduced in 1975 it cost brates its 30th anniver- sure that the 6502 con- about 25 dollars. That made it a serious com- sary this year. The intro- quered the world in a petitor to the processor it was copied from, the duction was preceded by short time as the brain in 6800, which by comparison costs a whopping a scandal: the designers popular home-computers 179 dollars. No wonder computer manufacturers of the 6502 had, in the such as the such as Apple and Commodore went for the first instance, developed Commodore 64 and the 6502. -
Unlimited Code and Data Support for the Zilog® Z80 & Z180 Family Of
White paper: Unlimited code and data support for the ZiLOG® Z80 & Z180 family of microprocessors. Softools’ development tools provide software engineers and programmers innovative and seemless code and data support for program development. These tools, along with ZiLOG's high performance Z180 processors, extend the life of these 8-bit processors. ZiLOG's Z180 Family Peripherals and Processor Performance a Platform for Users to Innovate The Z180 is ZiLOG's second generation Z80 based processor family. Building on its world famous Z80, ZiLOG's Z180 offers several feature and improvement that have made it an attractive platform for those who require higher CPU performance as well as peripheral integration. The Z180 CPU executes Z80 more efficiently, resulting in faster code throughput compared to a Z80 based system operating at the same speed. In addition, the Z180 family integrate a number of peripherals including high speed communication ports. One of the more used peripherals, however, is the Memory Management Unit, or MMU. This peripheral allow the Z180 family to address up to 1 Mbyte of code through a method called "code banking" or "memory paging" Introduction to Code Banking Code banking, or memory paging, is not a new concept and has been used for decades in many hardware and software systems. Hardware systems typically switch ROM or RAM pages or regions to map in various parts of code or data normally inaccessible. Software systems often paged memory by copying parts of program or data from one area or medium to a common paging area. This method is very prominent in the Windows® ZiLOG’s Z180-Class 8-bit Processors operating system.