JESD204B Survival Guide Practical JESD204B Technical Information, Tips, and Advice from the World’S Data Converter Market Share Leader*
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JESD204B Survival Guide Practical JESD204B Technical Information, Tips, and Advice from the World’s Data Converter Market Share Leader* *Analog Devices has a 48.5% global data converter market share, which is more than the next eight competitors combined, according to the analyst firm Databeans in its 2011 Data Converters Report. www.analog.com Contents MS-2374: What Is JESD204 and Why Should We Pay Attention to It? ................................................................................................2 MS-2304: High Speed Converter Survival Guide: Digital Data Outputs ..............................................................................................6 MS-2442: JESD204B vs. Serial LVDS Interface Considerations for Wideband Data Converter Applications ......................................10 MS-2448: Grasp the Critical Issues for a Functioning JESD204B Interface .....................................................................................14 MS-2433: Synchronizing Multiple ADCs Using JESD204B ...............................................................................................................21 MS-2447: Three Key Physical Layer (PHY) Performance Metrics for a JESD204B Transmitter .........................................................23 MS-2446: The ABCs of Interleaved ADCs ........................................................................................................................................31 MS-2438: New, Faster JESD204B Standard for High Speed Data Converters Comes with Verification Challenges ..........................36 MS-2503: Slay Your System Dragons with JESD204B .....................................................................................................................44 MS-2672: JESD2048 Subclasses (Part 1): An Introduction to JESD2048 Subclasses and Deterministic Latency .............................48 MS-2677: JESD204B Subclasses (Part 2): Subclass 1 vs. Subclass 2 System Considerations .........................................................54 MT-201: Interfacing FPGAs to an ADC Converter’s Digital Data Output ............................................................................................60 AD9144: Quad, 16-Bit, 2.8 GSPS, TxDAC+® Digital-to-Analog Converter Data Sheet (Page 1) .........................................................70 AD9234: 12-Bit, 1 GSPS JESD204B, Dual Analog-to-Digital Converter Data Sheet (Page 1) ............................................................71 AD9250: 14-Bit, 170 MSPS/250 MSPS, JESD204B, Dual Analog-to-Digital Converter (Page 1) .......................................................72 AD9625: 12-Bit, 2.5/2.0 GSPS, 1.3 V/2.5 V Analog-to-Digital Converter (Page 1) ............................................................................73 AD9675: Octal Ultrasound AFE With JESD204B (Page 1) .................................................................................................................74 AD9680: 14-Bit, 1 GSPS JESD204B, Dual Analog-to-Digital Converter (Page 1) ..............................................................................75 More JESD204 Information .............................................................................................................................................................76 1 | JESD204B Survival Guide Technical Article MS-2374 . routed to both the converter(s) and the receiver and provides What Is JESD204 and Why the clock for the JESD204 link between the devices. Should We Pay Attention to It? by Jonathan Harris, Applications Engineer, Analog Devices, Inc. A new converter interface is steadily picking up steam and looks to become the protocol of choice for future converters. This new interface, JESD204, was originally rolled out several years ago but has undergone revisions that are making it a much more attractive and efficient converter interface. As Figure 1. JESD204 Original Standard the resolution and speed of converters has increased, the demand for a more efficient interface has grown. The JESD204 The lane data rate is defined between 312.5 Megabits per interface brings this efficiency and offers several advantages second (Mbps) and 3.125 Gigabits per second (Gbps) with over its CMOS and LVDS predecessors in terms of speed, both source and load impedance defined as 100 Ω ±20%. size, and cost. Designs employing JESD204 enjoy the benefits of The differential voltage level is defined as being nominally a faster interface to keep pace with the faster sampling rates 800 mV peak-to-peak with a common-mode voltage level of converters. In addition, there is a reduction in pin count range from 0.72 V to 1.23 V. The link utilizes 8b/10b encoding which leads to smaller package sizes and a lower number of which incorporates an embedded clock, removing the trace routes that make board designs much easier and offers necessity for routing an additional clock line and the associated lower overall system cost. The standard is also easily scalable complexity of aligning an additional clock signal with the so it can be adapted to meet future needs. This has already transmitted data a high data rates. It became obvious, as the been exhibited by the two revisions that the standard has JESD204 standard began gaining popularity, that the undergone. The JESD204 standard has seen two revisions standard needed to be revised to incorporate support for since its introduction in 2006 and is now at Revision B. As multiple aligned serial lanes with multiple converters to the standard has been adopted by an increasing number of accommodate increasing speeds and resolutions of converter vendors and users, as well as FPGA manufacturers, it converters. has been refined and new features have been added that have This realization led to the first revision of the JESD204 increased efficiency and ease of implementation. The standard standard in April of 2008 which became known as JESD204A. applies to both analog-to-digital converters (ADCs), as well This revision of the standard added the ability to support as digital-to-analog converters (DACs) and is primarily multiple aligned serial lanes with multiple converters. The intended as a common interface to FPGAs (but may also be lane data rates, supporting from 312.5 Mbps up to 3.125 Gbps, used with ASICs). remained unchanged as did the frame clock and the electrical JESD204—WHAT IS IT? interface specifications. Increasing the capabilities of the standard to support multiple aligned serial lanes made it In April of 2006, the original version of JESD204 was possible for converters with high sample rates and high released. The standard describes a multigigabit serial data resolutions to meet the maximum supported data rate of link between converter(s) and a receiver, commonly a device 3.125 Gbps. Figure 2 shows a graphical representation of the such as an FPGA or ASIC. In this original version of JESD204, additional capabilities added in the JESD204A revision to the serial data link was defined for a single serial lane between a support multiple lanes. converter or multiple converters and a receiver. A graphical representation is provided in Figure 1. The lane shown is the physical interface between M number of converters and the receiver which consists of a differential pair of interconnect utilizing current mode logic (CML) drivers and receivers. The link shown is the serialized data link that is established between the converter(s) and the receiver. The frame clock is www.analog.com Page 1 of 4 ©2013 Analog Devices, Inc. All rights reserved. JESD204B Survival Guide | 2 MS-2374 Technical Article Figure 3. Second (Current) Revision—JESD204B In the previous two versions of the JESD204 standard, there Figure 2. First Revision—JESD204A were no provisions defined to ensure deterministic latency Although both the original JESD204 standard and the through the interface. The JESD204B revision remedies this revised JESD204A standard were higher performance than issue by providing a mechanism to ensure that, from power- legacy interfaces, they were still lacking a key element. This up cycle to power-up cycle and across link re-synchronization missing element was deterministic latency in the serialized events, the latency should be repeatable and deterministic. data on the link. When dealing with a converter, it is important One way this is accomplished is by initiating the initial lane to know the timing relationship between the sampled signal alignment sequence in the converter(s) simultaneously across and its digital representation in order to properly recreate all lanes at a well-defined moment in time by using an input the sampled signal in the analog domain once the signal has signal called SYNC~. Another implementation is to use the been received (this situation is, of course, for an ADC, a SYSREF signal which is a newly defined signal for JESD204B. similar situation is true for a DAC). This timing relationship The SYSREF signal acts as the master timing reference and is affected by the latency of the converter which is defined aligns all the internal dividers from device clocks as well as for an ADC as the number of clock cycles between the instant the local multiframe clocks in each transmitter and receiver. of the sampling edge of the input signal until the time that its This helps to ensure deterministic latency through the system. digital representation is present at the converter’s outputs. The JESD204B specification calls out three device subclasses: Similarly, in a DAC, the latency is defined as the number