Outphasing RF Power Amplifiers for Mobile Communication Base Station Applications
Differenzphasengesteuerte Hochfrequenz-Leistungsverst¨arker f¨urdie Anwendung in Mobilfunk Basisstationen
der Technischen Fakult¨at der Friedrich-Alexander-Universit¨atErlangen-N¨urnberg
zur Erlangung des Doktorgrades Dr.-Ing.
vorgelegt von M.Sc. Zeid Abou-Chahine aus Al-Manara, Libanon
Als Dissertation genehmigt von der Technischen Fakult¨at der Friedrich-Alexander-Universit¨atErlangen-N¨urnberg
Tag der m¨undlichenPr¨ufung: 18.06.2015
Vorsitzende des Promotionsorgans: Prof. Dr.-Ing. habil. Marion Merklein
Gutachter: Prof. Dr.-Ing. Georg Fischer Prof. Dr.sc.techn. Renato Negra
All praise be to Allah, the Lord of the worlds.
Alles Lob geh¨ortAllah, dem Herrn der Welten.
Abstract
The continuously growing focus on reducing energy consumption worldwide has infiltrated into the telecommunications domain in its both mobile terminals and base stations. This has led eventually to the introduction of advanced power amplifier (PA) architectures.
This work investigates the suitability of outphasing PAs for use as a high efficiency solu- tion in next generation base station applications. Besides the classical Chireix concept, several newly emerging outphasing variants are analyzed and compared. The effects of the nonlinear output capacitance are considered in detail. It is shown that harmonic isolation is vital for the Chireix PA realization using transistor devices. In addition, the power capability of the Chireix outphasing PA is discussed and a load-pull simulation technique for the complete PA is proposed. The findings are used to develop a method for designing practical Chireix PAs.
A proof of concept 60 W Chireix PA prototype using state of the art GaN HEMTs is presented. Measurements with 5 MHz 1-Carrier and 20 MHz 2-Carrier W-CDMA signals of 7.5 dB PAR resulted in respectively 45 % and 44 % average drain efficiencies.
Ubersicht¨
F¨urTelekommunikationsausr¨uster ¡ Endger¨ateherstellerwie Infrastrukturlieferanten ¡ liegt der Schwerpunkt weltweit mehr und mehr auf einem geringen Energieverbrauch. Dieser Schwerpunkt erfordert die Einf¨uhrung fortgeschrittener Leistungsverst¨arker- architekturen.
Diese Arbeit untersucht die Eignung des Outphasing-Konzepts im Hinblick auf hochef- fiziente Leistungsverst¨arker f¨urfortschrittliche Sendestationen der drahtlosen Kommu- nikation. Neben dem klassischen Chireix-Verfahren werden verschiedene moderne Outphasing-Varianten untersucht und gegeneinander abgewogen. Es wird gezeigt, dass es bei Verwendung von Transistoren im Chireix-Verst¨arker vordringlich auf die Isolation der beiden Pfade bei den Vielfachen der Grundfrequenz ankommt. Ferner wird die Eig- nung von Outphasing-Verst¨arkern f¨urhohe Ausgangsleistungen untersucht und ein neues Load-Pull-Simulationsverfahren zur Verst¨arkerentwicklung vorgeschlagen. Die Ergebnisse laufen in einem neuen Entwurfsverfahren f¨urChireix-Leistungsverst¨arker zusammen.
Die Eigenschaften des Entwurfsverfahren werden herausgerabeitet und seine Eignung anhand eines 60 W Chireix-Verst¨arker basierend auf GaN-HEMT-Bauelementen nach- gewiesen. Messungen zeigen bei 7, 5 dB Spitzen- zu Mittelwertleistung einen Wirkungs- grad von 45 % bei einem 5 MHz breiten W-CDMA-Signal, und 44 % bei 2 W-CDMA- Signalen und 20 MHz Signalbandbreite.
Acknowledgements
The completion of the research work presented in this doctoral thesis would not have been affordable without the support of numerous people.
I would like to thank deeply Prof. Dr.-Ing. Georg Fischer for his supervision through- out this phase. His guidance and support have been a great help to me for completing this thesis. I am thankful to all his suggestions and valuable comments. My grateful appreciations are also extended to Prof. Dr.-Ing. Dr.-Ing. habil. Robert Weigel for the opportunity to join the Institute for Electronics Engineering and pursue a doctoral degree at the Friedrich-Alexander University in Erlangen.
This work was funded by Nokia Siemens Networks in Ulm, Germany. I would like to thank NSN for their generous backing. As a member of the Radio Frequency Research and Predevelopment team, I have been surrounded by inspiring advisers and colleagues who have provided me with a productive environment to conduct research and explore new ideas. I would like to thank especially Dr.-Ing. Tilman Felgentreff for the project su- pervision and guidance. His professional assistance has helped me in keeping my progress on schedule. I wish to thank the colleagues in the RF team too, namely Karlheinz Borst, Dr.-Ing. Abhijit Ghose, Helmut Heinz, Norbert H¨uller,Wilhelm Schreiber and Georg Wissmeier for all their support, and last but not least Dr.-Ing. Christoph Bromberger for his support and for the many interesting discussions we made. My thanks are also extended to Dr. Christian Schieblich and his entire team for sharing their technical in- sights in several occasions. The work progress would have been much slower without the support with the remote simulations server. For that, I would like to thank J¨orgZ¨opnek. Also, many thanks go to Hans Jugl for his skilled care when it came to the circuit boards construction. I would like to express my vast appreciations to Frank Dechen. His expert support espe- cially with the DSP board has been much useful. Whenever management and resources issues showed up, Dr.-Ing. Hartmut M¨uller,Sieglinde Zeug and Doris Kalb were just there for providing their help. I would like to thank them for that. For his time in reviewing the thesis, I thank Prof. Dr.sc.techn. Renato Negra from RWTH Aachen.
I thank Kerstin Stoltze from the office of doctoral affairs at the Friedrich-Alexander Uni- versity for her assistance.
I would like to thank my friends and colleagues, Samer Abdallah, Mohammad Amin Abou Harb, Ahmad Awada, Anas Chaaban, Ahmad Al-Samaneh, Christian Musolff and Michael Kamper for their encouragements, cooperation and for the good times we had.
I express my sincere gratitude to my beloved family. I am forever indebted to my parents for their love, encouragement and endless support throughout my life.
Finally, I would like to thank my wife. Her love, kindness and patience have been a great asset for me in completing this thesis. Contents
1 Introduction1 1.1 Background...... 1 1.2 Structure of the Work...... 3
2 Outphasing Architecture Analysis5 2.1 Fundamentals...... 6 2.2 Outphasing with Wilkinson Combiner...... 7 2.2.1 Load Voltage...... 8 2.2.2 Power and Efficiency Calculations...... 10 2.2.3 Amplifier Loads...... 12 2.3 Outphasing with Chireix Combiner...... 13 2.3.1 Chireix Analysis with Ideal Class-B PAs...... 14
3 Emerging Outphasing Variants Study 19 3.1 PA-Engine Analogy...... 19 3.2 A Brief Overview of PA Architectures...... 21 3.3 Variants with an Isolating Combiner...... 22 3.3.1 Outphasing with Energy Recovery (Turbo-LINC)...... 22 3.3.2 Asymmetric Multilevel Outphasing (AMO)...... 24 3.3.3 Modified Multilevel Variants...... 27 3.4 Variants with a Nonisolating Combiner...... 27 3.4.1 Adaptive Compensation with Active Elements...... 27 3.4.2 Input Amplitude Modulated Outphasing (IAMO)...... 27 3.5 Average Efficiency Calculations...... 28 3.6 Outphasing Paradox...... 29
4 Practical Considerations for Chireix PA Design 31 4.1 Technology...... 32 4.2 Maximum Power Capability...... 33 4.3 Transistor Model...... 35
i Contents
4.4 Practical Chireix Analysis...... 37 4.4.1 Nonlinear Output Capacitance...... 38 4.4.2 Implications on Chireix PA Design...... 43 4.4.3 Load Modulation...... 45 4.5 Bandwidth Considerations...... 46 4.5.1 Instantaneous Frequency...... 47 4.5.2 Modulation Accuracy...... 48 4.5.3 Summary...... 52 4.6 Conclusion...... 53
5 Chireix PA Design 55 5.1 Design Methodology...... 55 5.2 Simulation Results...... 56 5.3 Realization...... 59
6 Characterization 61 6.1 Measurement Setup...... 61 6.1.1 Manual Configuration...... 61 6.1.2 Digital Configuration...... 62 6.1.3 Calibration...... 63 6.1.4 LO Leakage...... 65 6.2 Characterization using Static Measurements...... 66 6.2.1 Outphasing Measurements...... 66 6.2.2 Low Power Measurements...... 68 6.3 Real-Time Dynamic Measurement Results...... 68
7 Outlook & Summary 71 7.1 Future Work...... 71 7.1.1 Source Second-Harmonic Termination...... 71 7.1.2 Architecture Load-Pull...... 72 7.1.3 Miscellaneous...... 74 7.2 Summary...... 76 7.3 Zusammenfassung...... 77
A Transmission Line Equations 81
B Some Probabilistic Notions 83
ii Contents
C Proof of the DC & Fundamental Component Expressions of the Nonlinear Output Capacitance 85
D Code Samples 87
Abbreviations 104
List of Figures 105
List of Tables 109
Bibliography 111
Authored and Co-Authored Publications 119
Patent Submission 119
iii iv Chapter 1 Introduction
“...Having the forecasted traffic growth in mind, reducing the network energy consumption must be a major objective for the next decade.” — Nokia Technology Vision 2020 White Paper
With the existing communications throughput continuously being drifted towards higher data rates (Fig. 1.1 and 1.2), bandwidth has become a scarce resource [1]. For physical considerations linked to the transmission properties of an operating frequency, mobile broadband was found to be best suited roughly for the 450 MHz to 5400 MHz range [2]. This frequency limitation has urged communications researchers and engineers to come up with ingenious methods in order to cope with the seemingly ever increasing demand for an already occupied spectrum. Efforts have resulted in the emergence of what is called spectrum efficient modulation techniques. Most engineering novelties come at the expense of resolving the accompanied challenges they create during the course of their development, and next generation communication systems is no exception. These complex modulation techniques such as multiquadrature amplitude modulation (MQAM) heavily exploit the signal’s variation in amplitude. While this allows to use the spectrum more efficiently (given the same bandwidth, transceive significantly higher data rates than feasible with older techniques), it comes at the hurdle of increased signal dynamics. As the efficiency of a conventional PA degrades severely with increasing signal excursions, the work on both single transistor PA classes [3] and PA architecture concepts [4] alleviating this problem has been placed on track long time ago. Among several candidates, the outphasing architecture targets the objective of transmitting high peak to average power ratio (PAR) signals with high efficiency performance [5].
1.1 Background
Originally a differential architecture, Chireix’s outphasing PA was proposed in the begin- nings of the 1930’s as a high efficiency solution [7,8]. Throughout early 1970’s, it was
1 1 Introduction
Figure 1.1: Global mobile data [6].
Figure 1.2: High-end devices multiply traffic [6]. employed in RCA’s ampliphase AM-broadcast transmitters [4,9]. In that last decade, it came into light at microwave frequencies under the acronym LINC (linear amplifica- tion using nonlinear components) [10, 11]. Later on, a single ended implementation of it was suggested and theoretically analyzed in [12]. Despite their high expectations, the presented analyses were described to be difficult to follow in the microwave community, and that their materialization remained scarce and unclear [13]. In this context, it can be said that the analysis in [12] constituted a theoretical upper limit benchmark for how far any practical realization of the Chireix PA using class-B devices can reach. In fact, the original Chireix analysis was focused at vacuum tube PAs as the working horses for amplifying the two outphased signals [8]. This work investigates the suitability of the outphasing PA architecture for use in next generation base transceiver stations (BTSs). A multitude of outphasing variants are analyzed and compared. Based on that, a prac- tical study of the most prominent variant is presented. It deals with the considerations required for the design of a Chireix PA using state-of-the-art solid-state technology. At its heart, the study seeks for a better understanding of the importance of the harmonic terminations in the Chireix combiner. The work culminates in a design methodology for reproducible transistor-based Chireix PA designs. In addition, the work sheds the light on a new alternative implementation applicable in specific cases. Throughout this process,
2 1.2 Structure of the Work it is attempted to cover all analytical, numerical, simulation and measurements aspects of the topic.
1.2 Structure of the Work
Starting from the fundamentals, Chapter2 provides a generalized analysis of the Chireix architecture.
In Chapter3 , a study and comparison of modern emerging outphasing variants is reported.
The outphasing analysis is expanded in Chapter4 to consider several practical as- pects. Besides technology, power abilities and bandwidth considerations, the Chap- ter encompasses the effects of the presence of the nonlinear output capacitance of the transistors and the critical consequences on Chireix PA design.
A design technique is subsequently proposed in Chapter5 and a Chireix PA design is enclosed.
The test setup dedicated for outphasing measurements is described in Chapter6 . The characterization of the manufactured Chireix PA and measurement results are presented.
Chapter7 wraps-up with some recommendations and suggestions before conclud- ing the study.
3 4 Chapter 2
Outphasing Architecture Analysis
“The variable load is then obtained by acting on the phase difference between the grid excitations of the two parts of the final amplifier, whence the name of “outphasing” modulation given to the system.” — Henry Chireix, High Power Outphasing Modulation
The outphasing topology consists of a signal component separator (SCS) that splits the generally amplitude modulated (AM) and phase modulated (PM) signal into two PM signals such that their sum is equivalent to the original signal1. Since the resulting signals are only PM, the outphasing concept suggests then the usage of two efficient nonlinear amplifiers to perform amplification just before the final step of signal summation, thus allowing to recapture ideally an amplified replica of the input. A basic depiction of the concept is shown in Fig. 2.1. For high power BTS applications, the power delivered by the SCS needs to be amplified by predrivers (P1 and P2) and drivers (D1 and D2) before reaching the final stage outphasing PAs. When it comes to the combiner’s implemen- tation, two families are to be distinguished: the matched (lossy but isolating) combiner family and the lossless one (but not matched, not isolating). In this Chapter, deriva- tions of the primitive two implementations using Wilkinson and Chireix combiners are presented. First the Wilkinson case is considered. Since they share much of the mathe- matics, the Chireix combiner case is subsequently presented building upon the former’s derivation. Unlike the original derivations [8, 12], the following is generalized to account for the asymmetric signals case. This turns out to be useful when considering more so- phisticated implementations in Chapter3. As a starting point, the basic outphasing idea is introduced.
1The SCS realization is discussed in detail in Chapter6. Here it is shown that the Outphasing archi- tecture accepts analog as well as digital signals, e.g. with switched-mode PAs.
5 2 Outphasing Architecture Analysis
Figure 2.1: Outphasing PA architecture.
2.1 Fundamentals
An AM and PM signal to be amplified has the general form:
sptq rptq ¤ sinpωt φptqq (2.1)
Denoting max(rptq) by 2r0, sptq can be rewritten as rptq sptq 2r0 ¤ ¤ sinpωt φptqq 2r0 ¤ cospθptqq ¤ sinpωt φptqq (2.2) 2r0 where accordingly, ¢ rptq θptq arccos (2.3) 2r0 Thus, sptq can be split using trigonometric identities into
sptq r0 ¤ sinpωt φptq θptqq r0 ¤ sinpωt φptq ¡ θptqq
s1ptq s2ptq (2.4) where
s1ptq r0 ¤ sinpωt φptq θptqq (2.5a)
s2ptq r0 ¤ sinpωt φptq ¡ θptqq (2.5b)
The resulting two only PM signals can now be amplified separately by two PAs biased in a nonlinear mode with an equivalent voltage gain G and combined, resulting in an efficiently amplified version of the original AM-PM signal:
G ¤ s1ptq G ¤ s2ptq G ¤ ps1ptq s2ptqq G ¤ sptq (2.6)
6 2.2 Outphasing with Wilkinson Combiner
Denoting by v1ptq and v2ptq the amplified signals G ¤ s1ptq and G ¤ s2ptq, omitting the term φptq and rewriting θptq as θ for simplicity results without loss of generality in the following output, i.e. amplified, signals
v1ptq V0 ¤ sinpωt θq (2.7a)
v2ptq V0 ¤ sinpωt ¡ θq (2.7b)
where V0 G ¤ r0. Momentarily omitting φptq is justified by noticing that reincorporating it in each of the individual signals allows restoring the amplified signal’s phase since the latter can be written as
vptq v1ptq v2ptq V ¤ sinpωt θq V ¤ sinpωt ¡ θq 0 ¢ 0 ¢ ωt θ ωt ¡ θ ωt θ ¡ ωt θ 2V ¤ sin ¤ cos 0 2 2
2V0 ¤ cospθq ¤ sinpωtq (2.8)
2.2 Outphasing with Wilkinson Combiner
In this Section, the analysis of the outphasing architecture with the classical Wilkinson isolating combiner is carried out. Some useful mathematical and transmission line (TL) notions can be found in appendixA. The topology of this architecture is depicted in Fig. 2.2. Accounting for a generalized outphasing action, the output voltages have the form
PA1 Input signal SCS
PA2
Figure 2.2: Outphasing with Wilkinson combiner.
7 2 Outphasing Architecture Analysis
λ π v p¡ , tq V ¤ sinpωt θ q V ¤ cospωt θ ¡ q (2.9a) 1 4 1 1 1 1 2 λ π v p¡ , tq V ¤ sinpωt ¡ θ q V ¤ cospωt ¡ θ ¡ q (2.9b) 2 4 2 2 2 2 2
2.2.1 Load Voltage
Using A.2a, the following identity can be written
r p q ¤ ¡jβz ¡ ¤ jβz ¤ p ¡jβz jβzq Vi z Vi e Vi e Vi e Γie (2.10)
r th where Vipzq denotes the phasor voltage at a given location z on the i transmission line ¡ with a forward and backward wave amplitudes (Vi ,Vi ) and a reflection coefficient Γi ¡ λ (Fig. 2.2). Applying (2.10) at z 4 results in λ Vr p¡ q jV ¤ p1 ¡ Γ q (2.11a) 1 4 1 1 λ Vr p¡ q jV ¤ p1 ¡ Γ q (2.11b) 2 4 2 2 Simultaneously, (2.9a) and (2.9b) can be translated into the phasor forms
r λ jp¡ π θ q π V p¡ q V ¤ e 2 1 V =p¡ θ q (2.12a) 1 4 1 1 2 1 r λ jp¡ π ¡θ q π V p¡ q V ¤ e 2 2 V =p¡ ¡ θ q (2.12b) 2 4 2 2 2 2 Therefore using the last 4 equations, the following ratio can be obtained
V ¤ p1 ¡ Γ q V 1 1 1 =pθ θ q (2.13) ¤ p ¡ q 1 2 V2 1 Γ2 V2 Similarly at z 0,
r p q ¤ p q V1 0 V1 1 Γ1 (2.14a) r p q ¤ p q V2 0 V2 1 Γ2 (2.14b) r r V1p0q VL (2.14c) r r V2p0q VL (2.14d) and therefore V ¤ p1 Γ q 1 1 1 (2.15) ¤ p q V2 1 Γ2 Using (2.13) and (2.15), the following can be written
1 ¡ Γ1 1 Γ2 V1 ¤ =pθ1 θ2q (2.16) 1 Γ1 1 ¡ Γ2 V2
8 2.2 Outphasing with Wilkinson Combiner
Replacing Γ1,2 by their form A.3 results in ¡ ¡ 1 ¡ ZL1 Z0 1 ZL2 Z0 ZL1 Z0 ZL2 Z0 V1 ¤ =pθ1 θ2q (2.17) Z ¡Z0 Z ¡Z0 1 L1 1 ¡ L2 V2 ZL1 Z0 ZL2 Z0 Simplifying gives the following impedances ratio
ZL2 V1 =pθ1 θ2q (2.18) ZL1 V2 r r r r r r On the other hand, since IL I1p0q I2p0q, and all of VL, V1p0q and V2p0q are equal ñ Vr Vr p0q Vr p0q Vr Vr L 1 2 L L (2.19) ZL ZL1 ZL2 ZL1 ZL2
This means effectively that the parallel combination of ZL1 and ZL2 is equivalent to ZL and therefore
ZL2 ¤ ZL ZL1 (2.20a) ZL2 ¡ ZL ZL1 ¤ ZL ZL2 (2.20b) ZL1 ¡ ZL Substituting this in (2.18) and solving for the impedances results in
V2 ZL1 ZL ¤ p1 =p¡θ1 ¡ θ2qq (2.21a) V1 V1 ZL2 ZL ¤ p1 =pθ1 θ2qq (2.21b) V2 From (2.11a) and (2.12a) =p q V1 θ1 V1 (2.22) Γ1 ¡ 1
Substituting this in (2.14a) then employing the obtained expression of the impedance ZL1 in (2.21a) enables to write
r Γ1 1 VL V1=pθ1q ¤ Γ1 ¡ 1 ZL1 ¡ ¤ V1=pθ1q Z0 ZL V2 ¡ ¤ p1 =p¡θ1 ¡ θ2qq ¤ V1=pθ1q Z0 V1 ZL ¡ ¤ pV1=pθ1q V2=p¡θ2qq (2.23) Z0 Finally, the output or load voltage expression as a function of time can be written as
ZL π ZL π vLptq ¤ V1 ¤ sinpωt θ1 ¡ q ¤ V2 ¤ sinpωt ¡ θ2 ¡ q Z0 2 Z0 2 ZL π ¤ V3 ¤ sinpωt θ3 ¡ q (2.24) Z0 2
9 2 Outphasing Architecture Analysis where
2 p ¤ ¤ q2 p ¤ ¡ ¤ q2 V3 V1 cos θ1 V2 cos θ2 V1 sin θ1 V2 sin θ2 V 2 V 2 2V ¤ V ¤ cospθ θ q (2.25a) 1 ¢2 1 2 1 2 V1 ¤ sin θ1 ¡ V2 ¤ sin θ2 θ3 arctan (2.25b) V1 ¤ cos θ1 V2 ¤ cos θ2
For the symmetric case where V1 V2 V0 and θ1 θ2 θ, this simplifies to
ZL1 ZL ¤ p1 =p¡2θqq (2.26a)
ZL2 ZL ¤ p1 =p2θqq (2.26b) ñ ZL π vLptq 2 ¤ V0 ¤ cospθq ¤ sinpωt ¡ q (2.27) Z0 2 λ The obtained expression is analogous to (2.8) with the delay being caused by the 4 lines.
2.2.2 Power and Efficiency Calculations
The isolation current traversing the isolation resistor 2ZL has the phasor form r p¡ λ q ¡ r p¡ λ q r V1 4 V2 4 Iiso (2.28) 2ZL
For ZL real, the power dissipated in the isolation resistor and the power delivered to the load have the respective expressions "¢ * 1 λ λ P < Vr p¡ q ¡ Vr p¡ q ¤ Ir¦ diss 2 1 4 2 4 iso V 2 V 2 ¡ 2V ¤ V ¤ cospθ θ q 1 2 1 2 1 2 (2.29) 4Z ! ) L § § 1 1 § §2 Z r ¤ r¦ ¤ §r § L ¤ 2 PL < VL IL VL 2 V3 (2.30) 2 2ZL 2Z0 ? For Z0 2ZL 2 2 ¤ ¤ p q V1 V2 2V1 V2 cos θ1 θ2 PL (2.31) 4ZL The generalized Wilkinson combiner’s efficiency is therefore
P 1 V 2 V 2 2V ¤ V ¤ cospθ θ q η L ¤ 1 2 1 2 1 2 (2.32) 2 2 PL Pdiss 2 V1 V2
If V1 V2 V0 and θ1 θ2 θ, the efficiency reduces to the common expression
2 ηsym cos θ (2.33)
10 2.2 Outphasing with Wilkinson Combiner
To verify the validity of (2.32), the output and input voltages and currents of the circuit shown in Fig. 2.3 are simulated for V2 ranging between 0 V and 50 V, while arbitrarily ¥ ¥ setting the other parameters to V1 50 V, θ1 70 and θ2 30 .
P I v1 VtSine I_Probe SRC1 I_Probe1 P_Probe MLIN Amplitude=V1 Pout1 R TL1 Phase=Theta1 Risolation P Vload R=100 Ohm I I_Probe R P_Probe Iout Pout Rload R=50 Ohm P I v2 VtSine I_Probe SRC2 I_Probe2 P_Probe MLIN Amplitude=V2 Pout2 TL2 Phase=-Theta2
Figure 2.3: Efficiency assessment circuit schematic.
The simulated efficiency is then calculated as
Pout ηsim (2.34) Pout1 Pout2 (2.32) is evaluated for the same parameter values, as well as the Wilkinson’s efficiency expression presented in [14]. The simulated curve plotted in Fig. 2.4 confirms the derived analytical efficiency expression. The earlier form encountered in literature presents an incomplete description of the ideal Wilkinson’s combiner efficiency, where it is limited to 2 selections of V1, V2, θ1 and θ2 such that θ3 is an arbitrary constant .
50 45 40 35 30 (%)
η 25 20
15 Simulated (2.34) 10 Analytical (2.32) Analytical [14] 5 0 5 10 15 20 25 30 35 40 45 50 V2 (V)
¥ ¥ Figure 2.4: Wilkinson’s η assessment: V1 50 V, θ1 70 and θ2 30 .
2 ¥ If 0 V1,2 and 0 ¤ θ1,2 ¤ π{2 then θ3 shall be 0 for outphasing amplifier applications.
11 2 Outphasing Architecture Analysis
2.2.3 Amplifier Loads
From (A.2b),
r λ V1 IL1p¡ q j ¤ p1 Γ1q (2.35) 4 Z0
Substituting V1 by its form in (2.22) and solving results in
r λ j IL1p¡ q ¡ ¤ rV1=pθ1q V2=p¡θ2qs (2.36) 4 2ZL Similarly r λ j IL2p¡ q ¡ ¤ rV1=pθ1q V2=p¡θ2qs (2.37) 4 2ZL
r p¡ λ q ¡ r p¡ λ q =p¡ π q ¡ =p¡ π ¡ q r V1 4 V2 4 V1 2 θ1 V2 2 θ2 Iiso 2ZL 2ZL j ¡ ¤ rV1=pθ1q ¡ V2=p¡θ2qs (2.38) 2ZL The currents generated by the PAs are therefore
r r λ r j I1 IL1p¡ q Iiso ¡ ¤ V1=pθ1q (2.39a) 4 ZL r r λ r j I2 IL2p¡ q ¡ Iiso ¡ ¤ V2=p¡θ2q (2.39b) 4 ZL The impedances seen by each amplifier are respectively
Vr p¡ λ q 1 4 Z1 r (2.40a) I1 Vr p¡ λ q 2 4 Z2 r (2.40b) I2 Using (2.12a) and (2.39a), this translates into
V =p¡ π θ q ¡jV =pθ q 1 2 1 1 1 Z1 j j ZL (2.41) ¡ ¤ V1=pθ1q ¡ ¤ V1=pθ1q ZL ZL
Similarly Z2 ZL ñ
Z1 Z2 ZL (2.42) This means that the loads seen by each amplifier are constants no matter what the other variables are. Employing a Wilkinson combiner signifies that no load modulation is occurring. This is an integral difference to the Chireix combiner case which is analyzed in the next Section.
12 2.3 Outphasing with Chireix Combiner
2.3 Outphasing with Chireix Combiner
A first step toward an RF realization of the Chireix combiner would be to omit the isolating resistance of the Wilkinson combiner (Fig. 2.2). The resulting impedances that the PA devices see then become
r λ V p¡ q Z2 Z 1 4 0 (2.43a) 1 r λ p¡ q ZL1 IL1 4 r λ V p¡ q Z2 Z 2 4 0 (2.43b) 2 r λ p¡ q ZL2 IL2 4 ? For Z0 2ZL and considering the symmetric case using (2.26a) and (2.26b), the impedances can be written as 2Z Z L Z ¤ p1 j tanpθqq (2.44a) 1 p1 =p¡2θqq L 2Z Z L Z ¤ p1 ¡ j tanpθqq (2.44b) 2 p1 =p 2θqq L The admittances follow then as 1 p1 =p¡2θqq Y1 (2.45a) Z1 2ZL 1 p1 =p 2θqq Y2 (2.45b) Z2 2ZL ñ 1 cosp2θq sinp2θq Y1 ¡ j (2.46a) 2ZL 2ZL 1 cosp2θq sinp2θq Y2 j (2.46b) 2ZL 2ZL
For Yi Gi jBi, the conductances and susceptances are 1 cosp2θq G1 (2.47a) 2ZL sinp2θq B1 ¡ (2.47b) 2ZL 1 cosp2θq G2 (2.47c) 2ZL sinp2θq B2 (2.47d) 2ZL The described configuration might be named the uncompensated Chireix combiner. Be- sides performing outphasing on the excitation sources, Chireix’s consequent idea is that
13 2 Outphasing Architecture Analysis
by compensating the susceptances at a specific angle θc, the impedances seen by the PA devices are set to exhibit only a real part. In power engineering, this is known as reactive power control. Together with the usage of PAs in their nonlinear regime, this would bring overall efficiency benefits as shown in the following.
2.3.1 Chireix Analysis with Ideal Class-B PAs
The analysis so far has required that the voltage excitations (2.9a) and (2.9b) be sinusoidal with no further conditions. Therefore in this ideal case, the voltages should be free of harmonic content. This can be approached by assuming that all harmonics are terminated with a short circuit. From this perspective, the pure class-B PA constitutes an ideal candidate for the PA blocks of the outphasing architecture. Besides its sinusoidal output voltage waveform, its uncompromised power for efficiency over class-A PA [13] makes it ultimately suitable for the outphasing architecture. One could as well consider the use of class-C PA seeking higher efficiency, however this is expected to occur at the expense of available output power as the class-C PA’s power continuously decreases below class-A’s power with the conduction angle decreasing below π [13]. The magnitude of the fundamental component of class-B PA’s output current in relation to the consumed current IDC can be found by applying the Fourier series decomposition to the output current waveform. From [12]: § § 2 § § I ¤ §Ir § (2.48) DC π fund Simultaneously, the fundamental output currents can be written as: λ Ir Y ¤ Vr p¡ q (2.49a) 1 1 1 4 λ Ir Y ¤ Vr p¡ q (2.49b) 2 2 2 4 Therefore by noticing that (2.46a) and (2.46b§ ) assume§ a§ complex§ conjugate relationship § § § § ¦ §r p¡ λ q§ §r p¡ λ q§ (Y1 Y2 ) and that for the symmetric case V1 4 V2 4 V0, the consumption currents can be expressed as: 2 I I ¤ V ¤ |Y | (2.50) DC1 DC2 π 0 i Assuming a full-swing all-time positive output voltage waveform for the class-B blocks, their DC voltage should be equal to V0. The combined DC power consumption is hence: 4 P 2V ¤ I ¤ V 2 ¤ |Y | (2.51) DC 0 DCi π 0 i Adapting (2.31) to the symmetric case results in:
2 V0 2 PL ¤ cos pθq (2.52) ZL
14 2.3 Outphasing with Chireix Combiner
The efficiency of an outphasing amplifier employing an uncompensated Chireix combiner and ideal class-B blocks is therefore:
P π cos2 θ η L ¤ (2.53) PDC 4 ZL ¤ |Yi|
A direct observation for improving the efficiency is trying to diminish the magnitude |Yi|. The second step toward the Chireix combiner therefore is to add shunt jX and ¡jX elements compensating respectively the susceptances (2.47b) and (2.47d) at a specific outphasing angle θc so that sinp2θ q X c (2.54) 2ZL
The resulting topology is depicted in Fig. 2.5. To calculate the resulting new Yi ad-
Figure 2.5: Outphasing with Chireix combiner. mittances, it is sufficient to add the terms jX and ¡jX to respectively (2.46a) and (2.46b); as long as the voltage excitation sources are symmetrically sinusoidal, introduc- ing shunt admittances is valid and is not expected to perturb the analysis. Therefore the admittances become
1 cosp2θq sinp2θq sinp2θcq Y1 ¡ j j (2.55a) 2ZL 2ZL 2ZL 1 cosp2θq sinp2θq sinp2θcq Y2 j ¡ j (2.55b) 2ZL 2ZL 2ZL Fig. 2.6 shows on the Smith-chart the impedances of the uncompensated Chireix combiner (2.44) along with the impedances of the compensated Chireix combiner (reciprocal of 2.55) ¥ with an illustrative compensation angle θc 15 . As inferred by the equations, the real part in the uncompensated case is constant. Although the combiner itself is lossless, this hints to an overall continuous degradation of efficiency as the operation point moves
15 2 Outphasing Architecture Analysis away from desirable load values while θ and subsequently the delivered power is being modulated. In a striking difference to that and to the Wilkinson combiner case (2.42), the real parts of the compensated Chireix impedances3 do vary as θ is being modulated.
Recalling that θ’s modulation is implied by the input signal’s magnitude (2.3), both the
9 9
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20 20
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.2 1.4 1.6 1.8 2.0 3.0 4.0 5.0 10 20 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.2 1.4 1.6 1.8 2.0 3.0 4.0 5.0 10 20
0 0 -2 -2
Gamma2U Gamma1U 1 Gamma2C Gamma1C 1 0 . 0 . 1 0 1 - - - -0
0 2 0 2
.
. . . 5 0 5 0 - - - -
0 0
4. 4. - -
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-0. -0.
0 0
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0 9 . 0 9
. .
1 - 1 -
- 0 - 0
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Theta (0.000 to 89.000) Theta (0.000 to 89.000)
Figure 2.6: Uncompensated (left) vs. compensated Chireix combiner impedances loci. real and imaginary parts of the admittances (2.55) and their corresponding impedances are in fact being indirectly modulated by the input signal’s magnitude rptq. This is a pivotal point for the Chireix PA as it means that the device’s load is modulated for each input power level and consequently for each output power level. That load modulation behavior is what exactly classifies the Chireix PA as a typical load modulated PA architecture. The
impedance loci dependence on the design parameter θc and on ZL is shown in Fig. 2.7.
9 9
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8
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0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.2 1.4 1.6 1.8 2.0 3.0 4.0 5.0 10 20 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.2 1.4 1.6 1.8 2.0 3.0 4.0 5.0 10 20
0 0 2 2 - - Gamma2 Gamma1
Gamma2 Gamma1 1 1 0 . 0 . -1 -0 -1 -0
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1
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Theta (0.000 to 89.000) Theta (0.000 to 89.000)
Figure 2.7: Impedance loci sets for different θc and ZL settings. The arrows indicate ¥ ¥ orientations of increasing (left) θc and (right) ZL, respectively from 10 to 30 ¥ ¥ in 5 steps for ZL 50 Ω, and from 10 Ω to 50 Ω in 10 Ω steps for θc 15 .
3Recall that the real part of a complex impedance is not equal to the reciprocal of the real part of its equivalent admittance.
16 2.3 Outphasing with Chireix Combiner
As suggested by (2.52), the power back-off (PBO) level can be written as the following function of θ ¢ maxpP q PBO 10 log L 20 logpcospθqq (2.56) PL The real and imaginary parts of the compensated Chireix impedances can now be replotted as a function of the PBO. The load modulation behaviour of the Chireix PA can hence ¦ be clearly seen in Fig. 2.8 and 2.9, where only Z1 has been shown since Z1 Z2 .
2000 1000 θ =10 ◦ c ◦ θc =15 θ ◦ c =20 ◦ θc =25 500 1500 θ ◦ c =30 ) ) Ω Ω ( (
} 0 } 1 1
1000 Z Z { { −500
real ◦ imag θ =10 500 c ◦ θ =15 −1000 c ◦ θc =20 θ =25 ◦ c ◦ θc =30 0 −1500 −30 −27 −24 −21 −18 −15 −12 −9 −6 −3 0 −30 −27 −24 −21 −18 −15 −12 −9 −6 −3 0 PBO (dB) PBO (dB) (a) (b)
Figure 2.8: Modulated (a) real and (b) imaginary parts of the compensated Chireix
impedance Z1 for different compensation angle settings; ZL 50 Ω.
800 200 Z Ω L =10 Z Ω L =20 Z Ω L =30 Z =40 Ω
600 L ) 0 ) Z =50 Ω L Ω Ω ( ( } } 1 1
400 Z −200 Z { {
Z =10 Ω real L imag Z Ω L =20 200 −400 Z Ω L =30 Z Ω L =40 Z Ω L =50 0 −600 −30 −27 −24 −21 −18 −15 −12 −9 −6 −3 0 −30 −27 −24 −21 −18 −15 −12 −9 −6 −3 0 PBO (dB) PBO (dB)
(a) (b)
Figure 2.9: Modulated (a) real and (b) imaginary parts of the compensated Chireix ¥ impedance Z1 for different ZL settings; θc 15 .
The incorporation of compensation elements into the combiner does not only compensate the susceptances and consequently boosts the power factor, but remarkably results in a modulation of the real part instead of a constant one in (2.44). It can be noted that the real part peaks at a PBO that is related to θc. The relationship can be found by determining the real part of the reciprocal of (2.55). On the other hand, the imaginary π ¡ part nulls two times, one corresponding to θ θc and the other one to θ 2 θc.
17 2 Outphasing Architecture Analysis
The ideal class-B Chireix efficiency expressed in (2.53), can now be reevaluated for the compensated Chireix combiner as
π cos2 θ η ¤ (2.57) 2 |1 cosp2θq © j sinp2θq ¨ j sinp2θcq|
¥ and plotted as shown in Fig. (2.10) for an arbitrarily selected θc 15 compensation. The efficiency advantage can be noticed by comparison with the outphasing efficiency of the uncompensated case and when employing a Wilkinson combiner (2.33). Due to
Figure 2.10: Outphasing efficiencies assuming ideal class-B PA blocks. the nature of the function (2.57), two efficiency peaks emerge for the Chireix curve, one π ¡ located at θ θc and the other at θ 2 θc. If PBOHD and PBOLD designate how deep respectively the high drive and low drive peaks fall in PBO, and ∆ their distance in dB, then
PBOHD 20 logpcospθcqq (2.58a)
PBOLD 20 logpcosp90 ¡ θcqq (2.58b)
∆ PBOHD ¡ PBOLD
20 logpcotpθcqq (2.58c)
At this stage, it should be mentioned that linearity is not questioned with regard to the two PAs’ class of operation since the reconstruction of the amplitude in an outphasing PA is ultimately performed by modulating θ. In the following Chapter, some emerging outphasing variants are considered.
18 Chapter 3 Emerging Outphasing Variants Study
“Methods hitherto employed for reducing power consumption include the high level class B modulation system, such as is used at WLW, and the ingenious method of “outphasing modulation” invented by Chireix and employed in a number of European installations.” — William H. Doherty, A New High Efficiency Power Amplifier for Modulated Waves
In addition to the original concept, several outphasing variants have appeared in the last two decades. These suggested efficiency enhancement techniques can be classified into two outphasing PA families; one employing an isolating combiner where no mutual load modulation is occurring, and the other employing a nonisolating combiner, e.g. the Chireix combiner, with some further external mechanism. In this Chapter, an assessment of a multitude of these variants is reported. After defining a benchmark for the efficiency calculations, a comparison of the discussed variants is presented.
3.1 PA-Engine Analogy
To gain an understanding of the efficiency enhancement techniques applicable for PAs in general, it might be handy to draw an analogy between the PA as a system converting DC to RF energy, and the internal combustion engine converting chemical to mechanical energy. Fig 3.1 shows the fuel consumption of a traditional car. With the x-axis (speed) relating power and the y-axis (mpg) relating efficiency, it can be seen how efficiency is not the same for all output powers. The car performs best in terms of fuel consump- tion around 40 mph (65 km/h). The inevitable need for accelerating and decelerating requires however a system to modulate the engine’s load. Without a gearbox it would be extremely hard to accelerate from a stationary position while the gear ratio is 5 for instance. If it is not going to choke, the car would burn a lot of fuel without barely moving a tiny distance forward. A gearbox allows to present the engine with the “right” load at each operating output power level or output power level interval. Considering now
19 3 Emerging Outphasing Variants Study
Figure 3.1: A 1986 VW Golf GTI fuel consumption [15, 16]. the drain efficiency of any conventional single transistor PA, say class-E PA [17], it can be noted how efficiency steeply drops from a considerably high efficiency figure around 75 % or more as the delivered power level decreases (Fig. 3.2). With the appearance of ever increasing high PAR communication schemes and a continuously overshadowing alert for “green” communications, the need for PA load modulation mechanisms becomes imminent. In this sense, it can be said that the Doherty architecture [18] for example,
80 70 60 50 40 30 20 Drain Efficiency (%) 10 0 25 27 29 31 33 35 37 39 41 43 45 47 Pout (dBm) (a) (b)
Figure 3.2: (a) A realized class-E GaN HEMT (b) measured at 2170 MHz. especially an asymmetric configuration [19], resembles an automobile equipped with a hybrid engine technology where an electric motor would solely be running at low speeds, and the gasoline engine kicking-off at higher speeds being more efficient there, reducing thus the overall energy consumption. Therefore the expression heavy load modulation should not necessarily be bearing negative connotations. In fact, load modulation for any load modulated architecture is a two edged sword depending on the degree of success of a (nonisolating) combiner’s design. A fitting combiner will present the PAs with the “right” loads at the operating output power levels. Otherwise the impedance loci will be located in undesired places on the Smith-chart resulting in low efficiency performance.
20 3.2 A Brief Overview of PA Architectures
3.2 A Brief Overview of PA Architectures
In conjunction with voltage biasing, configurations of usually single amplifying devices, e.g. transistors, are charted according to their respective fundamental and harmonic terminations. While this categorization results in “PA classes” each convenient for certain applications [3], “PA architectures” employ PA classes as their building blocks toward obtaining a further improved dedicated amplification performance. A classification of some PA architectures is presented in Fig. 3.3. These architectures are broadly split into two categories: the one that rely mainly on bias modulation or control to produce output power with high efficiency, and the one that does so by modulating the load. By explicit load modulation, it is meant the category where the load is directly modulated, for instance by action of dynamically controlling varactors in the output matching circuitry. The implicit category on the other hand denotes the architectures where load modulation is taking place due to other artifacts. A famous example is the Doherty architecture [18] where the main amplifier’s load is intended to be carefully modulated by the action of the peaking amplifier, which is in turn modulated by the input signal. On the other hand, the loads of the two constitutive PAs of a Chireix amplifier are modulated by the action of the outphasing angle θ, which is in turn modulated by the input signal too1. From this perspective, some might say that the Chireix and Doherty PAs are two solution points in the same multidimensional optimization field, one acting on the relative phase difference between the split signals and the other on the individual power levels. It remains to
Figure 3.3: A classification of some PA architectures. be mentioned that other hybrid combinations sharing one or more of the traits of the architectures in Fig. 3.3 may as well exist. These include several emerging outphasing variants considered in the following.
1For more details, please refer to Chapter2 (e.g. Fig. 2.8 and 2.9).
21 3 Emerging Outphasing Variants Study
3.3 Variants with an Isolating Combiner
3.3.1 Outphasing with Energy Recovery (Turbo-LINC)
This suggests replacing the isolation resistor for instance of a Wilkinson combiner with a kind of energy harvester that feeds back the otherwise lost as heat energy to the DC supply, such that its input resistor be equal to the isolating resistor (usually 2ZL)[20], [21]. The idea can be compared to turbocharging where the hot exhaust gases strike the blades of a turbine for compressing oxygen-rich air and feeding it back to the combustion chamber (Fig. 3.4). Additional oxygen allows the engine to burn gasoline more completely, generating more performance and therefore improving the engine’s efficiency. A basic circuit illustrating the concept is shown in Fig. 3.5.
Figure 3.4: Turbocharged engine [22].
(a) (b)
Figure 3.5: (a) Outphasing with energy recovery using (b) a bridge rectifier.
In the following, an attempt to benchmark the efficiency capabilities of this proposition
22 3.3 Variants with an Isolating Combiner is presented. The different power quantities can be written as: π P ¤ P ¤ cos2pθq (3.1a) L 4 DC π P ¤ P ¤ p1 ¡ cos2pθqq (3.1b) inH 4 DC
PouH ηH ¤ PinH (3.1c)
PL ηTurbo-LINC (3.1d) PDC ¡ PouH where PinH, PouH and ηH are respectively the input power, output power and efficiency conversion of the harvester circuit. With the harvester made of a rectifier and a DC- DC converter, a realistic form of its conversion efficiency reflecting the fact that the rectifier’s output drops with smaller differential input voltage (i.e. with decreasing θ) can be formulated as: 2 ηH ηDC-DC ¤ ηRectifier ηDC-DC ¤ α ¤ sin pθq (3.2) where α is dependent on the rectifier’s topology and diodes properties. It must be men- tioned that the diodes should be supporting high peak-inverse-voltages on the order of 100 V which constitutes a technological challenge at high power HF applications. The overall efficiency of this variant can hence be approximated by cos2pθq η (3.3) Turbo-LINC 2 2 4{π ¡ α ¤ p1 ¡ cos pθqq ¤ sin pθq ¤ ηDC-DC An upper limit of the efficiency performance of this variant can be found by selecting α and ηDC-DC to emulate the highest possible efficiency of the harvester (α ηDC-DC 1).
PBO (dB) −Inf −15.21 −9.32 −6.02 −3.84 −2.31 −1.25 −0.54 −0.13 0 100 90 80 70 60 Wilkinson−LINC 50 Turbo−LINC 40 Harvester 30
Efficiencies (%) 20 10 0 90 80 70 60 50 40 30 20 10 0 θ (°)
Figure 3.6: Outphasing with energy recovery assuming ideal class-B PA blocks.
Although a tangible improvement over outphasing with the traditional Wilkinson com- biner can be seen (Fig. 3.6) (the limit is about 35 % efficiency at 6 dB PBO), it can be
23 3 Emerging Outphasing Variants Study concluded that this architecture falls short of competing with the original Chireix (Fig. 2.10) and other currently favored architectures.
3.3.2 Asymmetric Multilevel Outphasing (AMO)
Another suggestion is to continuously switch the drain voltages among discrete levels in accordance with the input signal so that the overall average efficiency is maximized [23],
[24]. Recalling the expression of the load voltage for asymmetric operation (2.24), V1 and
V2 do not have to be bound to fixed levels, rather could be made to adapt from a range of n levels (and have subsequently θ1 and θ2 determined) to achieve the highest possible efficiency for each desired output level. The optimization problem for the asymmetric ¦ ¦ 2-level case is therefore finding the two optimum levels Va and Vb that both of V1 and
V2 could take for maximizing the expected efficiency, that is finding S £ #£ £ £ £ + V V ¦ V ¦ V ¦ V ¦ 1 P a a b b S; S ¦ , ¦ , ¦ , ¦ V2 Va Vb Va Vb
It is important that the selection of the free variables V1, V2, θ1 and θ2 does not introduce any phase distortion to the transmission. While these parameters are tailored for high efficiency, their selection should always result in a constant θ3 value (2.24). This could be ensured if made according to the triangle sketch (Fig. 3.7), satisfying thereby
V1 ¤ sin θ1 V2 ¤ sin θ2 (law of sines)
Denoting the maximum desired amplitude value V3 by 2V0, and taking the still unop-
Figure 3.7: Asymmetric Outphasing.
timized Va,b levels such as Va ¤ Vb without loss of generality, implies by looking at the efficiency and output voltage expressions in (2.24) and (2.32), that for maximizing the
24 3.3 Variants with an Isolating Combiner efficiency while still covering the desired output voltage range, the following should be satisfied: Va V0 ¤ Vb. Using (2.25a), the entity to be maximized is
2»V0 1 V 2 η ¤ 3 ¤ ppV q ¤ dV (3.4) avg 2 2 3 3 2 V1 V2 0
Hence, the proper selection of V1 and V2 should be made according to the mapping
V1 Va; V2 Va for 0 V3 ¤ 2Va
V1 Va,b; V2 Vb,a for 2Va V3 ¤ Va Vb
V1 Vb; V2 Vb for Va Vb V3 ¤ 2V0
This produces the following writing
2»Va Va» Vb 2»V0 1 1 1 1 η V 2ppV qdV V 2ppV qdV V 2ppV qdV (3.6) avg 2 3 3 3 2 2 3 3 3 2 3 3 3 2 2Va Va Vb 2Vb 0 2Va Va Vb
For a Rayleigh distributed envelope signal, e.g. one of a W-CDMA signal [25], the proba- bility density function (PDF) of the load voltage’s envelope VL (and therefore of V3) and its cumulative distribution function (CDF) are respectively given by
2 VL ¡ VL ppV q ¤ e 2σ2 (3.7) L σ2 2 ¡ VL 2 P pVLq 1 ¡ e 2σ (3.8)
2 where σ is the statistical mode . With V3 bounded, it is practical to define a statistically significant maximum σ0 value for σ such that P pmaxpV3q, σ0q 1, resulting in σ0 2 ¡ Vb 2 V0. This allows to write the approximation e σ 0 for high PAR W-CDMA signals. Integrating by parts, expanding and approximating results in 2 2 2 2V 2 2 σ 2Va σ ¡ a σ η ¡ 1 ¡ ¤ e σ2 (3.9) avg 2 2 2 2 2Va Va Vb 2Va ñ ¦ ¦ V§b V0. Finding Va is realized by numerically finding the root of the equation B § a ηavg § ¤ π BV 0. Using the relation µ σ 2 linking the mode to the average µ of a a V V b 0 ¦ ¦ Rayleigh distributed signal, the quasianalytical Va and Vb values are plotted and their counterparts obtained from a brute force search (BFS) for the maximum ηavg against the PAR and shown in Fig. 3.8. Adapting the asymmetric 2-level outphasing architecture for
2AppendixB provides relevant statistical notions.
25 3 Emerging Outphasing Variants Study
S * F S S * F S V V V* F V V* F
Figure 3.8: Optimal two levels (V0 50 V).
use with class-B PAs with possible drain voltage levels Va and Vb, the average efficiency with a high PAR W-CDMA signal can be approximated by ¢ 2 2 2 2V 2 2 π σ 2Va σ ¡ a σ η ¤ ¡ 1 ¡ ¤ e σ2 (3.10) 2L-AMO 2 2 2 2 4 2Va Va Vb 2Va The optimized average efficiency of the 2-level AMO PA can hence be plotted against the PAR and compared to the traditional case (Fig. 3.9). Similarly the efficiency of the 2-level symmetric outphasing case is numerically computed and plotted for comparison. The 2-level AMO clearly outperforms the other two cases, conveying the message that a “hardware upgrade” (by adding levels) and a software one on top of it (by allowing asymmetric operation) are both key elements for boosting the efficiency. In order to
40 35 30
25 Asymmetric 2−Level Symmetric 2−Level 20 Wilkinson−LINC 15 10 Average Efficiencies (%) 5 7.5 8 8.5 9 9.5 10 10.5 11 11.5 12 W−CDMA PAR (dB)
Figure 3.9: 2-Level AMO average efficiency assuming ideal class-B PA blocks. further enhance average efficiency, additional voltage levels can be employed [26]. This can lead to improved Adjacent Channel Leakage power Ratio (ACLR) figures too [27].
26 3.4 Variants with a Nonisolating Combiner
3.3.3 Modified Multilevel Variants
Some further variants have been proposed [28, 29, 30] showing simultaneously some im- provements in efficiency and linearity from the outphasing with Wilkinson combiner im- plementation but some limitations when it comes to average efficiency compared to other PA architectures.
3.4 Variants with a Nonisolating Combiner
3.4.1 Adaptive Compensation with Active Elements
In this implementation, the compensation elements jX and ¡jX (Fig. 2.5) are realized with varactors for instance [31] rather than with passive structures or components. With the ability to tune the varactors through a control voltage, a dynamic compensation can be achieved for a range of θc values (2.55) with the motivation to boost efficiency instantaneously. Although good results can be achieved statically (50 % efficiency at 9 dB PBO [31]), no dynamic (real-time) realization have been presented. Furthermore the current varactor technology constitutes an obstacle for realizations supporting the high power levels in BTS applications [32].
3.4.2 Input Amplitude Modulated Outphasing (IAMO)
This technique does not involve any change in the hardware concept of the original Chireix idea, rather the SCS algorithm is exploited in a different manner: besides being outphased, the split signals are allowed to take on several amplitude levels in accordance with achiev- ing the highest efficiency at each desired output [33, 34].
70 60 50 40 30 PAE (%) 20 10 0 30 32 34 36 38 40 42 44 46 48 50 Pout (dBm)
(a) (b)
Figure 3.10: LS simulations showing (a) PAE curves that correspond to different input power levels while having θ swept for each and (b) emerging loci sets.
27 3 Emerging Outphasing Variants Study
With no 2nd harmonic isolation at the output side, simulations using large-signal (LS) models showed that in principle it is possible to reconstruct the PAE curve of the original Chireix concept [34]. This is depicted in Fig. 3.10. The concept is hence awaiting further investigations and hardware realizations3.
3.5 Average Efficiency Calculations
Traditionally in analog wireless systems, the power amplifier’s efficiency at maximum output power was used as a defacto efficiency figure-of-merit [35]. With the emergence of complex modulation schemes with considerable PARs, the focus was shifted toward the efficiency figure at a PBO that corresponds to the PAR in question. While this has lead to a more realistic figure-of-merit, restricting the assessment to this quantity does not properly reflect the system’s capabilities [35, 36]. Taking the signal’s PDF of the intended communication scheme into account allows to calculate the overall average efficiency. In this work, the W-CDMA signal with a PAR of 7.5 dB is selected as a reference signal in establishing a comparison between the different architectures. It has been shown that a W-CDMA signal is characterized by a Rayleigh distributed envelope [25]. The PDF and CDF are respectively given by
2 VL ¡ VL ppV q ¤ e 2σ2 L σ2 2 ¡ VL 2 P pVLq 1 ¡ e 2σ where σ is the signal’s statistical mode. A typical example is shown in Fig. 3.11. With
4 O O 3 O O 2 1
0 −1
Baseband Q (V) −2
−3 O O −4 −4 −2 0 2 4 Baseband I (V) O O Oy h
(a) (b)
Figure 3.11: A 7.5 dB PAR W-CDMA (a) IQ constellation and (b) distribution.
that in mind, this enables a theoretical upper limit efficiency assessment for a given
3An interpretation of the observed behavior is presented in light of Chapter4.
28 3.6 Outphasing Paradox outphasing PA variant prior to its hardware realization. Assuming ideal class-B cores, the obtained results for the discussed outphasing variants are summarized in Table 3.1.
Table 3.1: Outphasing variants comparison with a 7.5 dB PAR W-CDMA signal.
Variant Load Modulation Theoretical max ηavg Wilkinson-LINC no 17.70 % Turbo-LINC no 27.83 % 2L-AMO* no 38.37 % Chireix* yes 59.25 % Adaptive-Outphasing yes 78.54 % IAMO* yes 59.25 % *Design parameters tailored for the intended signal.
3.6 Outphasing Paradox
Arguably, the emergence of these variants can be traced back to the unsuccessful at- tempts in reproducing the very promising efficiency performance of the original Chireix (Fig. 2.10) in practice. It has been observed in [13] that both simulations and experimen- tal results appear to significantly miss the idealized analysis. One factor can be linked to the ambiguity in assimilating the concept: while it is true for realizations using an isolating combiner that operating the PAs in high efficiency mode comes at the cost of efficiency reduction due to the automatic implication of a lossy combiner (e.g. Wilkinson or branchline), stating that the PAs would draw a constant amount of DC power as well when using the Chireix combiner due to the driving signals’ constant envelope [37] is inadequate. This paradox can be resolved by noting that the DC current is actually a function of the Chireix load modulation as given by (2.50). As θ increases (low output power direction), the DC current (2.50) and power (2.51) decrease resulting in the effi- ciency curve shown in the previous Chapter. In fact it was not until very recently that a breakthrough in the realization of the original Chireix PA at simultaneously VHF and moderate power levels has occurred [38, 39, 40]. Next, some practical aspects playing a crucial role toward the physical realization of a Chireix PA are considered.
29 30 Chapter 4 Practical Considerations for Chireix PA Design
“It has to be said that Chireix’s original analysis is difficult to follow, and appears to have left behind a legacy of misunderstanding and misconception in the industry as to exactly what the technique has to offer.” — Steve Cripps, RF Power Amplifiers for Wireless Communications
The original Chireix analysis was focused at vacuum tube PAs (Fig. 4.1) as the working horses for amplifying the two outphased signals [8]. Applying the exact original approach in designing a Chireix PA for modern telecommunication systems using state-of-the-art solid-state technology, without any customization, would result in probable misses.
Glass tube
Anode
Grid Heated cathode Heater
Figure 4.1: Voltage applied to the grid controls plate (anode) current [41].
This Chapter deals with the considerations required for the design of a Chireix PA dedi- cated for BTS applications. First, the employed transistor technology is briefly presented. A discussion on the power capability of the Chireix architecture is reported thereafter, followed by a refined more realistic Chireix analysis accounting for some nonidealities. The Chapter proceeds with bandwidth considerations. The Chapter’s outcomes form the basis for a practical realization of a Chireix PA.
31 4 Practical Considerations for Chireix PA Design
4.1 Technology
Together with advanced PA architectures, employing state-of-the-art transistor technol- ogy are key items for an improved PA performance. GaN devices have been commercially available for more than a decade, but their employment in high power PA telecommuni- cation modules is just starting to lift-off. Some of the GaN key properties along with two other competing PA device materials are summarized in Table 4.1 where the Johnson’s
Table 4.1: Material properties comparison [42, 43].
Si GaAs GaN Unit
Band Gap Energy, Eg 1.1 1.4 3.4 eV
Breakdown Electric Field, Eb 0.3 0.4 3.0 MV{cm Mobility, µ 1300 6000 1500 cm2{V{s 7 7 7 Saturated Velocity, vsat 1.0 ¢ 10 1.3 ¢ 10 2.7 ¢ 10 cm{s Thermal Conductivity, K 1.5 0.5 1.5 W{cm{K ¥ Maximum Temperature, Tmax 300 300 700 C
Relative Permittivity, r 11.9 12.5 9.5 - JFM (normalized to Si’s) 1 1.7 27 - BFM (normalized to Si’s) 1 10 27.2 - and Baliga’s figure-of-merit (JFM [44] and BFM [45]) are respectively derived from E ¤ v JFM b sat (4.1a) 2π ¤ ¤ 3 BFM µ Eg (4.1b)
The high breakdown field of GaN HEMTs allows operation at high drain voltages. This leads to two main contributions concerning PA performance: first, in order to deliver the same power level when compared with other technologies, a higher drain voltage means a lower internal current and therefore less internal losses. Second, the higher drain voltage translates for the same power level into a higher output impedance level, resulting in lower loss matching circuits [42] due to the enhanced proximity to 50 Ω. On the other hand a smaller dielectric constant results in smaller capacitances, leading in turn to higher cutoff frequency. As the cutoff frequency relates to the gain-bandwidth product [46], the result is the ability to support higher bandwidth. Furthermore, the higher saturated velocity results in smaller charge densities for the same current. This means that the area can be reduced [43] leading to further reduction in capacitances. The GaN advantages constituted a motivation to select the GaN HEMT as the building block in this work. The reported Chireix PA and other single track PAs are therefore all GaN based.
32 4.2 Maximum Power Capability
4.2 Maximum Power Capability
Since not only efficiency but the figure watt(s) per currency unit is concerned too, it is important to estimate the maximum achievable power of a Chireix PA using specific transistor devices. The maximum power condition emanating from the delivered power equation of a Chireix PA (2.52) is θ 0 ¥. That equation suggests also that by making
ZL smaller, e.g. using an impedance transformer, the maximum obtainable power can be enhanced accordingly. However that would be applicable to ideal sources only. In practice, the maximum voltage Vmax and current Imax levels a given transistor can withstand do limit its achievable maximum power, and therefore the architecture’s potential. To be able to extract the maximum power from a single device1 at θ 0 ¥ as well, it is desired to have: Imax |Y1,2p0q| (4.2) Vmax Evaluating (2.55) at θ 0 ¥ allows to write § § § p q§ § 1 sin 2θc § Imax § ¨ j § (4.3) ZL 2ZL Vmax
Consequently, the task translates into finding the optimum Chireix load ZL denoted Zopt that maximizes the output power capability. This results in: b 1 Vmax 2 Zopt ¤ ¤ sin p2θcq 4 (4.4) 2 Imax
The maximum achievable power can hence be found by reevaluating (2.52) at θ 0 ¥ for
ZL Zopt: 2 V0 Pmax (4.5) Zopt
Under full-swing operation, while the output bias DC voltage, VDC, is equal to V0, the corresponding rail-to-rail voltage 2VDC should then be equating Vmax. The absolute max- imum power that can be obtained from a Chireix PA employing two transistors with breakdown limits Vmax and Imax can be estimated to be 1 V ¤ I P ¤ a max max (4.6) max 2 2 sin p2θcq 4
As can be seen, the impact of the technology is direct; while higher transistor’s maximum ratings intuitively point out to a higher Chireix PA power ability, the design parameter
θc introduces too a traceable though much less heavier impact on the architecture’s capa- bilities. A more detailed understanding can be gained by considering the classical class-B
1For more on loadline match and conjugate match, the reader is referred to [13].
33 4 Practical Considerations for Chireix PA Design
PA abilities built using a single transistor. The Fourier analysis suggests the following relation between Imax and the magnitude of the fundamental: § § § § I §Ir § max (4.7) fund 2 The obtainable maximum power out of a single device (in an isolated class-B configura- tion) is hence § § §r § §Ifund§ ?V0 ? 1 Pimax ¤ ¤ Vmax ¤ Imax (4.8) 2 2 8 That is in principle what is reflected in load-pull (LP) measurements. By comparing this to (4.6), it can be stated that the Chireix PA using two devices in class-B bias does not exactly possess twice the power capability of a classical class-B PA built out of one of ¥ these same devices. In fact, that’s only valid in the particular case when θc 0 , or in other terms when the Chireix PA degenerates to the uncompensated Chireix case. The following graph shows an exemplary Pmax curve for a class-B Chireix PA out of two GaN devices marketed for the 30 W range with the following ratings at room temperature [47]:
Vmax 84 V and Imax 3 A. Regardless of the power application, the maximum power
63 0 0 62 −0.07 −0.1 61 −0.14 60 −0.21 −0.2
59 −0.28 −0.3 58 −0.36 −0.4 Maximum Power (W) 57 −0.43 Power Degradation (dB)
56 −0.51 Max Power Degradation (dB) −0.5 0 5 10 15 20 25 30 35 40 45 0 5 10 15 20 25 30 35 40 45 ◦ ◦ θc ( ) θc ( )
(a) (b)
Figure 4.2: (a) 2 ¢ 31.5 W Chireix’s maximum power capability vs. the design parameter
θc and (b) the generic defined degradation factor κ. degradation factor κ can be defined as the ratio of a class-B Chireix’s maximum achievable power to what would have been obtained from the same employed two devices, having however each operated as a single class-B PA: ¢ £d Pmax 4 κ 10 log 10 log 2 (4.9) 2Pimax sin p2θcq 4
At its worst case, the “losses” attributed to κ remain below 0.5 dB (Fig. 4.2). Recalling from (2.57) that θc is ideally the only parameter affecting the overall efficiency perfor- mance, low values of κ means that the selection of θc is sustained. Furthermore extreme
34 4.3 Transistor Model
¥ 2 selections of θc nearby 45 that result in the highest κs are not expected . Often, it is desired to keep in practice some margin away from the ratings, for instance due to their temperature dependent nature. One option is therefore to slightly lower V0 while keeping VDC Vmax{2. This measure is useful as well when it is desired to keep the drain voltage above the transistor’s knee voltage Vk. In this case, Zopt is adjusted to b
1 VDC V0 2 Zopt ¤ ¤ sin p2θcq 4 (4.10) 2 Imax and Pmax becomes 2V 2 ¤ I 1 P 0 max ¤ a (4.11) max 2 VDC V0 sin p2θcq 4
3 where κ still holds . Accordingly, a good balance in the selection of VDC and V0 should be made to meet a certain desired power capability. It must be noted that the obtained expressions are only approximations. Nevertheless it was found for instance that (4.4) and (4.10) serve as a very good starting point in the design and optimization of a Chireix PA combiner based on a more sophisticated ADS model4.
4.3 Transistor Model
Modeling of a GaN HEMT can get quiet complex. In fact [48] reports a 22-element small- signal model accounting for the various parasitic elements of the device. This allows to reflect the device physics over wide bias and frequency ranges. A scalable LS model can be consequently constructed from the obtained multibias small-signal model [49, 50]. When it comes to circuit design, indeed the accuracy of such models play a vital role for the success of the design. Furthermore, the load-modulation rich behavior of the Chireix outphasing architecture (Fig. 2.8) necessitates an accurate and reliable transistor model, as classical LP measurements at specific operation points do not constitute at all a suitable design option. While indeed a complex model was employed in circuit simulations, this Section presents a primitive model that paves the way for a realistic understanding of the behavior of the Chireix PA when implemented using transistors rather than tubes. Fig. 4.3 shows a simplified small-signal equivalent circuit model of a packaged HEMT assuming a lossless package. The intrinsic model’s Π topology suggests the application of Y-parameters [51] to characterize its electrical properties. Focusing for now only on the intrinsic part of the packaged HEMT is partly justified by the possibility to compensate
2The compensation angles for the applicable examples studied in Section 3.5 did not surpass 20 ¥. 3 Recall that the optimum load for a class-B PA becomes RB pVDC V0q{pImaxq. 4This is presented in the design Chapter, i.e. Chapter5.
35 4 Practical Considerations for Chireix PA Design
Figure 4.3: Packaged GaN HEMT simplified small-signal equivalent circuit model. reactive parts of the package parasitics since the remaining resistive losses (corresponding resistances not shown) are unavoidable in reality. This helps in reaching the sought-after functional understanding of the Chireix PA operation using transistors. These parameters are [52]: ¢ 2 2 Ri ¤ C ¤ ω C y gs jω ¤ gs C (4.12a) 11 D D gd
y12 ¡jω ¤ Cgd (4.12b) ¡jωτ gm ¤ e y21 ¡ jω ¤ Cgd (4.12c) 1 jRi ¤ Cgs ¤ ω
y22 gd jω ¤ pCds Cgdq (4.12d)
2 ¤ 2 ¤ 2 where D 1 Ri Cgs ω . The equivalent Y-parameters representation is shown in Fig. 4.4 for both conduction and pinch-off conditions (ON and OFF states), where the output capacitance is the equivalent parallel combination of the drain-source and gate-drain capacitances:
Cout Cds Cgd (4.13)
(a) (b)
Figure 4.4: Y representation of the intrinsic HEMT in (a) ON and (b) OFF states.
36 4.4 Practical Chireix Analysis
4.4 Practical Chireix Analysis
The original Chireix analysis encompassed some idealistic assumptions. To be able to closely approach the very promising Chireix efficiency curve (Fig. 2.10) in reality, devia- tions from ideal case that emerge upon the use of solid-state transistors should be carefully considered, and whenever possible minimized. In parallel to the Chireix combiner design, the major points to be considered in that quest are identified as:
Gate bias voltage: The gate bias should be set such that the transistor is ON half the time, resulting in a drain current as much close as possible to a half-sine waveform. Strongly deviating from this bias for instance by operation in class-AB means a departure from the analysis that inherently assumed that, and expectedly a direct hit to efficiency. On the other hand, operating in deep class-C means less power capability.
Package parasitics compensation: Unpackaged transistors are not suitable for high power BTS applications. In order to mimic the ideal Chireix combiner (Fig. 2.5), it is necessary to de-embed the undesired package parasitic elements of a pack- aged transistor (Fig. 4.3) at least on the output side. It must be said that if the transistor is internally prematched, the internal matching should equally be de- embedded. In this regard, employing unmatched transistors is more convenient for the design of a Chireix PA.
Harmonic shorted terminations: The presented analysis in Chapter2 assumed sinusoidal voltage waveforms at the Chireix combiner inputs. This can be ap- proached by short-circuiting the harmonics. In fact, the inclusion of a 2nd harmonic termination at the right reflection angle can account for around 20% increase in the efficiency regardless whether the class is E, C or F [53]. Although about 10% can be gained with a proper 3rd harmonic termination [53], the class-B current waveform’s odd-overtones free content suggests that no short circuits are required for the odd harmonics. This constitutes a significant leverage in the output network design. Additional efficiency can theoretically be gained by properly terminating additional higher order (even) harmonics. In practice, the complexity of the matching networks becomes an issue especially that the obtained reward is minor. It must be noted that the care required for harmonic terminations reenforces the choice of using un- matched transistors. Otherwise an internal prematch transformation could hinder the realization of the optimal harmonic terminations. In the design Chapter, it is seen how the compensation of the package’s output parasitics and the 2nd harmonic short are codesigned.
37 4 Practical Considerations for Chireix PA Design
Output capacitance compensation: In contrast to package parasitics, the out- put capacitance is a nonlinear component (Fig. 4.4). Under large RF drives, which is the dominant regime when operating a Chireix PA, the intrinsic HEMT elements become dependent on the extrinsic voltages and not uniquely on the bias conditions. At the time the Chireix PA was invented, vacuum tubes (triodes, tetrodes...) were the only choice for amplification as the transistor as a device did not appear until more than a decade later. Since the interelectrode capacitances of a specific tube, most significantly the grid to cathode capacitance, are basically solely dependent on its geometrical characteristics [54], the compensation task required at HF was more or less not complicated. Unlike that, the nonlinear nature of the output capacitance of a GaN HEMT introduces a compensation milestone. The task of completely resonating it out and getting closer in shape to the ideal topology (Fig. 2.5) is not straightforward. One could think for instance of some form of dynamic matching by introducing active elements in the output matching path. Unfortunately, this in turn brings other complications5.
In light of that, the ideal Chireix analysis is refined in a basic manner, leading to a better understanding of a transistor-implementation of the Chireix PA. Since the network parameters [51] were developed for analyzing linear systems or nonlinear systems in their linear regime operation, the obtained Y representations cannot be directly applied to the analysis of the Chireix PA. The extrinsic voltage dependence of the intrinsic HEMT elements under large RF drive become even exacerbated by operation in class-B. As the transistor is continuously toggling between ON and OFF states, the concept of a single equivalent circuit Y representation of it would collapse. An alternative option to couple the transistor model into the Chireix architecture is to define harmonic admittances. In fact, the complexity and unfamiliarity of a nonlinear time-variable impedance/admittance is mitigated by applying the Fourier series analysis. This allows to restore a “fixed” admittance albeit relating harmonic components of the output current and voltage. In the following, an expression for the nonlinear capacitance Cout is developed.
4.4.1 Nonlinear Output Capacitance
The equation linking the current ic and voltage vc across a nonlinear Cout is given by d dv dC i pC ¤ v q C ¤ c v ¤ out (4.14) c dt out c out dt c dt where all of the entities ic, vc and Cout vary with time (the ptq is dropped for simplicity). Two essential cases can be distinguished:
5Subsection 3.4.1 briefly described the use of active elements in the combiner.
38 4.4 Practical Chireix Analysis
Chireix combiner with short circuits at the harmonics
This scenario represents the ideal class-B case being adapted to a transistor implementa- tion of the Chireix PA. The higher order harmonic content of the current source cycles through the short circuits, leaving no high order harmonic current content through Cout. The drain voltage higher order harmonic content gets nullified as well. This results in the capacitor voltage and current having the forms:
icptq A ¤ cospω0t Bq (4.15a)
vcptq VDC V0 ¤ sinpω0t θq (4.15b)
With that, a solution to the differential equation (4.14) can now be pursued. The solution can be found to be: A¤sinpω0t Bq Qres ω0 Coutptq (4.16) VDC V0 ¤ sinpω0t θq where Qres is a constant following from integration. The designation of this constant by Qres stems from the form of the capacitance (4.16) where a voltage dimensioned de- nominator implied a charge dimension for the numerator given in Coulomb. Indeed the numerator is the indefinite integral of icptq (4.15a), representing a variable charge across A Cout. For Cout to retain a meaningful positive value, Qres has to be ¡ . Although (4.16) ω0 gives an adequate representation of the output capacitance in real time, it is of higher interest to try to seek for it a frequency domain representation. The complete answer can be found by applying the Fourier transform to (4.16):
ˆ Coutpfq F pCoutptqq (4.17)
Unfortunately, the raw solution for that, although might have a closed-form expression [55], is extremely complex to handle. A simplified approach can hence be investigated with the goal of determining what factors affect the fundamental frequency component of Cout. The first simplification relies on the understanding that the output capacitance A decreases with increasing drain voltage, leading to a Qres " . The second comes by ω0 inspection that θ won’t be affecting the magnitudes in the frequency domain. These together yield the following Cout simplification for further analysis:
Qres Coutptq (4.18) VDC V0 ¤ sinpω0tq Using the obtained expression, an illustrative example reflecting the parameters of a 30 W GaN HEMT (Table 4.2) is shown in Fig. 4.5a. The corresponding more familiar form of the output nonlinear capacitance as a function of the drain or capacitor voltage vc is plotted in Fig. 4.5b. By noting that this function is periodic, the Fourier series ex-
39 4 Practical Considerations for Chireix PA Design
Table 4.2: Parameters reflecting an exemplary 30 W GaN transistor.
f0 T0 Qres VDC V0 2140 MHz 0.4673 ns 4e-11 C 28 V 26 V
T 20 15 (pF) 10 out C 5
0 0 10 20 30 40 50 60 vc (V) (a) (b)
Figure 4.5: Cout stemming from simplified circuit analysis for the harmonically shorted case (a) as a function of time and (b) as a function of variable capacitor (or drain) voltage for the parameters given in Table 4.2.
pansion can be applied, instead of the transform, to determine its fundamental frequency component Fourier coefficients a1 and b1. Additionally a0 is determined. The derivation is summarized in appendixC. It was found that
ˆ Qres CoutpDCq a (4.19a) V 2 ¡ V 2 DC £ 0 § § § § Q V §Cˆ pf q§ 2 res ¤ a DC ¡ 1 (4.19b) out 0 2 ¡ 2 V0 VDC V0
To verify the validity of the obtained expressions, the numerical FFT algorithm is applied to (4.18) in MATLAB. Both results are plotted as a function of the drain’s DC bias VDC
(Fig. 4.6a) and against the fundamental voltage magnitude V0 (Fig. 4.6b). The results in Fig. 4.6b shall not be confused with the understanding of a decreasing Cout versus an increasing drain voltage, since these point out to the DC and fundamental components of the nonlinear output capacitance and not to Coutptq (Fig. 4.5). Having reached that, it can be argued that the presented results are ungeneralized namely A due to the undertaken simplification Qres " . To overcome this uncertainty, an alter- ω0 native complementary path for inspecting the nonlinear output capacitance is presented.
Cout is extracted from the nonlinear LS model of Cree’s CGH27030F GaN HEMT [47] used for the Chireix PA realization. The extraction is based on the method presented in [50].
The result is plotted in Fig. 4.7 as a function of the gate and drain bias voltages vgs and
40 4.4 Practical Chireix Analysis
6 7 DC − Analytical DC − FFT 6 5 f0 − Analytical f0 − FFT 5 4 (pF) (pF) 4 | 3 |
out 3 out ˆ ˆ C C |
2 | 2 DC − Analytical 1 DC − FFT 1 f0 − Analytical f0 − FFT 0 0 25 30 35 40 45 50 55 14 16 18 20 22 24 26 28 V (V) DC V0 (V) (a) (b)
Figure 4.6: Parametric Cout’s DC and fundamental components for the simplified harmon-
ically shorted case (a) with respect to VDC and (b) with respect to V0 with the fixed parameter values as given in Table 4.2.
vds. As can be seen, the output capacitance is also a strong function of the gate voltage.
30
20
(pF) Fitted out 10 Extracted C
0 010 2030 40 −9 −10 5060 −6 −7 −8 70 −3 −4 −5 80 0 −1 −2 v (V) v (V) ds gs
Figure 4.7: Extracted (dotted) and fitted (colored surface) CGH27030F’s Cout.
By comparison to (4.16), it can be speculated that the factor A could be exhibiting some gate voltage dependency. Although the investigation of a simplified Cout can lead to some useful results [56], taking into account the gate bias effect is recommended especially for LS applications where for instance the Chireix PA transistors are biased in class-B and operated in full-swing mode. With that in mind an empirical form of the extracted Cout is pursued. The fitted expression taking into account the cross-coupling between vgs and vds was based on the equation models presented in [57] with minor modifications: ¨ ¨ ¤ p 2 q ¤ ¡ p 2 q p q Cout a 1 tanh bvgs cvgs 1 tanh dvgsvds evds fvds g pF (4.20)
The constants after fitting using MATLAB are summarized in Table 4.3. The surface fit
41 4 Practical Considerations for Chireix PA Design
Table 4.3: Empirical Cout constants in (4.20) for the CGH27030F HEMT.
a b c d e f g 19.205 -0.4246 -0.2876 -0.1014 -0.1815 0.0610 2.0780 is plotted in Fig. 4.7. By applying harmonic inputs in (4.20),
vgsptq VGS Vgs ¤ sinpω0t θq (4.21a)
vdsptq VDS G ¤ Vgs ¤ sinpω0t π θq (4.21b) where VDS and GVgs are respectively equivalent to the previously used VDC and V0 terms, a modulated Cout is obtained. The resulting real-time Cout is plotted in Fig. 4.8a for the intended design values given in Table 4.4 for different V0 settings (that correspond to different drive levels). Its spectral components can be retrieved by applying the FFT algorithm (Fig. 4.8b). The output capacitance values at DC, f0 and 2f0 are plotted in
25 5
20 4
15 (pF) 3 | (pF) ) f (
out 10 2 C out ˆ C | 5 1
0 0 0 0.2 0.4 0.6 0.8 0 2140 4280 6420 8560 10700 t (ns) f (MHz)
(a) (b)
Figure 4.8: (a) Real time fitted Cout for different V0 values and (b) its spectral components.
Table 4.4: Design parameters using the CGH27030F HEMT.
f0 VGS VDC G 2140 MHz -3.8 V 38 V 10
Fig. 4.9 as a function of the parameter V0. It is noted that the higher order components of
Cout are nonzero. Nevertheless for the purpose of compensation in the Chireix combiner, only the fundamental component of Cout is relevant.
Chireix combiner w/o a short circuit at the 2nd harmonic
In this case, a second order harmonic voltage Vds2 appears in vds:
vdsptq VDS G ¤ Vgs ¤ sinpω0t π θq Vds2 ¤ sinp2ω0t γq (4.22)
42 4.4 Practical Chireix Analysis
5 4.5 4 3.5 3 (pF)
| 2.5
out 2 ˆ C | 1.5 1 DC f0 0.5 2f0 0 28 29 30 31 32 33 34 35 36 V0 (V)
Figure 4.9: Cout’s first three spectral components as a function of the parameter V0.
This makes the fundamental component of the nonlinear output capacitance significantly dependent on it (Fig. 4.10).
3.5 3 2.5 (pF) |
) 2 0 f ( 1.5 out ˆ
C 1 | 0.5 0 0 1 2 3 4 5 6 7 8 9 10 Vds2 (V)
Figure 4.10: Cout’s fundamental component for the nonharmonic design case.
4.4.2 Implications on Chireix PA Design
The previous analysis points out that the nonlinear output capacitance component at f0 is not only dependent on the DC bias settings, but also on the magnitudes of the har- monic voltages. The analysis suggests that the output capacitance at the fundamental can uniquely be constant if the voltage magnitudes of the harmonics are constants too. At the fundamental, a constant input drive level and a low drain-to-source resistance helps stabilizing the fundamental voltage magnitude at the output. For the latter, GaN is a
43 4 Practical Considerations for Chireix PA Design suitable choice [42]. As the transistor’s nonlinear behavior in class-B will§ result in§ the § ˆ § generation of even only overtones, a constant and hence “compensatable” §Coutpf0q§ can nd be guaranteed by shorting at least the 2 harmonic in the combiner so that Vds2 0 for all outphasing θ angles. Otherwise leaving it unshorted would result in a floating Vds2 as the outphasing angle varies. Furthermore, the output capacitance value to be compensated is not the one§ obtained§ from small-signal analysis: while Coutp¡3.8 V, 38 Vq 2.17 pF § ˆ § (Fig. 4.7), §Coutpf0q§ hints to a higher value depending on the selected outphasing LS drive level magnitude (Fig. 4.9). It can be noticed that as V0 decreases, i.e. approach- ing small-signal operation, the converging to 2.17 pF DC component will prevail (Fig. 4.9).
On the other hand, it has been observed using GaN HEMTs from SEDI [58] that leaving out the 2nd harmonic termination together with modulating the input drive level allows to reconstruct the original Chireix PAE curve [33, 34]. In light of the discussed§ understanding§ § ˆ § of Cout, this behavior can be interpreted by the following mechanism: as §Coutpf0q§ becomes §a variable§ of the harmonics too, changing the input drive level will result in a compensated § ˆ § §Coutpf0q§ albeit occurring each time at a different outphasing angle θ. If that happens to coincide with the transistor characteristics, the compensation points will form a continuity allowing in principle to digitally recapture the original Chireix PAE curve by selecting the proper drive levels and outphasing angles sets (Fig. 4.11). Furthermore, a remarkable correlation when it comes to the ideal Chireix peaks distance and simulated IAMO ones is noticed (Fig. 4.11 and Table 4.5). It must be said that the implementation of such a variant requires the availability of solid LS models that enable describing the transistor characteristics in vast areas of load impedances and voltages.
70 70 60 60 50 50 40 40 30 30 PAE (%) PAE (%) 20 20 10 10 0 0 30 32 34 36 38 40 42 44 46 48 50 30 32 34 36 38 40 42 44 46 48 50 Pout (dBm) Pout (dBm)
(a) (b)
¥ ¥ Figure 4.11: IAMO PAE LS simulations with (a) θc 15 and (b) θc 30 designs.
44 4.4 Practical Chireix Analysis
Table 4.5: Peaks distances comparison for two different designs.
¥ ¥ Peaks distance comparison θc 15 θc 30 Chireix theoretical (2.58) 11.4 dB 4.8 dB LS IAMO simulations 10.8 dB 4.1 dB
4.4.3 Load Modulation
So far, it has been discussed that a main difference with the original analysis is the presence of the output capacitance. In order to move one step closer to a transistor- based implementation, the Chireix topology is slightly modified to include the output conductance and capacitance of each transistor. As can be noted from (2.55a) and (2.55b), the expression of Yi does not depend on V0. Under the assumption that the voltage is sinusoidal, accounting for the output conductance and capacitance by adding them in parallel can be safely made. This allows to obtain the new admittance expressions instead of rederiving them. Assuming an unpackaged transistor for now, the block to be inserted between the ideal current sources and the Chireix combiner is shown in Fig 4.12a.
(a) (b)
Figure 4.12: (a) Blocks inserted between the Chireix ideal current sources and Chireix combiner and (b) transformed loci at die’s plane.
In order to mimic the original Chireix combiner as much as possible, it is then required to compensate for each of the output capacitances with§ a parallel§ inductance inserted in the § ˆ § combiner such that its admittance is equal to ¡jω §Coutpf0q§. With that, the admittances
45 4 Practical Considerations for Chireix PA Design seen by the transistors can be written as
p q p q p q § § 1 cos 2θ sin 2θ sin 2θc § ˆ § YTR1 ¡ j j ¡ jω §Coutpf0q§ (4.23a) 2ZL 2ZL 2ZL p q p q p q § § 1 cos 2θ sin 2θ sin 2θc § ˆ § YTR2 j ¡ j ¡ jω §Coutpf0q§ (4.23b) 2ZL 2ZL 2ZL
This implies some transformation of the Chireix loci on the Smith-chart from the location seen in Fig. 2.7 to the one depicted in Fig 4.12b.
4.5 Bandwidth Considerations
As the outphasing concept relies on encoding the amplitude modulation into additional phase modulation, some bandwidth expansion is expected after the SCS. This is man- ifested by the arccos function, that is ideally used to generate the outphasing angle θ (2.3), taking the amplitude of the original signal as its independent variable. Indeed, calculations show how the spectrum of a W-CDMA 5 MHz-wide input signal considerably expands after splitting it into two outphasing signals (Fig. 4.13a). This was confirmed by measurements6 as seen in Fig. 4.13b. The obtained outcome has been reenforced by inspecting the spectrum of a 2-Carrier W-CDMA 20 MHz-wide signal (Fig. 4.14). In order to study the impact of the bandwidth expansion on the system requirements, the instantaneous frequency [59, 60] of the individual outphasing signals is first considered.
0 0 S S −5 in −5 1 S S −10 1 −10 2 S −15 2 −15 −20 −20 −25 −25 −30 −30 −35 (dB) −35 −40 −40
PSD (dB/9.4kHz) −45 −45 −50 −50 −55 −55 −60 −60 −60 −40 −20 0 20 40 60 2060 2080 2100 2120 2140 2160 2180 f (MHz) (MHz)
(a) (b)
Figure 4.13: (a) Calculated and (b) measured (normalized) bandwidth expansion of the individual outphased signals from a 5 MHz W-CDMA signal.
6The SCS setup is described in Chapter6.
46 4.5 Bandwidth Considerations
0 0 S −5 in −5 S −10 1 −10 S −15 2 −15 −20 −20 −25 −25 −30 (dB) −30 −35 −35 PSD (dB/9.4kHz) −40 −40 −45 −45 −50 −50 −60 −40 −20 0 20 40 60 2060 2080 2100 2120 2140 2160 2180 f (MHz) (MHz)
(a) (b)
Figure 4.14: (a) Calculated and (b) measured (normalized) bandwidth expansion of the individual outphased signals from a 20 MHz W-CDMA signal.
4.5.1 Instantaneous Frequency
From the expressions in (2.5), the instantaneous frequencies of the outphased signals can be written as 1 d f f ¤ pφptq θptqq (4.24a) 1 0 2π dt 1 d f f ¤ pφptq ¡ θptqq (4.24b) 2 0 2π dt With that, these quantities can be (numerically) calculated for any communication scheme. Applying this to three different 7.5 dB PAR W-CDMA signal configurations with the re- spective original bandwidths (BWs) of 5 MHz, 10 MHz and 20 MHz hints that the indi- vidual outphasing signals will expand significantly in BW each. Fig. 4.15a shows that for the 5 MHz case. By inspection, it is seen that the bandwidth occupied by the instanta- Number of Occurences Number of Occurences
−400 −300 −200 −100 0 100 200 300 400 −15 −10 −5 0 5 10 15 Instantaneous Frequency Shift (MHz) Instantaneous Frequency Shift (MHz)
(a) (b)
Figure 4.15: (a) Instantaneous frequency shift for the individual outphased signals from a 5 MHz W-CDMA signal and (b) its zoomed view.
47 4 Practical Considerations for Chireix PA Design neous frequency is equal to the sampling frequency of the baseband input signal, which amounted in this case to 307.2 MHz. Given that the broadband matching of any load impedance is subject to limitations emanating from the bounded value of the integral in [61], »8 1 ln dω (4.25) |Γpωq| 0 the expansion would translate into a challenging matching problem7. As a consequence, designing the PA cores to cope with the considerable full bandwidth expansion due to outphasing is extremely hard at a center frequency of 2.14 GHz, if not impossible. Taking however a zoomed look at the instantaneous frequency plot (Fig. 4.15b), it can be noted that the bell shaped distribution falls mostly in a much narrower range than the fully expanded one. For the given three signal configurations, the percentage of outphased data contained in a presumably limited frequency range supported by the PA cores is calculated and depicted in Fig. 4.16. It can be seen that 95 % or more of the outphased data in terms of instantaneous frequency occurrences is contained in respectively about 7 MHz, 20 MHz and 60 MHz BW of the outphased signals. Subsequently, the impact of having a restricted BW support from the PA cores can be studied.
I I I D I I I I I
Figure 4.16: Preserved outphased data as a function of the PA cores’ supported BW.
4.5.2 Modulation Accuracy
While the instantaneous frequency gives a statistical idea reflecting the percentage of outphased data in a given BW in terms of frequency occurrences, a more discrete and standardized metric to consider would be the error vector magnitude (EVM). The EVM is employed in many communication standards as a figure-of-merit of the transmitter’s
7The reflection factor can be minimized to a certain limit in a given frequency band.
48 4.5 Bandwidth Considerations modulation accuracy [62, 63, 64, 65], i.e. the fidelity in transmitting a given signal. The EVM can be computed using g f° ¡ © f N p ¡ r q2 p ¡ r q2 e k1 Ik Ik Qk Qk EVMrms ° ¢ 100 (4.26) N p 2 r2q k1 Ik Qk where
th Ik is the in-phase component of the k symbol in the reference signal, th Qk is the quadrature phase component of the k symbol in the reference signal, r th Ik is the in-phase component of the k symbol in the tested/transmitted signal, r th Qk is the quadrature phase component of the k symbol in the tested/transmitted signal, N is the vector length of the reference signal [66]. To check how the EVM gets affected upon BW truncation of the outphased signals, the Gedankenexperiment represented by Fig. 4.17 is performed: an ideal bandpass filter with adjustable BW is equally applied to each of the outphased signals. At different desired checkpoints along the flow of the signals, “EVM-meters” are placed as seen in Fig. 4.17. Two “PAR-meters” are introduced as well. An illustration of a truncated outphased sig- nal in frequency domain that corresponds to the 2-Carrier W-CDMA 20 MHz-wide signal configuration is depicted in Fig. 4.188. By adjusting the bandpass width, the virtual s s s s s s
Figure 4.17: Outphased signals BW truncation virtual test setup. setup allows to evaluate these metrics as a function of the Chireix PA supporting BW.
EVM at the checkpoint s1Filtered (with reference to s1) is plotted in Fig. 4.19. Applying the
95% rule (EVM1 5%) leads to the minimum required BWs of approximately 32 MHz, 75 MHz and 187 MHz for the respective signals, which is significantly more demanding than what was estimated using the instantaneous frequency metric in the previous sub- section. Comparing these to the original BWs of 5 MHz, 10 MHz and 20 MHz, it is found that the expansion factor varies between 6.4 and and 9.4 accordingly.
8Due to the similar properties of the two outphased signals, path 1 is only illustrated.
49 4 Practical Considerations for Chireix PA Design
0 0 S S −10 1 −10 1 S S −20 1Filtered −20 1Filtered −30 −30 −40 −40 −50 −50 −60 −60 −70 −70 PSD (dB/9.4kHz) −80 PSD (dB/9.4kHz) −80 −90 −90 −100 −100 −150−125−100 −75 −50 −25 0 25 50 75 100 125 150 −150−125−100 −75 −50 −25 0 25 50 75 100 125 150 f (MHz) f (MHz)
(a) (b)
Figure 4.18: Example of the outphasing signal corresponding to a 20 MHz 2-Carrier W- CDMA input, truncated in MATLAB to (a) 15 MHz and (b) 100 MHz.
100 05MHz W−CDMA 90 10MHz W−CDMA 80 20MHz W−CDMA 70 60 (%) 1 50 40 EVM 30 20 10 0 0 50 100 150 200 250 300 350 PA Supporting BW (MHz)
Figure 4.19: EVM of s1Filtered with reference to s1 as a function of the bandpass filter’s BW for three W-CDMA input signal configurations.
−3 100 x 10 90 05MHz W−CDMA 5 10MHz W−CDMA 05MHz W−CDMA 80 20MHz W−CDMA 10MHz W−CDMA 70 4 20MHz W−CDMA 60 3 50 40 EVM (%) 2 30 EVM (%) 20 1 10 0 0 0 50 100 150 200 250 300 350 0 5 10 15 20 25 30 35 40 45 50 PA Supporting BW (MHz) PA Supporting BW (MHz)
(a) (b)
Figure 4.20: (a) EVM of sL with reference to s as a function of the bandpass filter’s BW for three W-CDMA input signal configurations and (b) its zoomed view.
That’s considerable, however is it necessary and required for the PA cores to fully support
50 4.5 Bandwidth Considerations
this for a reliable transmission? To answer that, the EVM at the antenna port, i.e. sL relative to s, is examined as a function of the afforded BW and plotted in Fig. 4.20. It can be seen that the transmitted signal almost fully retains the content of the original signal starting from minimal BW support of 5 MHz, 10 MHz and 20 MHz respectively as indicated by the EVM values. To understand why, equation 2.5 is inspected. In fact, the outphased signals can be rewritten as
s1ptq r0 ¤ rsinpωt φptqq ¤ cospθptqq cospωt φptqq ¤ sinpθptqqs (4.27a)
s1ptq r0 ¤ rsinpωt φptqq ¤ cospθptqq ¡ cospωt φptqq ¤ sinpθptqqs (4.27b) ¡ © p q Recalling that θptq arccos r t leads to the following form 2r0
sptq s ptq s ptq (4.28a) 1 2 exp sptq s ptq ¡ s ptq (4.28b) 1 2 exp where
sexpptq r0 ¤ cospωt φptqq ¤ sinpθptqq (4.29)
This confirms the obtained finding from the EVM computations since the original signal is already “buried” in s1ptq and in s2ptq: provided the minimal filtering BWs of 5 MHz, 10 MHz and 20 MHz in the considered examples are not violated, and that the filters are 9 identically applied , the summation s1ptq s2ptq will result in sptq again no matter what the bandpass BW is. Does that imply that filtering is the next step? In fact, the role of
¨sexpptq serves to obtain constant amplitudes s1,2ptq, which is the motivation for achieving high efficiency in the Chireix architecture. Having known that truncating the outphasing signals in frequency domain does not harm the Chireix transmitter’s modulation accuracy, the answer to what extent does it harm the constant amplitude requirement (and subse- quently power efficiency) can be probed by inspecting the PARs of the outphased signals.
The setup in Fig. 4.17 accounts for that. The PAR of s1Filtered is plotted against the afforded BW in Fig. 4.21. It can be interestingly observed that BW supports of 27 MHz, 60 MHz and 118 MHz will have about the same effects on PAR as 206 MHz, 206 MHz and 220 MHz for the respective signals! Fully constant amplitude outphasing signals will re- quire however the “extra-miles” of reaching the sampling frequency of 307.2 MHz in terms of BW support.
9Any unbalance in the filtering could leave measurable effects on the degradation of the transmitted signal’s EVM.
51 4 Practical Considerations for Chireix PA Design
16 05MHz W−CDMA 14 10MHz W−CDMA 20MHz W−CDMA 12 10 (dB)
1 8 6 PAR 4 2 0 0 50 100 150 200 250 300 350 PA Supporting BW (MHz)
Figure 4.21: The PAR for s1Filtered as a function of the bandpass filter BW.
4.5.3 Summary
The BW support requirements for the Chireix PA cores has been investigated. It turns out that a (nonlinear) compromise emerges between how much BW support to dismiss and how much low PAR to retain. Saying for instance that the outphasing architecture can still live some high efficiency expectations with a 2 dB PAR for the outphased signals (instead of an ideal 0 dB PAR) implies about 20 MHz, 42 MHz and 94 MHz required support from the PA cores in terms of BW, something which is affordable around 2.14 GHz. Despite that, it is still suggested that the PAs should preferably offer some wideband performance, especially in the worst case scenario where two or more multicarriers are simultaneously placed on the two extreme sides of the transmit band. In such circumstances, class-J cores [67] could emerge as a good option for the Chireix PA in the future. Nevertheless this would present a double challenge, first being the “classical” class-J challenge to realize the dispersive harmonic terminations over the desired frequency band and second being the ability to preserve these terminations as the outphasing angle is varied or equivalently the load is being modulated. An insight about the difficulty of the latter point can be gained by noting that in a class-B implementation, a harmonic trap offers a way to shield the desired 2nd harmonic termination from the rest of the combiner circuit, albeit strictly speaking at a single frequency point. As it is observed in the next Chapter, for a narrow band regime, the area behind the trap can be effectively designed to get the 2nd harmonic termination’s reflection factor into a desired small “spot” on the Smith-chart when referred to the package plane. In its simplest form, a trap can be implemented using a quarter- wave open-circuit stub. When it comes to a class-J implementation, it becomes evident then that novel trapping structures might be required to provide a reasonable shielding
52 4.6 Conclusion for a segment of 2nd harmonics instead of a single frequency point, where the area behind such structures should still be exploited to tackle the first of the two challenges.
4.6 Conclusion
In this Chapter, several practical aspects crucial for the understanding and design of a modern Chireix PA were considered. An expression for a load maximizing the power capability in accordance with the selected transistors’ voltage and current ratings was obtained. It was argued that the inclusion of shielded harmonic terminations in the combiner constitutes a condition for proper Chireix outphasing operation. Subsequently, the location where to expect the impedance loci on the Smith-chart upon compensating the nonlinear output capacitance was anticipated. Besides that, it has been reasoned that the Chireix concept can actually sustain some limited BW support from the PA blocks. Based on the aforementioned outcomes, the next Chapter presents a Chireix PA design method, including verification using LS models, culminating in a 60 W Chireix PA design.
53 54 Chapter 5 Chireix PA Design
“Unfortunately, both simulation and experimental results appear to fall well short of the idealized analysis.” — Steve Cripps, RF Power Amplifiers for Wireless Communications
To test the outcomes and implications discussed in the previous Chapters, two class-B Chireix PA design cases using Cree’s CGH27030F 30 W GaN HEMTs [47] following both the same design technique with the only difference being the absence or presence of 2nd harmonic terminations in the Chireix combiner are simulated and compared. The Chapter concludes with a 60 W Chireix PA design.
5.1 Design Methodology
The developed design technique is summarized in the following steps:
1. Select convenient bias voltages.
2. Design the input and output bias network (Fig. 5.1).
3. Carry out source-pull & initial load-pull simulations.
4. Design input matching accounting for stability.
5. Carry out load-pull 2nd harmonic simulation.
6. Design 2nd harmonic termination structure (Fig. 5.1).
7. Realize the Chireix combiner as equation blocks (Fig. 5.1).
8. Test outphasing operation and optimize combiner elements.
9. Calculate its 3-port S-parameter.
10. Realize the 3-port in TL then in Momentum environments.
55 5 Chireix PA Design where steps 5 and 6 are skipped in the nonharmonic combiner case. Step 7 expands into:
1. Calculate the 2-port compensation block of the overall package and 2nd harmonic termination structure. The Y-matrix of this compensation block is obtainable from the inverse of the T-matrix of the overall structure to be compensated (Fig. 5.1). § § § ˆ § 2. Estimate a value of §Coutpf0q§ to be compensated for from Fig. 4.9. 1 3. Calculate the corresponding compensating inductance Lcomp 2 ˆ p q . ω0 |Cout f0 | 4. Calculate the Chireix ¨jX compensation elements as in (2.54).
5. Select an initial ZL value (Fig. 2.5). Design a convenient transformer to get it to 50 Ω later on.
6. Place the described blocks as shown? in Fig. 5.1 with the quarter-wave TL trans- formers having an impedance Z0 2ZL. 7. Similarly form path 2 except with a ¡ sign for the Chireix element, and join the
paths with ZL.
Figure 5.1: Path 1 of the practical Chireix combiner for the harmonic case.
The procedure can be iterated at several frequency points to avoid a narrow-band design.
5.2 Simulation Results
Fig. 5.2 and 5.3 show the simulated impedance loci referred to the package plane that each transistor experiences while the outphasing angle θ is swept, for respectively a Chireix
56 5.2 Simulation Results
PA without and with 2nd harmonic terminations in the combiner.
Figure 5.2: Package plane impedance loci on the Smith-chart at the fundamental (left) and 2nd harmonic (right ¡ renormalized to 5 Ω) for a nonharmonic Chireix ¥ combiner with θc 15 as a function of θ. The index i in Gammai corresponds to the device index, 1 being the device with the leading outphased signal.
0
9
9
. 2
. 2
8 1.0 .
1. . 0 0 .
.8 1 1 0
0 4 4 7
7 . .
. 1 1 0. 0
.6 .6
6
6 1 . . 1 0
0 .8 .8
1 1
5 0
5 0 . .
.
0 2 0 2.
4
4 . .
0 0
3.0 3.0
3 3
. . 0 0
4.0 4.0
2 0 5.0 .2 . 0 0. 5
1 1 0 . . 1 0 0 10
20 20
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.2 1.4 1.6 1.8 2.0 3.0 4.0 5.0 10 20 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.2 1.4 1.6 1.8 2.0 3.0 4.0 5.0 10 20
-20 0 2 -
Gamma2 Gamma1
1 -10 1 0. 0. 0 - - -1 Gamma2_2f0 Gamma1_2f0
2 2 - 5. 0
. . .0 0 0 5 - - -
0 0
. 4 . - 4 -
3 .3
-0. -0
0 0 .
.
3 - 3 -
.4 .4
-0 -0
5 0
. 5 0 . .
0 2. 2
- - 0 - -
8
8
.
.
1
1 -
6 -
. .6
6 6
0 . 0
- - . 1
1
-
7 7 - 4
. . 4
.
0 0 . 1
- - 8 1 -
2
.8 - . 2
9 .
9 .
0 0
. 0
. 1
- - 1
0 -
0 - 1.
- - - -1.0
Theta (5.000 to 105.000) Theta (5.000 to 105.000)
Figure 5.3: Package plane impedance loci on the Smith-chart at the fundamental (left) nd ¥ and 2 harmonic (right) for a harmonic Chireix combiner with θc 15 as a function of θ. The index i in Gammai corresponds to the device index, 1 being the device with the leading outphased signal.
57 5 Chireix PA Design
80 16 Combiner w/o 2nd Harmonic 70 14 Combiner w 2nd Harmonic 60 12 50 10 (V) 40 8 ds2 V PAE (%) 30 6 20 4 nd 10 Combiner w/o 2 Harmonic 2 Combiner w 2nd Harmonic 0 0 5 15 25 35 45 55 65 75 85 95 105 30 32 34 36 38 40 42 44 46 48 ◦ Pout (dBm) θ ( ) (a) (b)
Figure 5.4: (a) Simulated Chireix PA PAE and (b) 2nd harmonic drain voltage magnitude ¥ using LS models (θc 15 ).
The similarity between the simulated loci at the fundamental1 and the idealized Chireix loci after taking into account Cout compensation (Fig. 4.12)§ can be§ observed. The opti- § ˆ § mum compensating inductance was found to correspond to §Coutpf0q§ 3.2 pF. Fig. 5.4a shows the corresponding PAEs, confirming that it is not possible with a nonharmonic configuration to get close in shape to the promised ideal Chireix PA curve (Fig. 2.10). The two designs exhibit almost identical behaviors at the fundamental where the load is modulated due to the outphasing action, but the difference in efficiency performance is primitive. Although almost the exact same P max and P AEmax are achievable, the perfor- mance in PBO is hugely different (Fig. 5.4a): while the 2nd harmonic terminations are floating in the first case (Fig. 5.2), they are locked to a certain desired angle ( 100 ¥ for the reflection factor referred to the package plane) in the second one (Fig. 5.3) despite the load being modulated as θ is varying. This is done by using the area behind the harmonic traps in each of the paths to realize the desired phase of the reflection factor at the 2nd harmonic (Fig. 5.1). The simulated 2nd harmonic drain voltage is shown in Fig. 5.4b for each of the cases. It must be mentioned that losses due to dissipation in passive matching networks will result in some PAE degradation upon realization. For a two port network, the losses [68] are given by: 2 2 ς 1 ¡ |S11| ¡ |S12| (5.1)
As this quantity depends on the terminations, its use requires the correct values of the transistor’s input impedance when applied at the input side for instance. In order to get accurate results, cosimulation using ADS’s Momentum is employed. A comparison to
1For extreme outphasing angles, the loads might leave the unity circle of the Smith-chart. This behavior can be linked to the nature of actively modulated PA architectures where the output impedance of a transistor is actively seen by the other transistor, resulting in a slightly negative resistance.
58 5.3 Realization measurements is presented in the next Chapter.
5.3 Realization
The layout of the designed Chireix PA is depicted in Fig. 5.5. The design was originally targeted to include a driver stage. Inquiry of the FPGA power capabilities led to dropping the shown drivers’ circuitry for external ones with about 38 dB gain at 2140 MHz [69]. The PA’s hardware was realized on RO 4350B substrate [70] (Fig. 5.6).
Figure 5.5: Layout of the Chireix PA with harmonic combiner.
(a) (b)
Figure 5.6: (a) Driver stage circuitry built for separate testing and (b) realized Chireix PA with harmonic combiner on a 15 ¢ 12 cm2 board.
59 5 Chireix PA Design
Instead of a realization with stub topology, the Chireix elements were implemented us- ing two different length transmission lines [71]. The same applies for the capacitance compensation element, Lcomp (Fig. 5.1), where the two inductors (one per path) were merged into the TLs; As long as the agreement between the 3-port S-parameters of the equation-based combiner and its TL-based counterpart (at DC, f0 and 2f0 at least) is preserved, the realization topology can be freely set. On the other hand, the harmonic traps were realized using radial stubs. This realization tends to offer more bandwidth performance [72]. The mathematical symmetry of the Chireix combiner properties does not reflect into a physical geometric symmetry, hence the board is not symmetrical about its middle horizontal axis. In the following, the built setup dedicated for characterizing and driving the Chireix PA is described. Consequently, static and real-time measurement results are presented.
60 Chapter 6 Characterization
Although direct measurements of the impedance loci at the drain terminals using probes [73] could constitute an option for comparison purposes, in this work the assessment of the earlier discussed outcomes are made mainly through efficiency and spectrum mea- surements. In this Chapter, an overview of the built setup configurations and outphasing measurement practices is presented. Static measurement results of the designed Chireix PA are reported thereafter, followed by dynamic testing results.
6.1 Measurement Setup
6.1.1 Manual Configuration
As the preliminary measurements were concerned with concept assessment and develop- ment, a basic setup was firstly built. In this initial configuration, the SCS block (2.1) was exchanged for an RF signal generator feeding a driver PA whose output is followed by a 3 dB symmetric power splitter and a manually adjustable phase shifter connected to one of the available branches (PA2 in this case) after the splitter. Fig. 6.1 depicts the corresponding setup. The phase shifter emulates outphasing operation by introducing a phase delay that ultimately would have been encoded digitally if an SCS was employed. The output of the PA under test is connected to an attenuator before reading the output power with a power meter on one channel. The other channel was used for reading the input power just before splitting. In order to avoid burning the transistors when mea- suring the performance at considerable power levels, the setup was configured for pulsed measurements using an external arbitrary waveform generator. The measurement routine mainly consisted of recording the output power and corresponding DC current for each manually adjusted phase delay. This allowed to fully characterize the instantaneous static efficiency of the PA. Nevertheless, this came at a substantial time-cost. Considering that several sweeps of frequency, power levels, gate voltages and drain voltages were necessary, a rather automated setup looked much more convenient. In addition to that, the need
61 6 Characterization for real-time outphasing drive constituted a strong motivation to build a digital version of the setup so that the demonstrator can eventually be tested with some standard com- munication signals. After all, besides the quest for high efficiency, it was the modern advances in DSP and computational power that allowed to refuel the activities on the Chireix architecture.
Figure 6.1: Basic outphasing measurements setup.
6.1.2 Digital Configuration
A block diagram of the built digital measurement setup is depicted in Fig. 6.2. The
−
−
−
(a) (b)
Figure 6.2: (a) Digital setup block diagram and (b) photo. setup was configured for pulsed measurements by direct access to the IQ data, without
62 6.1 Measurement Setup the need for an external pulse source, before sending them to the FPGA platform1 via LAN. The passive components were calibrated for losses and phase delays. Due to the slightly different gains of the driver amplifiers (D1 and D2), a closed loop control algorithm utilizing the power meter (PM) and a switch (SW) selecting the path to read has been implemented. The controllable variables are: the RF, the pulse width, the duty cycle, the input power levels at the device under test (DUT), the DUT gate voltage, the DUT drain voltage and the outphasing angle θ at the DUT input plane. The measurement is controlled in MATLAB environment. Later on, the setup was upgraded with a spectrum analyzer (SA) at the output complementing the spectrum monitoring through the RX path at the input.
6.1.3 Calibration
Before performing outphasing tests, a number of calibrations are to be made. Figure 6.3 shows the passive losses and delay imbalances that exist between the two branches. After characterization with a network analyzer (NA), the collected data were logged into the PC for automatic calibration purposes. Similarly, the output attenuation was captured.
−0.06 −4
−0.08 −4.5 −0.1 −5 −0.12 −5.5 −0.14 −6 Phase Imbalance (°) Loss Imbalance (dB) −0.16
−0.18 −6.5 1600 1800 2000 2200 2400 2600 2800 1600 1800 2000 2200 2400 2600 2800 Frequency (MHz) Frequency (MHz)
(a) (b)
Figure 6.3: (a) Losses (b) and delay imbalances relative to path 1.
As for the external drivers [69], an automatic control script allowed to balance the gain between the two modules exhibiting slight differences (Fig. 6.4). For that purpose, the switch [74] that allows readings to be toggled between either of the input paths was also characterized for calibration (Fig. 6.5). A related script is contained in AppendixD.
1The FPGA used is an internal version for development purposes with a DAC rate of 307.2 MHz.
63 6 Characterization
39 Module 1 38 Module 2
37
36
Gain (dB) 35
34
33 2 2.05 2.1 2.15 2.2 2.25 2.3 Frequency (GHz)
(a) (b)
Figure 6.4: (a) Driver module and (b) small-signal gains.
(a) (b)
Figure 6.5: (a) The used switch and (b) its calibration setup.
Finally, to test the system functioning, a 3 dB combiner was exchanged momentarily in place of the outphasing DUT and a power level of 21 dBm was applied at each of the inputs. The outphasing angle was then (digitally) swept. Fig. 6.6 shows the difference between a noncalibrated and a calibrated setup, where in the latter case the peak power
64 6.1 Measurement Setup is observed right at 0 ¥ outphasing angle, i.e. when the outphasing signals are expected to be in-phase. The maximum output of slightly less than 24 dBm is due to the losses in the combiner itself. Some exemplary synchronized pulsed signals are shown in 6.7.
24 No Correction SPI CAL 23.5
23 Pout (dBm) 22.5
22 −30 −20 −10 0 10 20 30 θ (°)
(a) (b)
Figure 6.6: (a) 3 dB combiner and (b) outphasing measurement test.
(a) (b)
Figure 6.7: (a) Synchronized pulsed signals and (b) a zoomed view.
6.1.4 LO Leakage
The last remaining step before being able to conduct outphasing measurements is the local oscillator (LO) suppression. As the power meter’s sensors used for accurate power level readings instead of the SA are of broadband nature, suppressing the LO frequency (around 2.3 GHz) further enhances the readings. This becomes ultimately needed for low power readings as observed in the next Section. A basic compensation algorithm was
65 6 Characterization written in order to digitally achieve a cleaner spectrum (Fig. 6.8). As a consequence, this contributed to the LO’s image frequency getting attenuated too. With that, the setup
10 10 0 0 −10 −10 −20 −20 −30 −30 dBm dBm −40 −40 −50 −50 −60 −60 −70 −70 2000 2100 2200 2300 2400 2500 2600 2000 2100 2200 2300 2400 2500 2600 MHz MHz
(a) (b)
Figure 6.8: (a) Spectrum seen without and (b) with LO suppression around 2.3 GHz. was ready for the Chireix PA characterization and testing2.
6.2 Characterization using Static Measurements
Static outphasing measurements are used first to characterize the built Chireix PA. This allows the programming of the SCS algorithm for later usage with real-time signals.
6.2.1 Outphasing Measurements
For a constant input power, the outphasing angle is swept and the output power and corresponding efficiency values are fetched. These measurements were performed under the following conditions: 2 % duty cycle for the pulsed outphased signals, V gs ¡3.8 V,
V ds 38 V and P in 35 dBm. Fig. 6.9 shows good agreement between simulations and measurements where no circuit tuning has been made, confirming the previous analysis. For such a heavy load modulation architecture, model-based design seems the favorable way to enable a good realization, where similarly in this regard, some so called first-pass Doherty designs are appearing in conjunction with the steady advances in GaN HEMT modeling [75]. In Fig. 6.10, it can be seen that the percentage variation in efficiency is kept less than ¨2 % within a 60 MHz interval (RF bandwidth target) and down to 9 dB PBO levels. The drain efficiency for 7.5 dB PBO peaks at 2.11 GHz and amounts to 46.1 % approximately. Fig. 6.11 shows the measured efficiency of the Chireix PA for different drain voltage levels demonstrating some potential to hybridize it with a supply voltage modulated PA architecture [76].
2Code insights along with the function for suppressing the LO frequency are included in AppendixD.
66 6.2 Characterization using Static Measurements
80 70 60 50 40 30 Drain Efficiency (%) 20 Measurements ADS Momentum 10 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Pout (dBm)
Figure 6.9: Harmonic Chireix outphasing at 2.14 GHz.
1 dB 6 dB 7 dB 7.5 dB 8 dB 9 dB 75 70 65 60 55 50 45 40
Drain Efficiency (%) 35 30 2080 2090 2100 2110 2120 2130 2140 Frequency (MHz)
Figure 6.10: Measured efficiency at different PBO levels vs frequency.
75 65 55 45
35 28 V 32 V 25 36 V 40 V Drain Efficiency (%) 15 44 V 48 V 5 29 31 33 35 37 39 41 43 45 47 49 Pout (dBm)
Figure 6.11: Measured efficiency for several drain supply voltages (RF 2.12 GHz and
P in 35 dBm).
67 6 Characterization
6.2.2 Low Power Measurements
The dynamic range of an envelope modulated signal can reach 60 dB or more in practice (theoretically infinite due to zero-crossing). The action of outphasing alone cannot support such a range (Fig. 6.12); An unperfect cancellation of the two out-of-phase signals driving the nonlinear PAs ¡ possibly due to transistor fabrication related imbalances in Vgs and/or
Vds ¡ limits the outphasing action dynamic range to 20¡25 dB. In order to cover the lower
(a) (b)
Figure 6.12: (a) Measured outphasing dynamic range as θ is swept and (b) corresponding efficiency. output power range, one way is to lower the driving signals’ power while keeping θ constant moving therefore into a linear regime of operation [40]. As the PAR is well contained in the outphasing dynamic range, this kind of mixed-mode operation does negligibly affect the average efficiency. The measurements in this range were done after LO leakage digital cancellation. In the following, complementary measurements using real-time signals with the SCS programmed based on the static measurements are presented.
6.3 Real-Time Dynamic Measurement Results
The PA was tested with a 1-Carrier W-CDMA signal having a 7.5 dB PAR. It exhibited around 45 % average drain efficiency with a 39.6 dBm average output power. Despite the bandwidth expansion experienced with the individual outphasing signals, the amplified signal after recombination retained the original bandwidth of 5 MHz. The ACLR values without digital predistortion (DPD) amounted to 26 dBc approximately. The output spectrum of the amplified signal is shown in Fig. 6.13. A similar test was carried out with 20 MHz 2-Carrier W-CDMA signal resulting in around 44 % average drain efficiency. Due to the mixed-mode drive instead of an ideal outphasing drive, some nonnull dB PAR was measured at the inputs to the DUT. Measurement results are summarized in Table 6.1.
68 6.3 Real-Time Dynamic Measurement Results
Figure 6.13: Amplified signal’s spectrum ¡ One carrier.
Figure 6.14: Amplified signal’s spectrum ¡ Two carrier.
Table 6.1: Chireix PA measurement results.
Testing w 7.5 dB PAR W-CDMA 5 MHz 1C 20 MHz 2C
PAR S1 1.3 dB 1.8 dB
PAR S2 1.3 dB 1.8 dB
Average Pout 39.6 dBm 39.6 dBm Average Drain Efficiency 45 % 44 %
69 70 Chapter 7
Outlook & Summary
The realization of a PA prototype confirming the operation of the promising Chireix ar- chitecture for BTS applications has prompted the initiation of an investigation concerning possible improvements in the future. In this process, a simulation environment using LS models was invoked whenever possible. This Chapter covers some practices and recom- mendations found to enhance the design’s performance. The Chapter wraps-up with a summary concluding the work.
7.1 Future Work
7.1.1 Source Second-Harmonic Termination
It is known that the harmonic terminations at the input side play a critical role in the performance of a single PA device [77]. To asses this effect on the Chireix PA, an in- circuit harmonic source pull simulation is performed at the inputs of the presented Chireix design. It was found that the 2nd harmonic reflection angle is the dominating aspect with a significant role on PAE in PBO as seen in Fig. 7.1. This is the first time that two efficiency peaks are simultaneously observed in a practical Chireix PA design using LS models. It is expected however that some PAE degradation occurs upon EM Momentum simulation and realization due to the passive networks (input matching and combiner) dissipative losses. A very good option to mitigate that is to work at the transistor level [78]. The obtained result constituted a motivation to check the efficiency behavior with strictly smaller compensation angles and therefore a targeted lower BO peak (2.58). It can be observed from Fig. 7.2 that the low drive PAE peak deteriorates with smaller θc designs. This is attributed to the limited gain of the transistors as the outphasing principle relies on constant input drive. A key solution is therefore to manufacture transistors with higher gains.
71 7 Outlook & Summary
Figure 7.1: Simulated effect of a dedicated 2nd harmonic termination at the input sides of the Chireix PA.
80 70 60 50 40
PAE (%) 30 θc = 5 ◦ θc = 7 ◦ 20 θc = 9 ◦ θc =11 ◦ 10 θc =13 ◦ θc =15 ◦ 0 30 32 34 36 38 40 42 44 46 48 Pout (dBm)
Figure 7.2: Simulated effect of smaller compensation angles Chireix designs.
7.1.2 Architecture Load-Pull
In Chapter4, the presented discussion on the power capability resulted in the equa- tions (4.4) and (4.10) as first approximations to a ZL design value. On the other hand, Fig. 4.9 gave an idea about the range to expect for selecting the compensation inductance
72 7.1 Future Work
Lcomp. Alternatively, a search for the best combination of these two design parameters is proposed. This can be achieved by forming the Chireix PA circuit with the combiner as equation blocks in schematic environment as described in Chapter5, and then pa- rameterizing these variables around the found approximations resulting in an in-circuit optimization (Fig. 7.3). Average efficiency calculations can be involved at this stage as outlined in Section 3.5. Additional simulations with a parametrized θc (or other bias volt- age variables for instance) can be incorporated. With the LP method, regardless whether in measurement or simulation environments, being quiet familiar for a single device [79], the suggested approach can be said to be analogous to load-pulling the Chireix PA ar- chitecture instead. After finding the optimal range, a refined search can be made. The
ZL = 15.0 Ohm ZL = 16.0 Ohm ZL = 17.0 Ohm ZL = 18.0 Ohm 80 80 80 80 70 70 70 70 60 60 60 60 50 50 50 50 40 40 40 40 30 30 30 30 20 20 20 20 10 10 10 10 0 0 0 0 30 32 34 36 38 40 42 44 46 48 30 32 34 36 38 40 42 44 46 48 30 32 34 36 38 40 42 44 46 48 30 32 34 36 38 40 42 44 46 48
ZL = 19.0 Ohm ZL = 20.0 Ohm ZL = 21.0 Ohm ZL = 22.0 Ohm 80 80 80 80 70 70 70 70 60 60 60 60 50 50 50 50 40 40 40 40 30 30 30 30 20 20 20 20 10 10 10 10 0 0 0 0 30 32 34 36 38 40 42 44 46 48 30 32 34 36 38 40 42 44 46 48 30 32 34 36 38 40 42 44 46 48 30 32 34 36 38 40 42 44 46 48
ZL = 23.0 Ohm ZL = 24.0 Ohm ZL = 25.0 Ohm ZL = 26.0 Ohm 80 80 80 80 70 70 70 70 60 60 60 60 50 50 50 50 40 40 40 40 30 30 30 30 20 20 20 20 10 10 10 10 0 0 0 0 30 32 34 36 38 40 42 44 46 48 30 32 34 36 38 40 42 44 46 48 30 32 34 36 38 40 42 44 46 48 30 32 34 36 38 40 42 44 46 48
ZL = 27.0 Ohm ZL = 28.0 Ohm ZL = 29.0 Ohm ZL = 30.0 Ohm 80 80 80 80 70 70 70 70 60 60 60 60 50 50 50 50 40 40 40 40 30 30 30 30 20 20 20 20 10 10 10 10 0 0 0 0 30 32 34 36 38 40 42 44 46 48 30 32 34 36 38 40 42 44 46 48 30 32 34 36 38 40 42 44 46 48 30 32 34 36 38 40 42 44 46 48
Figure 7.3: Chireix architecture LP: ZL is varied from 15 Ω to 30 Ω in steps of 1 Ω and
Lcomp varied according to assumed Couts between 1.7 pF and 3.7 pF in steps
of 0.1 pF. The x-axis corresponds to Pout (dBm) and the y-axis to PAE (%). results are plotted in Fig. 7.4. In such a heavy load-modulated architecture, the classical tweaking by employment of tuning sticks on the board is not expected to result in finding the optimal outcomes. While for a PA made out of a single transistor this can be effective [80], applying this approach to the Chireix combiner can lead for instance to improvements
73 7 Outlook & Summary
ZL = 20.0 Ohm ZL = 20.5 Ohm ZL = 21.0 Ohm 80 80 80 70 70 70 60 60 60 50 50 50 2.9 pF 2.9 pF 2.9 pF 40 3 pF 40 3 pF 40 3 pF 30 3.1 pF 30 3.1 pF 30 3.1 pF 3.2 pF 3.2 pF 3.2 pF 20 3.3 pF 20 3.3 pF 20 3.3 pF 3.4 pF 3.4 pF 3.4 pF 10 3.5 pF 10 3.5 pF 10 3.5 pF 0 0 0 30 32 34 36 38 40 42 44 46 48 30 32 34 36 38 40 42 44 46 48 30 32 34 36 38 40 42 44 46 48
ZL = 21.5 Ohm ZL = 22.0 Ohm ZL = 22.5 Ohm 80 80 80 70 70 70 60 60 60 50 50 50 2.9 pF 2.9 pF 2.9 pF 40 3 pF 40 3 pF 40 3 pF 30 3.1 pF 30 3.1 pF 30 3.1 pF 3.2 pF 3.2 pF 3.2 pF 20 3.3 pF 20 3.3 pF 20 3.3 pF 3.4 pF 3.4 pF 3.4 pF 10 3.5 pF 10 3.5 pF 10 3.5 pF 0 0 0 30 32 34 36 38 40 42 44 46 48 30 32 34 36 38 40 42 44 46 48 30 32 34 36 38 40 42 44 46 48
ZL = 23.0 Ohm ZL = 23.5 Ohm ZL = 24.0 Ohm 80 80 80 70 70 70 60 60 60 50 50 50 2.9 pF 2.9 pF 2.9 pF 40 3 pF 40 3 pF 40 3 pF 30 3.1 pF 30 3.1 pF 30 3.1 pF 3.2 pF 3.2 pF 3.2 pF 20 3.3 pF 20 3.3 pF 20 3.3 pF 3.4 pF 3.4 pF 3.4 pF 10 3.5 pF 10 3.5 pF 10 3.5 pF 0 0 0 30 32 34 36 38 40 42 44 46 48 30 32 34 36 38 40 42 44 46 48 30 32 34 36 38 40 42 44 46 48
ZL = 24.5 Ohm ZL = 25.0 Ohm 80 80 70 70 60 60 50 50 2.9 pF 2.9 pF 40 3 pF 40 3 pF 30 3.1 pF 30 3.1 pF 3.2 pF 3.2 pF 20 3.3 pF 20 3.3 pF 3.4 pF 3.4 pF 10 3.5 pF 10 3.5 pF 0 0 30 32 34 36 38 40 42 44 46 48 30 32 34 36 38 40 42 44 46 48
Figure 7.4: Chireix architecture LP: ZL is varied from 20 Ω to 25 Ω in steps of 0.5 Ω and
Lcomp varied according to assumed Couts between 2.9 pF and 3.5 pF in steps
of 0.1 pF. The x-axis corresponds to Pout (dBm) and the y-axis to PAE (%). in one aspect such as efficiency while loosing BW. Even if one is trying to manually tune the Chireix combiner for one path, it is unlikely that the combiner will remain balanced as a whole and therefore the performance will drift unexpectedly. Therefore the suggested architecture LP can prove a helpful tool in searching the pZL,Lcomp, θcq space before any hardware realization taking place.
7.1.3 Miscellaneous
In the following, a number of different aspects are listed for future considerations.
Full utilization of simulator options: The adequate use of state-of-the-art CAD abilities is expected to result in more accurate modeling of the matching structures, reducing further discrepancies between simulations and measurements. Considering for instance the use of area pins [81] additionally contributes to the design’s success.
Employment of rotated radial stubs: It has been argued that the BW expansion
74 7.1 Future Work
experienced after splitting the incoming signal to outphased signals requires some broadband PA performance. In this regard, employing rotated butterfly radial stub [82] topologies could be useful.
Miniaturization of the combiner: Alternatively, the miniaturization of the com- biner for instance by making it integrated could lead to reductions simultaneously in size and costs.
Exploration of other classes: As long as the harmonics are isolated, some classes such as class-E [17] could further contribute to efficiency1 when used as the Chireix PA cores. On the other hand, class-J [13, 67] could prove useful when it comes to overcoming the BW challenges.
Hybridization with other architectures: With several drain voltages, the mea- surement presented in the last Chapter revealed some potential for applying drain voltage modulation to the Chireix PA. Considering new alternatives when it comes to hybridization with other types of architecture might lead to beneficial outcomes.
Mixed-mode smooth transition: The measured ACLR values hovered around 26 dBc. Before resorting to any DPD technique [83, 84], the ACLR can first be improved by recoding the transition between the linear and outphasing regimes so that θ’s function is continuously differentiable rather than continuous (Fig. 7.5).
100 Implemented function 90 Smoothed function 80 70
) 60 ◦ (
θ 50 40 30 20 10 ~ Output Power
Figure 7.5: Mixed-mode outphasing angle functions.
1with maximum efficiencies beyond the maximum 78 % of the ideal class-B.
75 7 Outlook & Summary
7.2 Summary
In this work, the suitability of outphasing PAs for use as a high efficiency solution in next generation BTS applications has been investigated. Analysis and comparison of a multitude of outphasing variants suggested that the original Chireix concept still holds the most promises among them. Consequently, the work presented the first analysis on the implementation of the Chireix concept using state-of-the-art transistor devices rather than vacuum tubes or ideal PAs. Specifically, the output capacitance effects on Chireix PA performance has been consid- ered in detail. The study showed that unexpected changes in the harmonic voltages at the transistor terminals could significantly alter the nonlinear capacitance’s value during outphasing operation. This makes it “uncompensatable” and subsequently explains why any nonharmonic transistor implementation of the combiner was unsuccessful in terms of the predicted Chireix performance. Besides the requirement of a desired harmonic termi- nation(s) to boost efficiency, it was shown that the inclusion of at least 2nd harmonic traps on the output side is a must for Chireix PA realization. That prevents any power exchange between the two PA paths at the 2nd harmonic. As well, it results in the stabilization of the nonlinear output capacitance during outphasing action and therefore enables its compensation (mathematically with an inductance) for proper outphasing functioning. Its value to be compensated for has been described most importantly as a function of the outphasing signals’ magnitude in addition to the bias voltages. The analysis has been fortified with the found optimum value of 3.2 pF for the considered Chireix design using
CGH27030F Cree GaN HEMTs, which deviates from the extracted small-signal Cout at the same bias voltages. On the other hand, by not fixing the second harmonic terminations in the combiner, it was seen that modulating the input amplitude too is required. That worked only in some specific cases. The work has also reported that the maximum power capability of the Chireix architecture is in practice affected by the compensation angle choice. However the power degradation effects were found to be minor and posed no severe consequences on the latter’s selection. Based on these findings, a method to design a practical Chireix PA using transistors has been proposed in which the harmonic Chireix combiner is mathematically defined as a 3-port network in a first step. In an attempt to cover the analytical, numerical, simulation and measurements aspects, the discussed outcomes have been used to build a 60 W Chireix PA. A dedicated setup with widely flexible digital control abilities for characterizing and driving the Chireix PA has been built. All aspects were found to reenforce the presented understanding. The PA was tested with 5 MHz 1-Carrier and 20 MHz 2-Carrier W-CDMA
76 7.3 Zusammenfassung signals of 7.5 dB PAR, exhibiting respectively 45 % and 44 % average drain efficiency. The work concluded with recommendations for improvements to be considered in the near future. Early LS simulations supplementary incorporating the 2nd harmonic terminations in the input matching networks pointed out to the possibility of realizing the two theorized peaks in the Chireix PA PAE curve for the first time. Fig. 7.6 shows a comparison
80 70 60 50 40 30 [38] 20 [39] [40] Drain Efficiency (%) This work 10 This work Chireix ideal 0 −16 −14 −12 −10 −8 −6 −4 −2 0 PBO (dB)
Figure 7.6: Summary. with other results from literature. This work further closes the gap between practice and ideal Chireix PA performance. Together with high gain transistors, a realization as an integrated solution satisfying the harmonic combiner’s 3-port S-parameter could finally pave the way for the commercialization of the Chireix PA for next generation telecommunication applications.
7.3 Zusammenfassung
Die vorliegende Arbeit hat die Eignung von Chireix-Verst¨arkern f¨urzuk¨unftigeMobilfunk- Basisstationen untersucht. Die Abw¨agungunterschiedlicher Varianten des Outphasing- Verfahrens hat gezeigt, dass der urspr¨ungliche Ansatz von Chireix noch immer den gr¨oßten Nutzen verspricht. Hierauf aufbauend setzte die vorliegende Arbeit zum ersten Mal das klassische Chireix-Verfahrens mittels moderner Transistorbauelemente anstelle von Vakuum-R¨ohrenoder (in der Theorie) idealisierten Leistungsverst¨arkern um. Hierf¨urmusste insbesondere der Einfluss der Ausgangskapazit¨atauf das Verhalten eines Chireix-Verst¨arkers untersucht werden. Im Outphasing-Betrieb hat sich ein unerwartet ausgepr¨agterEinfluss der Spannungen an den Transistoranschl¨ussenbei Vielfachen der Grundfrequenz auf den Wert der (nichtlinearen) Ausgangskapazit¨atbei der Grundwelle gezeigt. In Folge l¨asstsich die Ausgangskapazit¨atnicht kompensieren. Die vorliegende
77 7 Outlook & Summary
Arbeit konnte so zum ersten Mal erkl¨aren,weswegen verschiedene Ans¨atzeaus der Ver- gangenheit unerwartet unbefriedigende Ergebnisse gezeigt hatten: Die erfolgreiche Um- setzung des Chireix-Verfahren mithilfe von Transistoren erfordert beim Bau des Chireix- Kombiners eine Ber¨ucksichtigung des Transistor-Verhaltens bei den Oberwellen ebenso wie bei der Tr¨agerfrequenz! Neben dem Einfluss geeigneter harmonischer Abschl¨usseauf den Wirkungsgrad konnte gezeigt werden, dass zumindest bei der zweifachen Grundwelle die Isolation der beiden Verst¨arkerpfade unabdingbar f¨urdie Funktion des Chireix- -Verst¨arkers ist: Im Chireix-Verst¨arker muss die Ausgangsimpedanz der aktiven Bauele- mente im Summationsglied (resonant) ausgeglichen werden. Ohne Isolation verhindert der wechselseitige Einfluss der Oberwellen des einen Transistors auf die Ausgangskapazit¨at des anderen eine erfolgreiche Kompensation. Schließlich wurde gezeigt, dass der auszugle- ichende Kapazit¨atswert nicht nur von den eingestellten Transistor-Arbeitspunkten, son- dern vielmehr vom anliegenden Signalpegel abh¨angt.Diese Erkenntnis wird untermauert durch eine deutliche Ablage des im Verst¨arkerentwurf anzusetzenden Kapazit¨atswertes von dem aus dem Modell extrahierten Kleinsignalwert der Ausgangskapazit¨atder ver- wendeten Transistoren (CGH27030F von Cree). Auf der anderen Seite konnte gezeigt werden, dass in einzelnen Sonderf¨allenauf einen isolierenden Abschluss bei den Ober- wellen verzichtet werden kann, wenn zus¨atzlich zu der relativen Phasenlage der Ein- gangssignale auch der Eingangspegel in Abh¨angigkeit von der gew¨unschten Ausgangsleis- tung angepasst wird. In der Arbeit wurde auch gezeigt, dass die Leistungsf¨ahigkeit des Chireix-Verst¨arkers im praktischen Beispiel vom gew¨ahltenKompensationswinkel abh¨angt. Die Abh¨angigkeit erscheint jedoch nicht ausgepr¨agtgenug, um die Wahl des Kompensationswinkels zu beeinflussen. Auf den dargestellten Erkenntnissen aufbauend, konnte ein neuartiges Entwurfsverfahren f¨urChireix-Verst¨arker erarbeitet werden, das das Summationsglied als Dreitor auffasst, dessen Verhalten bei Grundfrequenz und Ober- wellen betrachtet wird. Anhand eines 60 W Beispielverst¨arkers wird der Verst¨arker teils anhand analytischer L¨osungenund teils mithilfe der numerischen Simulation optimiert und schließlich mithilfe von Messungen charakterisiert. Die unterschiedlichen Blickwinkel f¨ugensich zu einem stimmigen Gesamtbild zusammen und unterst¨utzendie dargestellte Betrachtungsweise, insbesondere die große Bedeutung der Oberwellen beim Entwurf des Summationsgliedes.
Wird der Beispielverst¨arker in der Messung mit einem 5 MHz breiten 1-Tr¨ager-W-CDMA- Signal beaufschlagt, zeigt er einen Wirkungsgrad von 45 %, bei einem 2-Tr¨ager-W-CDMA- Signal mit 20 MHz Bandbreite sind es 44 %.
Die Arbeit schließt mit einem Ausblick auf zuk¨unftige Verbesserungsm¨oglichkeiten. Ber¨ucksichtigen wir in ersten Großsignalsimulationen neben dem ausgangsseitigen har- monischen Abschluss auch das eingangsseitige Verhalten bei der ersten Oberwelle, so
78 7.3 Zusammenfassung
finden wir Hinweise, dass sich die ausgepr¨agte Uberh¨ohung¨ des Wirkungsgrades bei niedri- gen Singalpegeln wie sie die Theorie des Chireix-Verst¨arkers fordert zum ersten Mal auch im praktischen Beispiel sollte verwirklichen lassen. Die Simulationsergebnisse werden in Abb. 7.6 mit anderen Arbeiten vergleichen: Unter Ber¨ucksichtigung des eingangsseit- igen Oberwellenabschlusses verkleinert die vorliegende Arbeit die L¨ucke zwischen den bisherigen experimentellen Ergebnissen und dem theoretischen Versprechen des Chireix- Verst¨arkers deutlich. Werden die Lehren der vorliegenden Arbeit zur Unabdingbarkeit der Oberwellenterminierung in einem integrierten Aufbau und unter Einsatz von Transis- toren mit hoher Verst¨arkungumgesetzt, kann dies dem Chireix-Verst¨arker den Weg f¨ur den Einsatz in Mobilfunk-Basisstationen ebnen.
79 80 Appendix A Transmission Line Equations
Figure A.1: Transmission Line.
Assuming a monochromatic wave (time harmonic fields), all quantities will be proportional to ejωt, and thus the phasor Vrpzq depicted in Fig. A.1 is defined according to ! ) vpz, tq < Vrpzqejωt (A.1)
2π With β λ , the solution to the telegrapher’s equation [85] results in:
Vrpzq V e¡jβz V ¡ejβz (A.2a) V V ¡ Irpzq e¡jβz ¡ ejβz (A.2b) Z0 Z0
¡ ¡ V ZL Z0 Γ (A.3) V ZL Z0
Vrpzq V pe¡jβz Γejβzq (A.4)
! ) 1 P < Vr ¤ Ir¦ (A.5) av 2
81 82 Appendix B Some Probabilistic Notions
If X is a random variable characterized by a probability density function (PDF) fpxq, then its expected value or mean µ can be computed as
8» µ x ¤ fpxq ¤ dx (B.1) ¡8
The value of x for which fpxq has its maximum value is called the mode of the random variable and is denoted by σ, hence
fpσq maxpfpxqq (B.2)
The cumulative distribution function (CDF) describes the probability that the random variable X will be found to have a value less than or equal to x:
»x F pxq fptq ¤ dt (B.3) ¡8
0.7 1 σ =1 σ =2 σ =3 0.6 σ =4 σ =5 0.8 0.5 0.6 ) ) 0.4 x x ( ( f 0.3 F 0.4 0.2 σ =1 0.2 σ =2 0.1 σ =3 σ =4 σ =5 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 x x (a) (b)
Figure B.1: (a) PDFs and (b) CDFs corresponding to different Rayleigh distribution modes.
83 B Some Probabilistic Notions
Studies of the PDF and CDF of the Rayleigh distribution can be found in many textbooks such as [86]. The respective functions are given by
x ¡ x2 fpxq ¤ e 2σ2 (B.4a) σ2 ¡ x2 F pxq 1 ¡ e 2σ2 (B.4b) for x ¥ 0. These are plotted in Fig. B.1 for different mode values. For this particular distribution, the mean and mode are linked through c π µ σ ¤ (B.5) 2
84 Appendix C Proof of the DC & Fundamental Compo- nent Expressions of the Nonlinear Out- put Capacitance
The corresponding Fourier series coefficients are given by:
2π »ω0 ω0 Qres a0 dt (C.1a) π VDC V0 sinpω0tq 0 2π »ω0 ω0 Qres a1 cospω0tqdt (C.1b) π VDC V0 sinpω0tq 0 2π »ω0 ω0 Qres b1 sinpω0tqdt (C.1c) π VDC V0 sinpω0tq 0
d p q du d p q du d p q du Using the identities du tan u 1 u2 , du arctan u cos2 u and du ln u u , it can be shown that
¤ ¢ § 2π p { q § ω0 arctan V0 ?VDC tan ω0t 2 § ¦ V 2 ¡V 2 § 2Qres ¦ a DC 0 § a0 ¥ § π V 2 ¡ V 2 § DC 0 § 0 § 2π § ω Qres § 0 a1 pVDC V0 sinpω0tqq§ πV0 0 ¤ ¢ § 2π p { q § ω0 2V arctan V0 ?VDC tan ω0t 2 § ¦ DC 2 ¡ 2 § Q VDC V0 b res ¦ω t ¡ a § 1 ¥ 0 2 2 § πV0 V ¡ V § DC 0 § 0
85 C Proof of the DC & Fundamental Component Expressions of the Nonlinear Output Capacitance Further substitution of the integrals intervals results in 2Q a n a res 0 DC 2 ¡ 2 VDC V0 a 0 1 £ 2Q V b res 1 ¡ n a DC 1 f0 2 ¡ 2 V0 VDC V0 P t ¡ u where following from the arctan function, nDC and nf0 Z ... 1, 0, 1, ... . To deter- mine these integers, the following limits whose values are known for V0 0, i.e. for a Qres static Coutptq , are evaluated: VDC a Q lim 0 res (C.4) Ñ V0 0 b2 VDC 2 2 lim a1 b1 0 (C.5) V0Ñ0 yielding nDC nf0 1. The large-signal DC and fundamental components of the output nonlinear capacitance can hence be written as
ˆ a0 Qres CoutpDCq a (C.6) 2 V 2 ¡ V 2 DC 0 £ § § b § § Q V §Cˆ pf q§ a2 b2 2 res a DC ¡ 1 (C.7) out 0 1 1 2 ¡ 2 V0 VDC V0
86 Appendix D Code Samples
Overall, 17 MATLAB functions were developed and 7 instrument drivers were invoked in addition to 20 loaded calibration files (including the cables’). In the following, three sam- ple scripts, the first one corresponding to loading the calibration data and generating the calibration look-up-tables (LUTs) for later access, the second one corresponding to the ini- tialization of the digital control setup and its configuration for outphasing measurements, and the last one corresponding to the LO suppression/cancellation are included.
87 D Code Samples
% NSN - RF Predevelopment % Zeid Abou-Chahine
% Generates phase and loss imbalances look up tables for the calibration % of the different pathes (passive components and switch) % Arbitrary reference taken: path1
% clc
% clear all
close all
global freq; global Inter_SPI; global Inter_P1_Loss; global Inter_P2_Loss; global Inter_SLI; global Inter_SOL;
Step = 0.5; % step for interpolation in MHz Violet = [127/255 16/255 162/255]; Orange = [255/255 175/255 0/255]; Yellow = [255/255 211/255 8/255]; Red = [175/255 0/255 51/255]; Green = [52/255 195/255 51/255]; Gray_L = [104/255 113/255 122/255]; Gray_M = [163/255 166/255 173/255]; Gray_S = [234/255 234/255 234/255];
Color = [Violet; Orange; Yellow; Red; Green; Gray_L; Gray_M; Gray_S]; set(0,'DefaultAxesColorOrder',Color)
Import measurement files
% % "Semi-Rigid" coaxial cable [Freq,Cable_dB] = importfile('Cable_dB.CSV',13, 213); [Freq,Cable_Phase] = importfile('Cable_Phase.CSV',13, 213);
% % Coupler 10dB [Freq,PM_Coupling_dB] = importfile('C10dB_Coupled_dB.CSV',13, 213); [Freq,PM_Coupling_Phase] = importfile('C10dB_Coupled_Phase.CSV',13, 213); [Freq,PM_Through_dB] = importfile('C10dB_Through_dB.CSV',13, 213); [Freq,PM_Through_Phase] = importfile('C10dB_Through_Phase.CSV',13, 213);
% % Switch [Freq,P1_SW_dB] = importfile('SW_P1_dB.CSV',13, 213); [Freq,P1_SW_Phase] = importfile('SW_P1_Phase.CSV',13, 213); [Freq,P2_SW_dB] = importfile('SW_P2_dB.CSV',13, 213); [Freq,P2_SW_Phase] = importfile('SW_P2_Phase.CSV',13, 213);
88 % % Narda Couplers [Freq,P1_Coupling_dB] = importfile('42227_Coupled_dB.CSV',13, 213); [Freq,P1_Coupling_Phase] = importfile('42227_Coupled_Phase.CSV',13, 213); [Freq,P1_Through_dB] = importfile('42227_Through_dB.CSV',13, 213); [Freq,P1_Through_Phase] = importfile('42227_Through_Phase.CSV',13, 213);
[Freq,P2_Coupling_dB] = importfile('42228_Coupled_dB.CSV',13, 213); [Freq,P2_Coupling_Phase] = importfile('42228_Coupled_Phase.CSV',13, 213); [Freq,P2_Through_dB] = importfile('42228_Through_dB.CSV',13, 213); [Freq,P2_Through_Phase] = importfile('42228_Through_Phase.CSV',13, 213);
% % Output Attenuation % % N.B. Consider cables attenuation too if used % 40 dB Attenuator [Freq,OutAtt] = importfile('A40dB_dB.CSV',13, 213); % [Freq,OutAtt_Phase] = importfile('A40dB_Phase.CSV',13, 213); % 20 dB Attenuator % [Freq,OutAtt] = importfile('A20dB_dB.CSV',13, 213);
% No Attenuator % OutAtt=zeros(length(OutAtt),1);
% Output Coupler [Freq,OutCoup] = importfile('C20dB_Through_dB.CSV',13, 213); OutAtt = OutAtt + OutCoup;
Freq = Freq*1e-6; Freq_min = Freq(1); Freq_max = Freq(length(Freq)); % % Interpolate with MHz Step specified at the start of the file freq = Freq_min:Step:Freq_max; % zoomed frequency vector for interpolation freq = freq.'; % transpose
Pathes Phase Imbalance (Input)
% % PA IN1toRX phase P1_Phase = unwrap(Cable_Phase, 180) + unwrap(PM_Through_Phase, 180) +... unwrap(P1_SW_Phase, 180) +... unwrap(P1_Coupling_Phase, 180) - unwrap(P1_Through_Phase, 180); % % PA IN2toRX phase P2_Phase = unwrap(Cable_Phase, 180) + unwrap(PM_Through_Phase, 180) +... unwrap(P2_SW_Phase, 180) +... unwrap(P2_Coupling_Phase, 180) - unwrap(P2_Through_Phase, 180); Phase_Imbalance = P2_Phase - P1_Phase; % (P1 is the arbitrary reference) SPI = smooth(Phase_Imbalance,0.1,'rloess'); % Smoothed Phase Imbalance % rloess is suitbale because it has a filter-like property... Inter_SPI = spline(Freq,SPI,freq); % Interpolated Smoothed Phase Imbalance
% Test individually smoothed phases (heavy loss of info) % SP1 = smooth(P1_Phase,0.1,'rloess'); % SP2 = smooth(P2_Phase,0.1,'rloess'); % iSP = SP1 - SP2;
89 D Code Samples
figure % plot(Freq, P1_Phase); % plot(Freq, wrapTo360(P1_Phase)) % equi to mod(P1_Phase,360) % plot(Freq, P1_Phase,Freq, P2_Phase) % plot(Freq, SPI); % plot(Freq, Phase_Imbalance, Freq, SPI); % plot(Freq, Phase_Imbalance, Freq, SPI, Freq, iSP); % plot(Freq,Phase_Imbalance,Freq,SPI,freq,Inter_SPI); plot(Freq,SPI,freq,Inter_SPI,'LineWidth',1.5);
grid on; xlabel('Frequency (MHz)'); ylabel('Phase Imbalance (°)');
save('PathesPhaseImbalance.mat','freq','Inter_SPI');
Pathes Loss Imbalance (Input)
% % PA IN1toPM loss P1_Through = PM_Coupling_dB + P1_SW_dB + P1_Coupling_dB - P1_Through_dB; P1_Loss = -P1_Through; Inter_P1_Loss = spline(Freq,P1_Loss,freq); % Interpolated Path1 Loss % PA IN2toPM loss P2_Through = PM_Coupling_dB + P2_SW_dB + P2_Coupling_dB - P2_Through_dB; P2_Loss = -P2_Through; Inter_P2_Loss = spline(Freq,P2_Loss,freq); % Interpolated Path2 Loss
Loss_Imbalance = P2_Loss - P1_Loss; % (P1 is the arbitrary reference) SLI = smooth(Loss_Imbalance,0.1,'rloess'); % Smoothed Loss Imbalance % SLI = smooth(Loss_Imbalance,5); % Smoothed Loss Imbalance Inter_SLI = spline(Freq,SLI,freq); % Interpolated Smoothed Loss Imbalance
figure
% plot(Freq,P1_Loss,Freq,P2_Loss); % plot(Freq,Loss_Imbalance); % plot(Freq,Loss_Imbalance,Freq,SLI); % plot(Freq, SLI); plot(Freq,Loss_Imbalance,Freq,SLI,freq,Inter_SLI,'LineWidth',1.5);
grid on; xlabel('Frequency (MHz)'); ylabel('Loss Imbalance (dB)');
Output Attenuation
Output_Loss = -OutAtt; SOL = smooth(Output_Loss,0.1,'rloess'); % Smoothed Output Loss Inter_SOL = spline(Freq,SOL,freq); % Interpolated Smoothed Output Loss
90 figure plot(Freq,Output_Loss,Freq,SOL,freq,Inter_SOL,'LineWidth',1.5); grid on; xlabel('Frequency (MHz)'); ylabel('Output Attenuation (dB)'); save('PathesLosses.mat','freq','Inter_P1_Loss',... 'Inter_P2_Loss','Inter_SLI','Inter_SOL');
Other Smoothing/Filtering Options
% % % figure % % % f=fit(Freq,Mag_Imbalance,'smoothingspline'); % % % p = polyfit(Freq,Mag_Imbalance,6) % % % g = polyval(p,Freq); % % % % plot(f,cdate,pop) % % % plot(f,Freq,Mag_Imbalance) % % % figure % % % plot(Freq,g,Freq,Mag_Imbalance)
Published with MATLAB® R2013a
91 D Code Samples
% NSN - RF Predevelopment % Zeid Abou-Chahine
% Initializes and configures setup for outphasing measurements
clc close all clear all
pause on
% pause(n) % pause n seconds % num2str() % str2num('') or str2double('') % latter is faster but restricted to scalar not array of scalars % freq = 2140e6; % strcat('FREQ ',num2str(freq)) does not preserve the space % horzcat('FREQ ',num2str(freq))
Initialize FPGA
disp('Switch SG ON.') disp('Switch GAIA board ON.') disp('Switch DAC board ON.') disp('Wait for GAIA complete bootup (~6.3A SS current).') disp('Type return once done.') keyboard
startup_ledaNew; pause(0.5); disp('Connection with GAIA established'); disp('Initializing board...'); gpb.initBoard; disp('Board is ready'); pause(0.5);
Measurement Conditions and Initial Settings
global T_ON; global T; global cap_mode; global data_mode; global RF; global x_Sinus1; global x_Sinus2; global VF1; global VF2; global VF_Safety; global TrigS; %INT1 or INT2
92 T_ON = 5e-6; % (s) T = 250e-6; % (s) cap_mode = 0; % 0 -> capture TX DPD_out and PDRX data data_mode = 6; % JEDEC ADC 4 RF = 2120; % (MHz) VF1 = 0.02; VF2 = 0.02; TrigS = 'INT1'; % Default setting for PM trigger source (output)
VF_Safety = 0.5; % (1 upper limit results in an error from GAIA anyway) % level should be determined apriori manually. % depends on drivers/predrivers
Ig = 0.05; % (A) limit
Vd_Sumitomo = 50; % (V) Vd_Cree = 38; % (V) Vd = Vd_Cree; Id = 2.5; % (A) limit
V_Driver = 5; % (V) I_Driver = 5; % (A)
V_Fan = 15; % (V) I_Fan = 0.3; % (A) limit
I_SW = 0.05; % (A) limit
Load Calibration Files into MATLAB
% Generate pathes calibration look up tables if needed % Gen_Cal_Tables % (Concerned variables should be set to global in the % original code) load PathesLosses.mat; load PathesPhaseImbalance.mat;
Connect Instruments
% AWG = connectZInstrument('AWG'); SG1 = connectZInstrument('SG1'); PS1 = connectZInstrument('PS1'); PS2 = connectZInstrument('PS2'); PS3 = connectZInstrument('PS3'); SPS = connectZInstrument('SPS'); PM = connectZInstrument('PM'); MM = connectZInstrument('MM'); SA = EQUIPMENT.FSQ;
PS3.Display.Text = 'BISMILLAH';
93 D Code Samples
pause(3) invoke(PS3.Display, 'Clear');
Configure SG1 (In case not manually set)
% Supply ref osc to GAIA Configure_SG(SG1);
Configure MM
% Use the Range property to specify the expected value of the input signal. % Ranges: 10 mA, 100 mA, 1 A, 3 A MM.Dccurrent.Range = 3; MM.Function = 'Agilent34401FunctionDCCurrent'; % MM.Math.Function = 'Agilent34401MathNull'; % Default Setting % MM.Math.Function = 'Agilent34401MathAverage'; % MM.Math.Enabled = 'on'; % A = invoke(MM.Measurement, 'Read', 1); % waiting time in ms. % B = invoke(MM.Measurement, 'Read', 1); % waiting time in ms. % C = invoke(MM.Measurement, 'Read', 1); % waiting time in ms. % MM.Math.Average; % Automatically Average will be (A+B+C)/3 given Enabled % MM.Math.Count % MM.Math.Enabled = 'off'; % invoke(MM.Display, 'settext', 'BISMILLAH')
if (invoke(MM.Utility, 'ErrorQuery') ~= 0) disp('MM error'); end
Configure PS2
% Driver and FS Gate (Vg)
% PS2.init; invoke(PS2.Output1, 'ApplyVoltageCurrent', 0, 0); % Driver signal invoke(PS2.Output2, 'ApplyVoltageCurrent', V_Fan, I_Fan); % Fan signal invoke(PS2.Output3, 'ApplyVoltageCurrent', -5, Ig); % Safety Vg Signal - Always negative PS2.Outputs.Enabled = 'on'; pause(0.5);
invoke(PS2.Output1, 'ApplyVoltageCurrent', V_Driver, I_Driver); % Driver signal pause(1);
Configure PS3
% Turn ON SW and select Path1 as default
% PS3.init; invoke(PS3.Output1, 'ApplyVoltageCurrent', 0, I_SW); % 0V Path1 - 5V Path2
94 invoke(PS3.Output2, 'ApplyVoltageCurrent', 5, I_SW); invoke(PS3.Output3, 'ApplyVoltageCurrent', -5, I_SW); % Always negative PS3.Outputs.Enabled = 'on';
Configure System Power Supply
% FS Drain (Vd)
SPS.voltage = Vd; SPS.current = Id; % current limit SPS.outp = 'ON'; % % alpha = SPS.power % read power
Generate and Send Test Signals
% Pulsed [x_Sinus1, x_Sinus2] = Sinus_Pulsed(RF,T_ON,T);
% CW % [x_Sinus1, x_Sinus2] = Sinus_Pulsed(RF,T_ON,T_ON); gpb.sendTxData2(x_Sinus1*VF1,x_Sinus2*VF2);
LOs Compensation load DACs.mat; gpb.setSPI('AD9122_1',{[hex2dec('1B'),hex2dec('60')]}); % Activate DC offsets gpb.setSPI('AD9122_2',{[hex2dec('1B'),hex2dec('60')]}); % Activate DC offsets AD9122_LO_feedthrough_compensation(gpb,DAC1,DAC2); pause(3);
PS3.Output1.VoltageLevel = 0; %0V Path1 - 5V Path2 pause(1); [DAC1,DAC2,LO_Suppression] = Suppress_LO(gpb,SA,DAC1,DAC2,1,1); disp(horzcat('TX1 LO Suppression = ',num2str(LO_Suppression),' dB')); % [DAC1,DAC2,LO_Suppression] = Suppress_LO_RX(gpb,DAC1,DAC2,1); % disp(horzcat('TX1 LO Suppression = ',num2str(LO_Suppression)));
PS3.Output1.VoltageLevel = 5; %0V Path1 - 5V Path2 pause(1); [DAC1,DAC2,LO_Suppression] = Suppress_LO(gpb,SA,DAC1,DAC2,2,1); disp(horzcat('TX2 LO Suppression = ',num2str(LO_Suppression),' dB')); % [DAC1,DAC2,LO_Suppression] = Suppress_LO_RX(gpb,DAC1,DAC2,2); % disp(horzcat('TX2 LO Suppression = ',num2str(LO_Suppression))); save('DACs','DAC1','DAC2');
95 D Code Samples
Calibrate PM
gpb.sendTxData2(x_Sinus1*0,x_Sinus2*0); pause(5); Configure_PM(PM,1,1,RF,T_ON); % PM,Z,CAL,f,T_ON pause(1);
ReSend Test Signals
gpb.sendTxData2(x_Sinus1*VF1,x_Sinus2*VF2); pause(3); % Adjust_Pins(gpb,PS3,PM,15,15); % Adjust level to a starting low value
Define Colors
Violet = [127/255 16/255 162/255]; Orange = [255/255 175/255 0/255]; Yellow = [255/255 211/255 8/255]; Red = [175/255 0/255 51/255]; Green = [52/255 195/255 51/255]; Gray_L = [104/255 113/255 122/255]; Gray_M = [163/255 166/255 173/255]; Gray_S = [234/255 234/255 234/255];
Color = [Violet; Orange; Yellow; Red; Green; Gray_L; Gray_M; Gray_S];
Published with MATLAB® R2013a
96 function [DAC1,DAC2,LO_Suppression] = Suppress_LO_RX(gpb,DAC1,DAC2,I)
% NSN - RF Predevelopment % Zeid Abou-Chahine
% This function runs an automatic adjustment algorithm for finding the DACs DC offsets % for LO compensation. It is based on the gradient method. % The DACs are updated with the found complex DAC values.
% Inputs: % gpb board identifier % SA Spectrum analyzer identifier % DAC1 complex initial value for TX1 LO compensation via adjusting DC offsets on path1 % DAC2 complex initial value for TX2 LO compensation via adjusting DC offsets on path2 % I path to be compensated (either 1 or 2); The other path's (2 or 1) DAC % value is kept untouched.
% Outputs % DAC1 updated complex value % DAC2 updated complex value % LO_Suppression The amount of suppression achieved in dB on the selected path 'I' global x_Sinus1; global x_Sinus2; global cap_mode; global data_mode;
% close all
% 1b named Datapath control % DatapC = '64'; % DatapC = hex2dec(DatapC); % DatapC = dec2bin(DatapC) % DatapC = str2num(DatapC) % DatapC = bitor(DatapC, 00000100) gpb.setSPI('AD9122_1',{[hex2dec('1B'),hex2dec('60')]}) % Activate DC offsets gpb.setSPI('AD9122_2',{[hex2dec('1B'),hex2dec('60')]}) % Activate DC offsets % gpb.setSPI('AD9122_1',{[hex2dec('1B'),hex2dec('64')]}) % Bypass DC offsets
TX_LO_Abstand = abs((gpb.config.fFBLO - gpb.config.fTXLO)*1e-6); if I == 1 ProgDACsCommand = 'AD9122_LO_feedthrough_compensation(gpb,DAC1*polars(1)*exp(1i*pi/180*polars(2)),DAC2)'; disp('TX1 LO suppression running...'); N = length(x_Sinus1); elseif I == 2 ProgDACsCommand =
97 D Code Samples
'AD9122_LO_feedthrough_compensation(gpb,DAC1,DAC2*polars(1)*exp(1i*pi/180*polars(2)))'; disp('TX2 LO suppression running...'); N = length(x_Sinus2); end
Violet = [127/255 16/255 162/255]; Orange = [255/255 175/255 0/255]; Yellow = [255/255 211/255 8/255]; Red = [175/255 0/255 51/255]; Green = [52/255 195/255 51/255]; Gray_L = [104/255 113/255 122/255]; Gray_M = [163/255 166/255 173/255]; Gray_S = [234/255 234/255 234/255];
Color = [Violet; Orange; Yellow; Red; Green; Gray_L; Gray_M; Gray_S];
TraceC = Yellow; AxisC = Yellow; PlotBack = 'black'; FigBack = 'black'; FS = 16; LW = 1.4;
% TraceC = Yellow; % AxisC = Gray_L; % PlotBack = 'black'; % FigBack = 'black'; % FS = 16; % LW = 1.4; FPS = 5; %frames per second for video recording
Capture Settings Read SA
scrsz = get(0,'ScreenSize'); figure('Renderer','zbuffer','Position',[scrsz(3)/4 scrsz(4)/3 60*16 60*9]) % figure('Renderer','OpenGL') results in a prob with the box on set(gcf, 'Color',FigBack) y_tilde = zeros(N,1); GAIA_RAM = gpb.fetchSignals(N,cap_mode,'SYNC',data_mode); y_tilde = y_tilde + GAIA_RAM.RxB2; clear GAIA_RAM ampdb(y_tilde(1:2:end), gpb.config.fTXDACNCO*1e-6); LinePlots = get(gca, 'Children'); set(LinePlots,'Color',TraceC,'LineWidth',LW); h=get(gca, 'children'); f=get(h, 'XData'); dB=get(h, 'YData');
98 TXLOind = find(f>=TX_LO_Abstand,1,'first'); P0_LO = dB(TXLOind) set(gca,'Color',PlotBack); set(gca,'FontSize',FS) grid on set(gca,'Xcolor',AxisC); set(gca,'Ycolor',AxisC); box on grid on xlim([f(1) f(end)]) ylim([floor(min(dB)/5)*5 ceil(max(dB)/5)*5]) % xlabel('RX Abstand (MHz)','FontSize',FS) % ylabel('dB','FontSize',FS) set(gca,'NextPlot','replaceChildren','Visible','on');
% Prepare for recording % vidObj = VideoWriter('LO_Supression_DACs_advUser_Test','MPEG-4'); vidObj = VideoWriter(['LO_Supression_DAC',num2str(I),'_advUser'],'Motion JPEG AVI'); vidObj.Quality = 100; vidObj.FrameRate = FPS; open(vidObj); writeVideo(vidObj, getframe(gcf)); % take first snapshot
DAC Compensation
Polars = []; P_LO = []; polars = [1 0]; % recommended start value of 1 0 corresponds to no modification of DACs % step = [0.2 4]; % initial step width; set after P0_LO assessment step_reduction = [0.6 0.6]; % reduction factors of step width % step_reduction = [0.5 0.5]; % reduction factors of step width % step_min = [0.001 0.05]; % minimum step width % step_min = [0.0005 0.025]; % minimum step width % step_min = [0.0005 0.01]; % minimum step width step_min = [0.0005 0.005]; % minimum step width
Samps = 1; % Uncertainty margin (+-Samps) within +-10 Samples around gpb.config.fTXLO n_max = 50; % Maxim iterations for individual Mag/Phase search M = 3; % number of gradient loop for coefficient set
LO_Threshold = 20; disp(['LO target: ',num2str(LO_Threshold)]);
LO_Index = TXLOind+[-Samps:Samps]; %fixed LO index(ces); Relying % on max to find the LO in low LO powers might return a noise index (in case LO is already % compensated). Ideally Samps should be 0, set 1 for allowing some uncertainty;
Polars = [Polars; 1 0];
99 D Code Samples
P_LO = [P_LO P0_LO];
if (P0_LO < LO_Threshold) disp(['LO below noise level of ',num2str(LO_Threshold)]); LO_Suppression = 0; close(gcf); return; elseif (P0_LO < LO_Threshold + 10) step = [0.02 0.05]; % initial step width elseif (P0_LO < LO_Threshold + 20) step = [0.2 0.5]; % initial step width elseif (P0_LO < LO_Threshold + 30) step = [0.5 2]; % initial step width else step = [1 4]; % initial step width end
j = 1;
% gradient method for m=1:M for coeff = [1 2] n=1; slope_change = 0;
% optimise coefficients for n=1:n_max; j = j+1; polars(coeff) = polars(coeff)+step(coeff); Polars(j,:) = polars; eval(ProgDACsCommand); disp('Plotting SA...') pause(0.5)
y_tilde = zeros(N,1); GAIA_RAM = gpb.fetchSignals(N,cap_mode,'SYNC',data_mode); y_tilde = y_tilde + GAIA_RAM.RxB2; clear GAIA_RAM; ampdb(y_tilde(1:2:end), gpb.config.fTXDACNCO*1e-6); LinePlots = get(gca, 'Children'); set(LinePlots,'Color',TraceC,'LineWidth',LW); writeVideo(vidObj, getframe(gcf));
h=get(gca, 'children'); % f=get(h, 'XData'); dB=get(h, 'YData'); P_LO(j) = max(dB(LO_Index));
[P_LO.' Polars]
if(P_LO(j)>P_LO(j-1)) step(coeff) = step(coeff)*-step_reduction(coeff); if (abs(step(coeff)) < abs(step_min(coeff)))
100 step(coeff) = sign(step(coeff))*abs(step_min(coeff)); end slope_change = slope_change+1; end
if(slope_change > 2) [~,ind_min]=min(P_LO); polars = Polars(ind_min,:); % polars=Polars(j-1,:); % step(coeff) = -step(coeff); % if j>10 % [~,ind_min]=min(P_LO(end-4:end)); % polars = Polars(end-4+ind_min-1,:); % end break; end
if (P_LO(j) < (LO_Threshold-5)) disp(['LO below ',num2str(LO_Threshold-5)]); if I == 1 DAC1 = DAC1*polars(1)*exp(1i*pi/180*polars(2)); elseif I == 2 DAC2 = DAC2*polars(1)*exp(1i*pi/180*polars(2)); end LO_Suppression = P_LO(1) - P_LO(j); % close(gcf) close(vidObj); return; end end end end
[P_LO_min,ind_min]=min(P_LO); if (ind_min ~= length(P_LO)) j = j+1; P_LO(j) = P_LO_min; polars = Polars(ind_min,:); Polars(j,:) = polars; end if I == 1 DAC1 = DAC1*polars(1)*exp(1i*pi/180*polars(2)); elseif I == 2 DAC2 = DAC2*polars(1)*exp(1i*pi/180*polars(2)); end
AD9122_LO_feedthrough_compensation(gpb,DAC1,DAC2); pause(1) y_tilde = zeros(N,1); GAIA_RAM = gpb.fetchSignals(N,cap_mode,'SYNC',data_mode); y_tilde = y_tilde + GAIA_RAM.RxB2;
101 D Code Samples
clear GAIA_RAM; ampdb(y_tilde(1:2:end), gpb.config.fTXDACNCO*1e-6); LinePlots = get(gca, 'Children'); set(LinePlots,'Color',TraceC,'LineWidth',LW); writeVideo(vidObj, getframe(gcf));
h=get(gca, 'children'); dB=get(h, 'YData'); P_LO(j) = max(dB(LO_Index));
[P_LO.' Polars] % LO_Suppression = P_LO(1) - P_LO(end); % close(gcf) close(vidObj);
end
102 Abbreviations
ACLR Adjacent Channel Leakage power Ratio
ADS Advanced Design System
AM Amplitude Modulated
AMO Asymmetric Multilevel Outphasing
BFM Baliga’s Figure-of-Merit
BTS Base Transceiver Station
BW Bandwidth
CAD Computer Aided Design
CDF Cumulative Distribution Function
DPD Digital Predistortion
DUT Device Under Test
EVM Error Vector Magnitude
ET Envelope Tracking
GaAs Gallium Arsenide
GaN Gallium Nitride
HEMT High Electron Mobility Transistor
IAMO Input Amplitude Modulated Outphasing
JFM Johnson’s Figure-of-Merit
LINC Linear Amplification with Nonlinear Components
103 Abbreviations
LO Local Oscillator
LP Load-Pull
LS Large Signal
LUT Look-Up Table
MQAM Multiquadrature Amplitude Modulation
NA Network Analyzer
PA Power Amplifier
PAR Peak-to-Average power Ratio
PBO Power Back-Off
PDF Probability Density Function
PM Phase Modulated
RCA Radio Corporation of America
SA Spectrum Analyzer
SCS Signal Component Separator
Si Silicon
W-CDMA Wideband-Code Division Multiple Access
104 List of Figures
1.1 Global mobile data [6]...... 2 1.2 High-end devices multiply traffic [6]...... 2
2.1 Outphasing PA architecture...... 6 2.2 Outphasing with Wilkinson combiner...... 7 2.3 Efficiency assessment circuit schematic...... 11 ¥ ¥ 2.4 Wilkinson’s η assessment: V1 50 V, θ1 70 and θ2 30 ...... 11 2.5 Outphasing with Chireix combiner...... 15 2.6 Uncompensated (left) vs. compensated Chireix combiner impedances loci.. 16
2.7 Impedance loci sets for different θc and ZL settings. The arrows indicate ¥ orientations of increasing (left) θc and (right) ZL, respectively from 10 to ¥ ¥ 30 in 5 steps for ZL 50 Ω, and from 10 Ω to 50 Ω in 10 Ω steps for ¥ θc 15 ...... 16 2.8 Modulated (a) real and (b) imaginary parts of the compensated Chireix
impedance Z1 for different compensation angle settings; ZL 50 Ω..... 17 2.9 Modulated (a) real and (b) imaginary parts of the compensated Chireix ¥ impedance Z1 for different ZL settings; θc 15 ...... 17 2.10 Outphasing efficiencies assuming ideal class-B PA blocks...... 18
3.1 A 1986 VW Golf GTI fuel consumption [15, 16]...... 20 3.2 (a) A realized class-E GaN HEMT (b) measured at 2170 MHz...... 20 3.3 A classification of some PA architectures...... 21 3.4 Turbocharged engine [22]...... 22 3.5 (a) Outphasing with energy recovery using (b) a bridge rectifier...... 22 3.6 Outphasing with energy recovery assuming ideal class-B PA blocks..... 23 3.7 Asymmetric Outphasing...... 24
3.8 Optimal two levels (V0 50 V)...... 26 3.9 2-Level AMO average efficiency assuming ideal class-B PA blocks...... 26 3.10 LS simulations showing (a) PAE curves that correspond to different input power levels while having θ swept for each and (b) emerging loci sets.... 27
105 List of Figures
3.11 A 7.5 dB PAR W-CDMA (a) IQ constellation and (b) distribution..... 28
4.1 Voltage applied to the grid controls plate (anode) current [41]...... 31 4.2 (a) 2 ¢ 31.5 W Chireix’s maximum power capability vs. the design param-
eter θc and (b) the generic defined degradation factor κ...... 34 4.3 Packaged GaN HEMT simplified small-signal equivalent circuit model.... 36 4.4 Y representation of the intrinsic HEMT in (a) ON and (b) OFF states... 36
4.5 Cout stemming from simplified circuit analysis for the harmonically shorted case (a) as a function of time and (b) as a function of variable capacitor (or drain) voltage for the parameters given in Table 4.2...... 40
4.6 Parametric Cout’s DC and fundamental components for the simplified har-
monically shorted case (a) with respect to VDC and (b) with respect to V0 with the fixed parameter values as given in Table 4.2...... 41
4.7 Extracted (dotted) and fitted (colored surface) CGH27030F’s Cout...... 41
4.8 (a) Real time fitted Cout for different V0 values and (b) its spectral compo- nents...... 42
4.9 Cout’s first three spectral components as a function of the parameter V0... 43
4.10 Cout’s fundamental component for the nonharmonic design case...... 43 ¥ ¥ 4.11 IAMO PAE LS simulations with (a) θc 15 and (b) θc 30 designs... 44 4.12 (a) Blocks inserted between the Chireix ideal current sources and Chireix combiner and (b) transformed loci at die’s plane...... 45 4.13 (a) Calculated and (b) measured (normalized) bandwidth expansion of the individual outphased signals from a 5 MHz W-CDMA signal...... 46 4.14 (a) Calculated and (b) measured (normalized) bandwidth expansion of the individual outphased signals from a 20 MHz W-CDMA signal...... 47 4.15 (a) Instantaneous frequency shift for the individual outphased signals from a 5 MHz W-CDMA signal and (b) its zoomed view...... 47 4.16 Preserved outphased data as a function of the PA cores’ supported BW... 48 4.17 Outphased signals BW truncation virtual test setup...... 49 4.18 Example of the outphasing signal corresponding to a 20 MHz 2-Carrier W- CDMA input, truncated in MATLAB to (a) 15 MHz and (b) 100 MHz... 50
4.19 EVM of s1Filtered with reference to s1 as a function of the bandpass filter’s BW for three W-CDMA input signal configurations...... 50
4.20 (a) EVM of sL with reference to s as a function of the bandpass filter’s BW for three W-CDMA input signal configurations and (b) its zoomed view.. 50
4.21 The PAR for s1Filtered as a function of the bandpass filter BW...... 52
5.1 Path 1 of the practical Chireix combiner for the harmonic case...... 56
106 List of Figures
5.2 Package plane impedance loci on the Smith-chart at the fundamental (left) and 2nd harmonic (right ¡ renormalized to 5 Ω) for a nonharmonic Chireix ¥ combiner with θc 15 as a function of θ. The index i in Gammai corre- sponds to the device index, 1 being the device with the leading outphased signal...... 57 5.3 Package plane impedance loci on the Smith-chart at the fundamental (left) nd ¥ and 2 harmonic (right) for a harmonic Chireix combiner with θc 15 as a function of θ. The index i in Gammai corresponds to the device index, 1 being the device with the leading outphased signal...... 57 5.4 (a) Simulated Chireix PA PAE and (b) 2nd harmonic drain voltage magni- ¥ tude using LS models (θc 15 )...... 58 5.5 Layout of the Chireix PA with harmonic combiner...... 59 5.6 (a) Driver stage circuitry built for separate testing and (b) realized Chireix PA with harmonic combiner on a 15 ¢ 12 cm2 board...... 59
6.1 Basic outphasing measurements setup...... 62 6.2 (a) Digital setup block diagram and (b) photo...... 62 6.3 (a) Losses (b) and delay imbalances relative to path 1...... 63 6.4 (a) Driver module and (b) small-signal gains...... 64 6.5 (a) The used switch and (b) its calibration setup...... 64 6.6 (a) 3 dB combiner and (b) outphasing measurement test...... 65 6.7 (a) Synchronized pulsed signals and (b) a zoomed view...... 65 6.8 (a) Spectrum seen without and (b) with LO suppression around 2.3 GHz.. 66 6.9 Harmonic Chireix outphasing at 2.14 GHz...... 67 6.10 Measured efficiency at different PBO levels vs frequency...... 67 6.11 Measured efficiency for several drain supply voltages (RF 2.12 GHz and
P in 35 dBm)...... 67 6.12 (a) Measured outphasing dynamic range as θ is swept and (b) corresponding efficiency...... 68 6.13 Amplified signal’s spectrum ¡ One carrier...... 69 6.14 Amplified signal’s spectrum ¡ Two carrier...... 69
7.1 Simulated effect of a dedicated 2nd harmonic termination at the input sides of the Chireix PA...... 72 7.2 Simulated effect of smaller compensation angles Chireix designs...... 72
7.3 Chireix architecture LP: ZL is varied from 15 Ω to 30 Ω in steps of 1 Ω and
Lcomp varied according to assumed Couts between 1.7 pF and 3.7 pF in steps
of 0.1 pF. The x-axis corresponds to Pout (dBm) and the y-axis to PAE (%). 73
107 List of Figures
7.4 Chireix architecture LP: ZL is varied from 20 Ω to 25 Ω in steps of 0.5 Ω
and Lcomp varied according to assumed Couts between 2.9 pF and 3.5 pF in
steps of 0.1 pF. The x-axis corresponds to Pout (dBm) and the y-axis to PAE (%)...... 74 7.5 Mixed-mode outphasing angle functions...... 75 7.6 Summary...... 77
A.1 Transmission Line...... 81
B.1 (a) PDFs and (b) CDFs corresponding to different Rayleigh distribution modes...... 83
108 List of Tables
3.1 Outphasing variants comparison with a 7.5 dB PAR W-CDMA signal.... 29
4.1 Material properties comparison [42, 43]...... 32 4.2 Parameters reflecting an exemplary 30 W GaN transistor...... 40
4.3 Empirical Cout constants in (4.20) for the CGH27030F HEMT...... 42 4.4 Design parameters using the CGH27030F HEMT...... 42 4.5 Peaks distances comparison for two different designs...... 45
6.1 Chireix PA measurement results...... 69
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118 Authored and Co-Authored Publications
[1] Z. Abou-Chahine, T. Felgentreff, G. Fischer, and R. Weigel, “An input ampli- tude modulated harmonic outphasing PA,” in Mediterranean Microwave Symposium (MMS), 2013 13th, Sept 2013, pp. 1–4. Best student paper award.
[2] Z. Abou-Chahine, T. Felgentreff, G. Fischer, and R. Weigel, “Efficiency analysis of the asymmetric 2-level outphasing PA with Rayleigh enveloped signals,” in Power Amplifiers for Wireless and Radio Applications (PAWR), 2012 IEEE Topical Con- ference on, Jan 2012, pp. 85–88. Best student paper award.
[3] C. Musolff, M. Kamper, Z. Abou-Chahine, and G. Fischer, “Linear and efficient Doherty PA revisited,” Microwave Magazine, IEEE, vol. 15, no. 1, pp. 73–79, Jan 2014. Winning design of the MTT’s high efficiency PA student contest.
[4] C. Musolff, M. Kamper, Z. Abou-Chahine, and G. Fischer, “A linear and efficient Doherty PA at 3.5 GHz,” Microwave Magazine, IEEE, vol. 14, no. 1, pp. 95–101, Jan 2013. Winning design of the MTT’s high efficiency PA student contest.
Patent Submission
[1] Z. Abou-Chahine and T. Felgentreff, “Input amplitude modulated outphasing with an unmatched combiner,” International Patent Application WO 2014/075736 A1, May 22, 2014.
119