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Litex: an Open-Source Soc Builder and Library Based on Migen Python DSL

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Litex: an Open-Source Soc Builder and Library Based on Migen Python DSL LiteX: an open-source SoC builder and library based on Migen Python DSL Florent Kermarrec Sebastien´ Bourdeauducq Jean-Christophe Le Lann and Hannah Badier Enjoy-Digital, Landivisiau, France M-Labs, Hong-Kong ENSTA Bretagne, Brest and Lab-STICC UMR fl[email protected] [email protected] [email protected] Abstract—LiteX [1] is a GitHub-hosted SoC builder / IP A. EDA renewal through DSLs and platform-based design library and utilities that can be used to create SoCs and full A recent trend, however, shows that several new HDLs are FPGA designs. Besides being open-source and BSD licensed, its originality lies in the fact that its IP components are entirely starting to emerge. Their common characteristic is that they are described using Migen Python internal DSL, which simplifies its essentially internal Domain Specific Languages (DSLs). These design in depth. LiteX already supports various softcores CPUs languages –sometimes called “embedded DSLs”– are hosted and essential peripherals, with no dependencies on proprietary by a mainstream programming language. No matter which IP blocks or generators. This paper provides an overview of host language is used, embedding a DSL in a mainstream LiteX: two real SoC designs on FPGA are presented. They both leverage the LiteX approach in terms of design entry, libraries programming language provides several benefits: comfort, and integration capabilities. The first one is based on RISC-V smooth learning curve, access to host language libraries and core, while the second is based on a LM32 core. In the second ecosystem. Complex compiler technologies or specific parsers use case, we further demonstrate the use of a fully open-source are not necessary, which significantly reduces the amount of toolchain coupled with LiteX. work required compared to the effort needed to create a brand- Index Terms—open-source, SoC, Python, DSL, FPGA, IP library new language. The design of such internal DSLs is based on efficiently mapping domain-specific concepts to the host language syntax. I. INTRODUCTION The renewal of HDLs, based on embedded DSLs like Electronic Design Automation (EDA) plays a central role in Chisel/SpinalHDL, is also encouraged by the advent of RISC- the advent of all the electronic devices we use daily, ranging V platform-based design (PBD). This initiative is intended from small embedded systems to internet-scale infrastructures. to counterbalance the supremacy of ARM in the field of The success of EDA may mainly be attributed to its capability embedded systems, by providing a set of royalty-free soft- to describe semi-conductor devices with tools and languages cores. Such softcores play a central role in platform-based based on robust abstraction layers: transistors, layout, logic, design, which has been defined [3] as “an integration oriented register-transfer level (RTL), behavioral descriptions, etc. design approach emphasizing systematic reuse, for develop- Thanks to these levels of abstraction, engineers do not have to ing complex products based upon platforms and compatible face the entire complexity of the underlying device they are hardware and software virtual components, intended to reduce designing, which makes the design process more constructive development risks, costs and time to market”. This reuse calls and efficient. In this process, Hardware Description Languages for new methodologies: to build complex embedded systems (HDLs), such as Verilog and VHDL, still play a pivotal role. organized around a processor, two ingredients are mandatory. New features that aim at facilitating the designer’s job have The first is abstraction: modern languages are likely to provide been added at a slow pace. This conservative slowness has such characteristics though either object-oriented or functional arXiv:2005.02506v1 [cs.AR] 5 May 2020 left only very little room for newcomers. Among them, Sys- modeling. As clearly stated in the previous definition, the temVerilog has succeeded to emerge as the most natural way to second ingredient is the availability of component libraries. describe and execute complex test benches, while SystemC is B. Objectives of the paper now mainly associated to transaction-level platform modeling. On the contrary, synchronous languages [2], whose formal In this paper, we present LiteX [1], SoC builder and library aspects could have been beneficial to EDA, have not been of IP components described at the RTL level, together with adopted widely in EDA, despite decades of extensive research. various utilities that facilitate the building of complete SoC In the same vein, High-level Synthesis, which calls for C- designs. LiteX resorts to a DSL, written in Python and named based design entry, has not gained the popularity of HDLs Migen. LiteX has been used successfully and on a daily basis yet. Nowadays, classical HDLs, acting as RTL description for several years by Enjoy-Digital [4], a company dedicated languages, still stand as the cornerstone of EDA. to open-source FPGA-based design, in various application domains (multimedia, software defined radio, automotive, etc.) and is progressively being adopted by users around the world. This work is licensed under a “CC BY-NC-SA 4.0” license. The obvious key of this adoption lies both in the very permissive open-source license adopted by LiteX (BSD), and A. Migen FHDL the choice of Python for the RTL descriptions and deployment. Similar to previous cited technologies, Migen FHDL (Frag- LiteX participates in a larger trend that will be discussed in mented Hardware Description Language) allows to describe this paper. and simulate RTL circuits. It is based on a custom Python The rest of the paper is organized as follows. Next Section abstract syntax tree (AST) and can produce synthesizable Ver- makes a short survey of the trend of eDSLs for EDA, and es- ilog. FHDL does not follow the event-driven paradigm of most pecially for RTL design. Section 3 presents Migen FHDL and HDLs, and instead replaces it with notions of synchronous and MiSoC. Section 4 introduces LiteX SoC builder and library. combinatorial statements. In Section 5, a full SoC design on FPGA is exposed and a Thanks to Migen FHDL, highly and easily configurable fully open-source design flow based on LiteX is presented. cores can be designed. Creating a design by writing a Python program raises the level of abstraction, by for example II. RELATED WORK : BENEFITS OF INTERNAL DSLS FOR enabling the use of object-oriented programming or meta- RTL DESIGN programming. The choice of Python in particular, as opposed to other programming languages such as Scala, also gives a Many hardware-oriented embedded DSLs have been pro- clear advantage for Migen adoption: Python is an easy to posed. Among them, SystemC itself can be cited at first. learn and well-known language, already used for many other It was proposed by Liao in [5] (at that time, SystemC was tasks by application engineers, for instance for algorithmic named Scenic). SystemC relies on C++ objects and allows to prototyping. describe hardware systems at various level of abstractions. The The following code example shows how a functional design simulation engine remains event-driven, similar to VHDL and can be implemented in a short, efficient and readable manner: Verilog. It has received a large audience, and has improved since the early paper of Liao to include sophisticated features from migen import * for transaction-level modeling [6], which allows to build mod- from migen.fhdl import verilog els usable by software programmers for early SoC validation. c l a s s Blinker(Module): However, SystemC has not been used fully as RTL entry. d e f i n i t (self, sys c l k freq , period): A DSL that has recently been receiving growing attention is s e l f.led = led = Signal() Chisel [7] and its fork named SpinalHDL. They both strongly ### contribute to the recent renew of RTL design practices. They also take an active part in the advent of RISC-V softcores. toggle = Signal() c o u n t e r p r e l o a d = int(sys c l k f r e q * p e r i o d / 2 ) Chisel initially targets synchronous designs, where the clock counter = Signal(max=counter p r e l o a d + 1) is implicit. The host language is Scala, a multi-paradigm language (object-oriented and functional), with a static typing. s e l f.comb += toggle.eq(counter == 0) s e l f.sync += n Here again, Scala [8] is known for its syntactic flexibility: I f ( t o g g l e , semicolons are optional, any method can be used as an infix led.eq(˜led), operator, etc. These features provide a strong differentiator counter.eq(counter p r e l o a d ) ) . E l s e ( with respect to VHDL for instance, which is known to be ex- counter.eq(counter − 1) tremely verbose. However, the benefits of Scala go far beyond ) the syntax: the type inference mechanism, parameterized types # Create a 10Hz blinker from a 100MHz system clock. and generators are particularly appealing for hardware design. blinker = Blinker(sys c l k freq=100e6, period=1e −1) HardCaml, an OCaml library for designing hardware, shares p r i n t(verilog.convert(blinker , f blinker.led g )) several aspects with Chisel, as OCaml offers many of the same modern multi-paradigm features provided by Scala. Haskell (a pure functional language) has also been used extensively for Listing 1. Blinking LED design example describing hardware: Lava [9], CλaSH [10], [11]. An older approach based on Java for FPGA programming was proposed This design consists of a decrementing counter that toggles in [12]. Furthermore, an interesting approach named MyHDL a one-bit signal whenever it reaches 0. The one-bit signal [13] and based on Python was introduced by Decaluwe in [14].
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