Complementary Metal-Oxide- Semiconductor

Journal of Scientific & Industrial Research Vol. 63, October 2004, pp 795-806

Emerging trends in ultra-miniaturized CMOS (Complementary metal-oxide- semiconductor) transistors, single-electron and molecular-scale devices: A comparative analysis for high-performance computational nanoelectronics

V K Khanna Solid State Devices Division, Central Electronics Engineering Research Institute, Pilani 333 031

The current status and trends of the three ultra-small scale integrated circuit technologies, namely nanoscale CMOS, single- and molecular electronics are comprehensively reviewed. A comparative study is made, pointing out their relative pros and cons for nanoelectronic computing. Crucial aspects of MOS downscaling include, from the physical viewpoint, the infamous short-channel effect caused by drain induced barrier lowering (DIBL), the narrow width effect associated with small channel width, the combined small-geometry effect, and hot-carrier degradation; together with the conflicting requirements of shallow silicided junctions and low junction leakage; random doping fluctuations; ultrathin gate oxide reliability; polysilicon depletion effect; atomic scale roughness at the Si/SiO 2 interface; and high lithographic expenses, on the technological side. For sustaining growth in device density, a possible route for the microelectronics industry is to shift from the traditional field-effect transistor-based paradigm to one based on nanostructures. Single electronics has not been able to bear the envisaged fruits. While prospects of solo single-electron logic are murky, the concept of a mixed single- electron device/FET multi-valued logic and memory appears to be beneficial. But to achieve the ultimate performance, it may be expedient to transform our philosophy fundamentally to start from the molecular level, instead of scaling down old technologies to nanometer level. Molecular electronics appears to be the appropriate approach because the development cost of scaled technologies, and cost-effectiveness of resulting devices is not encouraging. The review seeks to provoke keen interest in these futuristic nanotechnologies.

Keywords : Nanotechnology, Computers, Single-electron transistor, Molecular electronics, Nanocells, Quantum dots IPC Code: Int. Cl. 7: H 01 L 29/00, H 01 L 21/336, H 01 L 27/00

1 Introduction faced by the nanoMOSFET technology, and sheds The computer industry has progressed by leaps and light on the upcoming technologies to maintain the bounds. This phenomenal success is ascribed to the constant pace of progress in this vital sector. constant downsizing of contemporary CMOS devices Investment in terms of development effort and cost and circuitry resulting in lower cost, faster, and denser together with relative economic and technological computers with reduced power consumption and gains expected are the prime factors under enhanced functionality. Consumer’s demand for deliberation. portable battery-operated products has stimulated considerable efforts for exploration of low-voltage 2 Prelude to Switching and Amplifying Devices devices. MOSFETs (Metal-oxide-semiconductor for Nanocomputers field-effect transistors) having decananometer channel To enable the reader to understand the subject and lengths are already mass fabricated while those less appreciate the importance of the issues raised, we than 10 nm have been demonstrated in research begin with an introduction to the switching and environments. Below 10 nm, MOSFETs are close to amplifying devices that constitute the hardware of their basic limits of operation 1, and at this scale, their present-day electronic digital computers. All digital realization is confronted with gigantic physical and computers contain a basic structural unit, ‘the financial constraints. Information technology needs transistor’ which is a device capable of performing high-speed devices. Naturally, alternative approaches two functions: switching and amplification. The state like, single electronics and molecular electronics have of the transistor can be employed to adjust the voltage attracted the attention of researchers all over the on a wire as high or low, designated as binary zero and globe 2. This paper discusses critically the obstacles one on the computer. Further, using a small input ______signal the transistor can control an output signal that is Email: [email protected] several-fold larger than this signal. The switching 796 J SCI IND RES VOL 63 OCTOBER 2004

prevented by limitations of fabrication technology and quantum mechanical laws governing the device operation. As a solution to this problem, two categories of alternative devices to the MOSFET have appeared viz., single-electron transistors and molecular devices.

In the next section, the problems encountered in shrinking MOSFETs are addressed. Then the novel nanoelectronic switching and amplifying devices are described. Although the operating principles of these devices are radically different from those of the MOSFET, these devices retain the terminology of source, drain and gate in the same conceptual roles as the MOSFETs. To acquaint the reader with the terminology of these devices the single-electron transistor 3-10 contains a small island of semiconductor or metal, ranging in size from 5-100 nm. This island is embedded between two narrow walls of some other material or an insulating oxide of the island material. It is said that the island is enclosed between two potential energy barriers.

Electrons confined to islands exhibit two essential quantum mechanical effects: energy quantization and tunneling. These effects control the electron transport in a nanoelectronic device. Quantum mechanics allows the energy of each electron to be one of a finite number of one-electron energy levels. Moreover, when the potential barriers are very thin, ~ 5-10 nm, there exists Fig. 1—(a) Simplified structure of N-channel MOSFET. (b) P- a finite probability for ‘tunneling’ of electrons to move channel and N-channel MOSFETs in an N-well CMOS technology to or from the island, provided there is a vacant state of the same energy on the opposite side. function allows the implementation of logical and The other approach of molecular electronics 11-19 is arithmetic functions in a computer while amplification based on devising molecular structures that can act as permits the transmission of signals within the computer switching elements, and assembling these molecules without attenuation. into the accurate extended structures for computation.

The transistor most commonly used in digital The ability of a single molecule to conduct current computers is the metal-oxide-semiconductor field- was not recognized easily because very constricted effect transistor (MOSFET)[Fig. 1(a)]. In this device, wire structures offer high resistance even if they are current flows from the source terminal to the drain made from good electrical conductors. Chain terminal when the voltage applied to the gate terminal molecules composed of repeating units of aromatic is sufficient to invert the underlying silicon to form a groups with acetylene linkage are known to conduct conducting channel from source to drain. A pair of electric current. They are called molecular wires and complementary devices, one P-channel MOSFET and can be made appreciably long. Incorporating quantum one N-channel MOSFET constituting the wells into molecular structures for confinement of complementary metal-oxide-semiconductor (CMOS) mobile electrons, switching devices can be made. A structure, [Fig. 1(b)], is widely used in digital circuits. quantum well can be embedded in a molecular wire

To augment the capabilities of computers, their by inserting pairs of barrier groups that break the fundamental structural unit, namely the MOSFET, has sequence of conjugated π-orbitals. been made progressively smaller in size resulting in With this brief tutorial, we begin to investigate the ultradense electronic circuits. The MOSFET has now problems encountered in shrinking the MOSFET reached a stage where its further miniaturization will be devices. KHANNA: COMPARATIVE ANALYSIS FOR HIGH-PERFORMANCE COMPUTATIONAL NANOELECTRONICS 797

3 Downscaling of MOS Devices, Significant Probl- when the channel length becomes comparable to the ems and Recourse to Other Approaches source-substrate or drain-substrate depletion depth, Ever since J S Kilby invented and demonstrated the and is caused by the overlapping of the depletion integrated circuit in 1958, the manufacturing of region due to the gate field with the depletion regions semiconductor ICs has continued to grow near the source and drain junctions, terminating the exponentially. In 1965, Gordon Moore, the co-founder built-in fields from source and drain 22 . This of Intel, observed that the number of transistors per unit overlapping decreases the total amount of depleted area in an integrated circuit doubles every 18 months. charge available in the P-substrate to compensate the This observation referred to as the Moore’s law has field applied to the gate. The net result of this charge been corroborated during the past four decades as sharing is that the depletion region below the gate is a integrated circuit complexity has advanced from small- trapezoidal-shaped region instead of the rectangular- scale integration (SSI: active device count 1-100 per shaped volume visualized for easy calculation. chip), through medium-scale integration (MSI: 100- Therefore the charge near the non-parallel sides of the 10 3), large-scale integration (LSI: 10 3-10 4), and very trapezium is subtracted from the bulk charge, large-scale integration (VLSI: 10 4-10 5) to ultra large- accounting for the lower threshold voltage. scale integration (ULSI: 10 5-10 6). This have been The first step towards preventing short channel possible due to the continued reduction of minimum effect is to ensure suitable gate control of the scaled device dimension. Breakthroughs in semiconductor channel by shortening the lateral extension of the device fabrication during the past two decades have junctions by reducing their depth. Thus the pushed the minimum feature sizes down to the source/drain regions comprise two parts, viz. a nanometer region. Driven by the advances in extreme shallow drain/source extension region and a deep ultraviolet lithography, electron-beam lithography and source/drain junction region. Raising the substrate X-ray lithography, epitaxial growth with atomic layer doping level to prevent the lateral extension of the accuracy by molecular beam epitaxy (MBE), and using drain depletion region further alleviates the short- state-of-the-art process technology, miniaturization of channel effect. This produces a significant silicon MOSFET-based integrated circuits have been deterioration of the performance of the transistor intensively pursued for data processing and memory because the carrier mobility in a heavily doped functions. In the past few years, MOSFET dimensions substrate region is drastically reduced. Also the have reached the decananometer scale with dimensions leakage current increases. As a result, a higher off- ranging between 10 to 100nm. Devices with physical state current is obtained, accompanied by a larger gate lengths 40-50 nm are already available. Within the subthreshold swing. A better remedy is to achieve the next 2 to 3 y, 35 nm gate length transistors will be same goal by a vertical doping redistribution with the available for mass manufacturing. The prediction is that the current trend will continue to progress at the same pace with a new technology every 3 y and the minimum feature size scaled down by a factor of approximately 0.7. At 2009, a 70-nm linear dimension CMOS technology will become available. By 2012 the leading edge devices will employ gate lengths of 50 nm with gate oxide thickness ≤ 1.5 nm. It is forecasted that after 2016, the MOSFET will shrink down to nanometer scale when its physical dimensions in a mass production environment will reach 9 nm (ref. 20 and 21). Main problems of MOS scaling along with applicable remedies are enumerated below:

(a) Short -channel Effect The primary effect is the reduction of threshold voltage with the shortening of the channel, which can Fig. 2—Charge sharing between gate and source, and gate and be understood from Fig. 2. It becomes significant drain in a MOSFET 798 J SCI IND RES VOL 63 OCTOBER 2004

help of a retrograde doping profile . The drain source extension regions are built for decreasing the parasitic resistances and pockets or halos are made by ion implantation for increasing the doping concentration below the channel region. Thus the low-concentration region at the surface controls the threshold voltage while the halos assure the short-channel immunity. These pockets are made in such a way that they lie close to the source/drain junctions for averting punchthrough while the channel region with a lighter doping for low threshold voltage remains unaffected. The peak doping concentration in the halo implant must be greater than that required with uniformly Fig. 3—Cross-section of the MOSFET width showing the actual and ideal shapes of depletion regions doped subsurface layer. Although retrograde profiles provide improved carrier mobility, unfortunately the doped region under the field oxide called the channel removal of the dopant from the interfacial channel stop during high-temperature processing steps into the region decreases the threshold voltage, leading to channel region. This encroachment increases the unacceptably high off current. Therefore the density of charge in the channel region near its sides. advantages derived are subject to trade-off between To counteract the effect of this charge, a higher on-state and off-state currents. To illustrate, using a voltage has to be applied for inversion, raising the smaller channel depletion width and a smaller source- threshold voltage. A further increase in threshold drain depletion width reduces short-channel effect. voltage occurs due to the bird’s beak effect . Here, a But a smaller channel depletion width increases the tapering of the oxide, results in extra charge under the subthreshold swing producing either a lower on- oxide structure yielding a higher threshold voltage. current or a higher off-current. Similarly the reduction (c) Small-geometry Effect of source-drain depletion widths by raising the When the channel length and width are substrate doing concentration alters the balance simultaneously reduced the resultant small-geometry between on-current and off-current. structure exhibits not only short-channel and narrow- width effects but shows a combined effect due to the (b) Narrow-width Effect The increase in threshold voltage for narrow coupling of the aforesaid two effects. This joint channel width can be interpreted with reference to manifestation of short-channel and narrow-width effects is referred to as small-geometry effect . Fig. 3. On approaching the edge of the device the contour of the depletion region makes a transition (d) Shallow and Deep Source/Drain Contact Regions from the deep depletion region under the thin gate For smaller depth junctions, the cross-sections of oxide to the shallow depletion region under the source and drain junctions shrink, increasing the thicker field oxide 22 . Practically, this transition takes parasitic series resistance of the MOSFET. Hence, place smoothly instead of the abrupt transition shown deeper junctions are necessary for minimizing the by the dotted lines for simplifying the calculations. source and drain resistances. But shallow junctions Hence the triangular region of additional charge are desirable for controlling the short-channel effects. between the dotted lines and the smooth bend must be Therefore, a trade-off is needed between very shallow considered for threshold voltage calculation. For junction depths and degradation of source/drain wider MOSFETs the contribution of this charge in resistances. Additionally the junction curvature comparison to the bulk charge is negligible but for increases for shallow junctions, raising the electric narrower widths, this charge becomes an appreciable field in the drain region, thereby lowering the fraction of the total bulk charge, thereby raising the breakdown voltage and increasing the susceptibility threshold voltage of the device. In effect the threshold of the device to hot-carrier effects. Furthermore, in voltage increases because of loss of some of the gate- smaller depth junctions the likelihood of junction induced space charge in the fringing field. damage increases, promoting the leakage current. Additional increase in threshold voltage is The source/drain contact structure comprises the produced due to the encroachment of the heavily- extension region of smaller depth and the contact KHANNA: COMPARATIVE ANALYSIS FOR HIGH-PERFORMANCE COMPUTATIONAL NANOELECTRONICS 799

region of larger depth. The drain extension decreases dielectric constant of 3.9 for the same equivalent the peak electric field near the drain end of the oxide thickness. Hence, a 6.4 nm thick Ta 2O5 layer channel and hence the hot electron damage, besides has the same effect as an SiO 2 layer of thickness 1 reducing the short-channel effect. The deeper nm. The former, due to the necessity of a thicker film, contacting junction is formed to accommodate the provides easy control of thickness. But the quality of thickness of the silicide layer and minimize the Si-SiO 2 interface must be ensured for achieving high junction leakage. The depth of the deeper junction channel mobility. If such an interfacial SiO 2 layer is should not be larger than necessary because a larger required with Ta 2O5, the latter may pose value requires a thicker spacer oxide and a longer tab implementation difficulties because the required extension, resulting in higher resistance. thickness of the interfacial layer may itself be 1 nm.

(g) Polysilicon Depletion Effect (e) Randomness of Dopant Placement in the Transistor This phenomenon 24 is caused by boron penetration Channel from P + polysilicon gate through the thin gate oxide. As there are only 100 dopant atoms in a 50 nm × 50 nm FET the impact of the randomness of dopant Nitrided oxide or oxynitride gate dielectrics are distribution on the transistor characteristics becomes utilized for preventing boron penetration but they more severe in the small devices 21 . This is because the deteriorate the properties of the MOS interface so that doping is performed by ion implantation or thermal oxynitrides without nitrogen at the interface are diffusion. In both these processes the precise position useful. A metal gate electrode such as, W/TiN x is a of the individual dopant atoms cannot be controlled. promising technology for sub-50 nm MOSFETs There are statistical variations of both the number and because of its smaller gate depletion, high thermal position of the dopant atoms. The total number and stability, low resistivity, and CMOS-process compatibility. spatial distribution of the dopant atoms in the channel is scattered around an average value. (h) Hot-carrier Degradation of Small MOSFETs Carriers are said to be hot 25 when they possess high (f) Oxide Integrity energies parametrized by an effective temperature Since the invention of the MOSFET, thermally temperature Te greater than the lattice temperature T. grown silicon dioxide has been the unrivalled gate Obviously, these carriers cannot transfer their insulator due to its remarkable properties unmatched energies to the lattice atoms fast enough to maintain by other materials 23 . But silicon dioxide below 3 nm thermal balance and are therefore not in thermal is not expected to be robust enough for future equilibrium with the lattice. They are generated in the transistor gate dielectric applications. Direct tunneling substrate or insulating regions of the device or the is very sensitive to oxide thickness, increasing inverted channel region when the MOSFET is exponentially with thickness. The increased current operating in the linear or saturation mode. Main raises the standby power dissipation, thereby problems associated with hot carriers are shift of adversely affecting the MOSFET performance. For threshold voltage with time, decrease in gate oxide thickness < 5 nm, an anomalous transconductance, drain current degradation, source- degradation mode referred to as quasi-breakdown drain breakdown induced by avalanche, minority- (QB) has been reported, causing high gate leakage carrier current in the substrate, majority-carrier current at low oxide field and large gate signal substrate current and parasitic gate currents. Special fluctuations. For sub-100 nm gate length MOSFETs care is taken during device design to nullify their the major challenge is suppression of gate leakage effects. current to a permissible level < 1 A/cm 2 for desktop P-channel MOSFETs are less prone to hot-carrier and < 1 mA/cm 2 for portable applications at a problems than N-channel MOSFETs due to the larger required gate capacitance without serious impairment ionization coefficient of holes and greater barrier of channel mobility. height at the insulator interface. In NMOSFETs, hot Hence, thermal oxide is likely to be replaced by carriers consist of substrate hot electrons (SHE), higher dielectric constant materials such as, silicon channel hot electrons (CHE), avalanche hot electrons oxynitrides, TiO 2, Ta 2O5, Si 3N4 and (Ba, Sr) TiO 3. (AHE) and avalanche hot holes (AHH). Tantalum oxide with a dielectric constant of 25 can be SHE are produced when the electrons are made 6.4-times thicker than silicon dioxide with a accelerated by the gate field towards the surface. 800 J SCI IND RES VOL 63 OCTOBER 2004

Energy of most of these electrons decreases through boron than arsenic, results in larger peak surface inelastic scattering. When the electric field is > 20 concentration of arsenic than boron. On the other kV/cm, the electron drift velocity saturates. Further hand, P-channel MOS devices are more resistant to increase in gate field causes impact ionization and hot carrier effects than N-channel devices. This is a under suitable biasing conditions, a fraction of major advantage favouring PMOS. electrons acquire sufficient energy to surmount the Si- The above hurdles in MOS scaling have SiO 2 interfacial barrier. The number of electrons necessitated that research must resort to other injected into the gate oxide is determined by the approaches to achieve further development in this emission probability, which, in turn, is controlled by area. the barrier height. The emission probability is greatly Because continuous shrinkage of MOS device increased by raising the substrate doping dimensions has to meet both functionality and concentration. Some of the electrons injected into the manufacturability requirements, it is necessary to look gate oxide remain trapped inside it, and the number of for new device structures, such as delta-doped (DD) such trapped electrons increases with time. The MOSFET, pocket-implanted (PI) MOSFET, partially- accumulated electrons change the flatband voltage and fully-depleted (PDSOI and FDSOI) MOSFETs and hence the threshold voltage of the device. and double-gate (DG) MOSFET, to sustain the CHE are created by attraction of electrons by the growth of the IC industry in the nanotechnology era 26 . positive drain voltage. Some of the electrons are Retrograded doping profile can lower the minimum heated by the high electric field in the drain depletion achievable channel length by 20 per cent, i.e., up to region. It is found that the drain voltage required for 70 nm. Partially-depleted SOI MOSFET has a maintenance of injection of hot electrons into the comparable scaling potential to the bulk MOSFET but insulator decreases with channel length reduction. fully-depleted SOI MOSFET is difficult to be scaled This happens because of the increased electric field in below 150 nm for satisfactory short-channel the drain region and the effect of 2-D nature of the performance. Only the DG MOSFET can achieve fields in the smaller devices. very small channel length with low threshold voltage AHE and AHH are produced when the drain and thick gate oxide > 4 nm. The two gates provide voltage is high enough to initiate weak avalanching good electrostatic integrity minimizing the drain- by impact ionization in the pinch-off region of the induced barrier lowering and threshold voltage MOSFET. AHE and AHH are collectively known as variation with channel length. avalanche hot carriers (AHC). Nanotechnology is the creation of materials, Using graded drain profile reduces generation of devices and systems through the control of matter on hot carriers but if the source junction is also graded the nanometer length scale (at the level of atoms, like the drain the injection efficiency of source into molecules and supramolecular structures) and the the channel and hence the transconductance utilization of novel properties and phenomena decreases, whereby the channel resistance increases. occurring at that scale. As all natural materials and

(i) N-Channel and P-Channel MOSFETs processes lay down their groundwork at the nanoscale In larger MOSFETs the 2-3-times higher mobility the control of matter at this scale means tailoring the of electrons as compared to holes results in three-to- fundamental properties exactly at the scale where they one current drive ratio as well as faster switching are determined. A nanometric structure is one which speed for NMOS than PMOS devices. But similar has at least one characteristic dimension measured in remarks do not apply to small NMOS and PMOS nanometers. devices because the current in these devices is determined by saturation velocities of carriers which 4 Basic Physics of Single Electronics is ~ 1 ×10 7 cm/s for both electrons and holes. Single electronics is concerned with the controlled Therefore, comparable transconductance values are flow of electrons between small conducting obtained from both NMOS and PMOS devices. islands 27-29 . The underlying idea of single electronics But PMOS devices have a higher series resistance is shown in Figure 4, where a small conductor called than their NMOS counterparts. The reason is that the island is electrically neutral in the beginning PMOS shallow source/drain junctions are formed by (Figure 4a). Hence, an additional electron is boron diffusion, whereas NMOS shallow junctions transferred to the conductor even by a feeble force, use arsenic diffusion. Higher diffusion coefficient of e.g., by tunneling across an energy barrier produced KHANNA: COMPARATIVE ANALYSIS FOR HIGH-PERFORMANCE COMPUTATIONAL NANOELECTRONICS 801

Fig. 5—Schematic of the single-electron box

to thermal energy. When the island size is 100 nm, Ec has the major contribution to Ea which is around 1 Fig. 4—The basic concept of single-electronics meV ~ 10 K. To avoid the suppression of single- electron effects by thermal noise the experiments by a thin dielectric layer. This electron upsets the must be conducted below 1 K. For island size of 10 charge balance of the island making it electrically nm, Ea is 100 meV so that the device is capable of negative. The negative charge thus acquired by the room-temperature operation. But for many single- island prevents any further electron from reaching in electron devices the island size has to be reduced to its vicinity (Fig. 4b) due to the high electric field less than 1 nm, which is inconveniently smaller than created by it which may be ~ 140 kV/cm on the present day lithographic resolution permits. Then Ek surface of sphere of 10-nm diameter in vacuum. The starts to play the decisive role. Hence, such small high electric field is an effect produced by the islands are known as quantum dots . At this scale the extremely small size of the island. This effect is transport properties are extremely sensitive to dot size expressed in terms of the charging energy given by and shape, and therefore islands of this size are generally avoided. q2 E = , … (1) c C 5 Principal Single-Electron Devices (SEDs)

where q is the electronic charge and C is the (a) Single-electron Box, the Conceptually Simplest Single- capacitance of the island. The blockage of the transfer electron Device of any further electron to the island by virtue of This device (Fig. 5) consists of a reservoir of Coulomb repulsion is called the Coulomb blockage electrons called the source separated by a tunnel effect . A single-electron device is defined as an barrier from an island beyond which is placed a gate electronic component in which the addition or electrode . On applying a voltage to the gate electrode, subtraction of electrons to/from an electrode is electron tunneling is initiated between the source and controlled with the precision of a single electron the island. As an electronic component of a digital using the Coulomb blockade effect. computer the single-electron box has the disadvantage As the island size is decreased, in the limiting case that the number of electrons in the box uniquely when it becomes comparable with the de Broglie depends on the applied voltage so that the component wavelength of electrons in the island the energy cannot be used as a memory device for storing quantization phenomenon becomes pronounced. information. Furthermore the component is unable to Hence, in place of the charging energy, a more carry direct current. Hence, an electrometer is relevant concept is the electron addition energy E required to measure its charge state. a expressed as: (b) Single-electron Transistor

This structure (Figure 6) overcomes the drawbacks E =E +E , … (2) a c k of the single-electron box. It consists of a small conducting island sandwiched between two tunnel of which the charging energy Ec is one component and barriers, and a controlling gate electrode. Effectively, the remaining part is the quantum kinetic energy of the it comprises a conducting island placed between the electron ( Ek). source and drain terminals instead of the channel or The condition for appearance of Coulomb blockade inversion layer in a MOSFET. Every time a single effect is that the Coulomb energy becomes comparable electron is added to the island the transistor turns ON 802 J SCI IND RES VOL 63 OCTOBER 2004

requires sub-10 nm structures that are not easy to fabricate from the lithographic standpoint . Thirdly, tunneling is exponentially sensitive to atomic layer fluctuations in barriers producing unacceptably large device to device variations.

Like the CMOS circuits, research in single-electron devices has also tended to pursue binary logic 30-32 . Methods used for single-electron device research are direct electron beam writing and scanning probe manipulation. Low speed prevents the application of these methods to whole chip or whole wafer level. Consequently the fabrication of ULSI circuits with nm resolution seems a prohibitively costly affair . The prospects of single electronics, at least for computer Fig. 6—The capacitively-coupled single-electron transistor logic, are therefore, discouraging 27 . Furthermore, it must be emphasized that present-day technological and OFF. problems like long interconnect delay and large power The building block for single electron devices is consumption cannot be satisfactorily solved by simply the multiple tunnel junction containing multiple replacing the conventional devices with the single- tunnel barriers and electron islands. Electron islands electron ones. By this one-to-one substitution the are made by pattern dependent oxidation (PADOX) situation may even get worsened because of the low method 28 . Naturally formed islands are also used. drivability resulting from the high tunneling Nanosilicon materials too have been investigated. resistance of single-electron devices. The inferior 6 Advantages and Shortcomings of Single drive capability of a single-electron device leads to its Electronics; and Emphasis on Single-electron poor interaction with a remotely located logic unit. This problem is circumvented by using a multi-valued Memory Instead of Logic 33 Major advantages of single electronics are: (i) Easy logic scheme that achieves high functionality with scalability fewer components and interconnections. Single- which results from the operation of devices 34 on Coulomb repulsion between electrons allowing the electron transistor has unique characteristics such as devices to operate at atomic dimensions rendering periodic increase and decrease of drain current with ultra-large scale integration possible, (ii) Low power gate voltage besides staircase-like increase of drain dissipation because of the involvement of a very current with drain voltage thus providing more small number of electrons to accomplish basic functions by using a smaller number of circuit components. operations, and (iii) High operating speed because of transference of a small number of electrons in a But single electronics/FET hybrid memory is process contrary to the charging or discharging of a promising. Here, also the requirement of high-cost large number of electrons ~ 10 5 in a single digital ULSI nanofabrication methods such as multiple operation. electron beam writing is a major economic The foremost difficulty encountered when using disadvantage. Besides, single electronics also single-electron devices in a logic functional unit is provides the physical understanding of the limitations their poor current drive capability as compared to of single-electron charging effects on nanoscale CMOS devices. Since communication with a distantly devices. It has applications in unique scientific located logic unit is a prime requirement, this task is instrumentation like metrology or as tools of scientific performed by CMOS devices. The second serious research, and for fundamental standards of current, shortcoming is the need for low-temperature resistance and temperature. operation . Such operation may be suitable for 7 Necessity of Molecular Electronics, and the understanding the physical mechanisms of devices but Advantages Offered the impact of the technology on industry and society Any successful technology must allow room will be felt only when the devices are capable of temperature operation at the atomic level. It must use operating at room temperature, a feature which self-aligned fabrication. Interconnections between KHANNA: COMPARATIVE ANALYSIS FOR HIGH-PERFORMANCE COMPUTATIONAL NANOELECTRONICS 803

devices must also be addressed. Molecular electronics is an emerging field that seeks to utilize the properties of individual molecules or groups of molecules, notably polyphenylene chains, carbon nanotubes, porphyrins, ploythiophenes, and DNA (deoxyrib- onucleic acid) strands to perform logic or memory functions in microelectronic circuits that are now implemented by semiconductor devices 35-39 . As molecules are 10 7-times smaller than transistors, they afford substantial miniaturization so that lithographic advances will have to care of the size advantage offered by molecules to provide proportionate increase in computation capability per unit area. Moreover, as transistor costs fall on bulk manufacturing, molecular devices also benefit from Fig. 7— A simple nanocell batch production by replication of molecules in large numbers with high yields. Thus in manifold ways, tools for detection, measurement and maneuvering of molecular electronics seems to be more rewarding. individual molecules. The key requirement in molecular electronics is the placement and connection 8 Distinction between Bulk Applications of of a molecule between metal electrodes . An important Molecules and Molecular-scale Electronics; technique uses the spontaneous self-absorption of Enabling Technologies and Terminological molecules between contacts such as, the ability to Analogies form self-assembled monolayers (SAM) of oligomers Molecular materials , mainly organic type, have on metals. long been used for electronic and photonic The terminology of solid-state physics is modified applications such as, liquid crystal displays (LCDs), in molecular electronics as: Highest occupied and light-emitting diodes (LEDs), lasers, transistors, and lowest occupied molecular orbitals take the place of sensors. But in molecular electronics the molecule valence and conduction bands. Similarly, instead of itself is looked upon as an active electronic device , doping for Fermi level modification, one refers to e.g., unimolecular rectification takes place through changes in electron affinity and ionization potential of the molecular orbitals of a single D-σ-A molecule by molecules through chemical substitution. The through-bond tunneling mechanism ( D denotes an analogue of bandgap engineering is designing in electron donor having a low ionization potential, A is molecular orbitals. a high electron-affinity electron acceptor, and σ is a covalent bridge). 9 Nanocell Circuits for Logic and Memory Polyphenylene molecules act as conductors. Functions Carbon nanotubes or bucky tubes of different The nanocell 40,41 is a molecular electronics diameters and helicities, exhibit wide-ranging architecture comprising a random, self-assembled behaviour from conductors to insulators. A junction array of molecules and conducting nanoparticles between two types of chiral structures results in a which are addressed by metallic leads or input/output diode switch. A field-effect transistor is made by (I/O) pins, for programming the nanocell as a logic incorporating a single-wall nanotube between two gate or memory device, after the fabrication of the metal electrodes. Experiments on DNA have yielded cell. Fig. 7 shows a simple nanocell containing two various results from insulating properties to metallic nanoparticles depicted as circles and five molecular conduction due to different DNA sequencing switches indicated by dark and bright lines, dark for conditions. ON and bright for OFF states of molecules, and the Enabling technologies for molecular electronics are two input/output leads shown as black rectangles. the nanofabrication techniques in conjunction with Immediately after fabrication the nanocell conducts atomic imaging techniques such as, scanning electricity across its leads in a non-linear fashion. tunneling microscope (STM) and atomic force Only after proper programming does it carry out the microscope (AFM). ATM and AFM are the main desired functions. The programming is done by 804 J SCI IND RES VOL 63 OCTOBER 2004

cell clicks this cell into an aligned configuration, either a 1 or 0, without any current flowing between the cells. The middle dot of each cell is used for clocking purposes . The potential of this dot can be varied. For a large, attractive potential the mobile charges are pulled by the middle dot producing the null state of the cell in which it contains no information. When the potential of the middle dot is large but repulsive the charge shifts to the cell corners resulting in a 1 or 0 state. Clocked control of the QCA cell provides reduces the power dissipation and provides power gain. It also furnishes

computational pipelining. In molecular electronics the Fig. 8—A clocked six-dot quantum-dot cellular automata cell role of quantum dots is played by the redox centres which are reduced by adding an electron or oxidized by applying voltage pulses in an algorithmically defined losing an electron, without breaking the chemical order to the cell leads whereby the molecules switch bonds. Thus the QCA paradigm offers the simplicity of their states in accordance with voltage dependent binary representation and general-purpose computation switching rules, and the cell is configured for the in nanoscale computing. targeted logic function. The nanocell exploits the self- assembling tendency of molecules to place them in predefined regions at the required densities, thereby 11 Conclusions building the interconnection pathways. Thus the focal This paper examines the present status and idea of a nanocell is to simplify cell fabrication and forecasts of microelectronic devices and circuits for transfer the difficult tasks to the post-fabrication the computing industry. Three distinct competing programming. Although the constructional units of the challenges have emerged: (i) To solve the problems of nanocells are molecules the nanocells have dimensions the mainstream CMOS technology in the sub-10 nm on the micron scale so that lithographic techniques can region, (ii) To solve the low-temperature operation be utilized for making the inteconnections. problems of single electronics, i.e., the random charge effect, so that reliable room-temperature device 10 Clocked Molecular Quantum-dot Cellular operation becomes a reality, and (iii) To radically Automata (QCA) change the present line of thinking, and visualize Another favourite molecular electronics design is computers built from molecular designs such as QCA, the clocked molecular quantum-dot cellular automata a transistorless computation paradigm that addresses (QCA) 42-45 . In this computing approach the present-day device interconnections. Motivation for such switches are not used. However, binary digits are paradigms is provided by the opportunity to break retained by representing the information as the away from the long-prevailing FET-based logic of electronic charge configuration among the quantum current switches by making the basic logic element an dots of a cell. The devices are made up of cells which array of quantum dots. themselves are build up of a small number of quantum Amongst these three candidate approaches the dots , defined as regions wherein charge is localized. CMOS technology has achieved the highest degree of Figure 8 shows a clocked six-dot QCA cell. The cell maturity. It indubitably occupies the ‘enviable contains two additional mobile electrons which have a supreme position’. Prospects of single-electron logic tendency to minimize their mutual Coulomb interaction as a frontier technology are dismal but single by occupying the opposite corners of the cell. The four electron/FET hybrid memory, and combined single- dots occupying the opposite corners of the cells electron/ metal-oxide-semiconductor transistor multi- therefore determine the two energetically equivalent valued logic 33 could be used as a supportive ground degenerate state polarizations of the cell technology to CMOS circuits. The potential of designated as the binary “0” and “1”. For computations molecular electronics remains to be harnessed. the cells are placed near each other. Then interaction Perhaps its impact may be more penetrating and takes place between the adjoining cells via capacitive effective in introducing revolutionary or evolutionary coupling. Perturbation of the neighbouring cell on any changes in the scenario in the long run. KHANNA: COMPARATIVE ANALYSIS FOR HIGH-PERFORMANCE COMPUTATIONAL NANOELECTRONICS 805

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