DOCSLIB.ORG

Run-Time Adaptable VLIW Processors

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Run-Time Adaptable VLIW Processors Fakhar Anjam Run-time Adaptable VLIW Processors Resources, Performance, Power Consumption, and Reliability Trade-offs Run-time Adaptable VLIW Processors Resources, Performance, Power Consumption, and Reliability Trade-offs PROEFSCHRIFT ter verkrijging van de graad van doctor aan de Technische Universiteit Delft, op gezag van de Rector Magnificus prof. ir. K.C.A.M. Luyben, voorzitter van het College voor Promoties, in het openbaar te verdedigen op dinsdag 27 augustus 2013 om 15:00 uur door Fakhar ANJAM Master of Science in Information Technology Pakistan Institute of Engineering and Applied Sciences (PIEAS), Islamabad geboren te Karak, Pakistan Dit proefschrift is goedgekeurd door de promotor: Prof. dr. K.L.M. Bertels Copromotor: Dr. ir. J.S.S.M. Wong Samenstelling promotiecommissie: RectorMagnificus voorzitter Prof.dr.K.L.M.Bertels TechnischeUniversiteitDelft,promotor Dr. ir. J.S.S.M. Wong Technische Universiteit Delft, copromotor Prof.dr.E.Charbon TechnischeUniversiteitDelft Prof.dr.L.Carro UniversidadeFederaldoRioGrandedoSul, Brazilië Prof.Dr.-Ing.H.Blume LeibnizUniversitätHannover,Duitsland Prof.Dr.-Ing.M.Hübner Ruhr-UniversitätBochum,Duitsland Prof. dr. ir. G.N.Gaydadjiev ChalmersUniversityofTechnology, Zweden Prof.dr.G.J.T.Leus TechnischeUniversiteitDelft,reservelid This thesis has been completed in partial fulfillment of the requirements of the Delft University of Technology (Delft, The Netherlands) for the award of PhD degree. The research described in this thesis was supported in parts by: (1) CE Lab. Delft University of Technology, (2) HEC Pakistan. Publishedanddistributedby: FakharAnjam Email: [email protected] ISBN: 978-94-6186-191-7 Keywords: Computer Architecture, Parallel Execution, Softcore Processors, VLIW Processors, Run-time Reconfiguration, Fault Tolerance, Customization, Parametriza- tion, FPGAs, Trade-offs Cover page designed by Hanike (www.hanike.nl). Copyright c 2013 Fakhar Anjam All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without permission of the author. Printed in The Netherlands To my father and all other members of my family Summary In this dissertation, we propose to combine programmability with reconfig- urability by implementing an adaptable programmable VLIW processor in a reconfigurable hardware. The approach allows applications to be developed at high-level (C language level), while at the same time, the processor organiza- tion can be adapted to the specific requirements (both static and dynamic) of different applications. Our proposed customizable VLIW processor called ρ-VEX can be adapted at design-time as well as at run-time. Its instruction set architecture (ISA) is based on the VEX ISA and a toolchain (parametrized C compiler and sim- ulator) is publicly available from Hewlett Packard (HP) for architectural ex- ploration and code generation. The design-time parameters include the pro- cessor’s issue-width, the type of different functional units (FUs) and their la- tencies, the type and size of multiported register files, degree of pipelining, size of instruction and data memories, type of interrupt and exception systems, selection of default custom operations, datapath sharing. If the behavior of applications is not known at design-time or an application has different phases with distinct requirements, a fixed processor may not perform efficiently for all the applications/phases. To this end, we propose a run-time reconfigurable processor that can adapt its organization dynamically during execution. The run-time parameters include the processor’s issue-width, the type and number of different FUs, and the register file size. Additionally, we propose config- urable fault tolerance techniques for the ρ-VEX processor. The designer can choose to include or exclude the fault tolerance in the processor at design-time. When the fault tolerance is included, it can be made permanently enabled or enabled/disabled at run-time. All these options enable users to trade-off be- tween hardware area/resources, performance, power/energy consumption, and reliability. The processor is available as open-source. i Samenvatting In dit proefschrift stellen we voor om programmeerbaarheid te combineren met reconfigureerbaarheid door het implementeren van een aanpasbare pro- grammeerbare VLIW processor in herconfigureerbare hardware. De aanpak staat het ontwikkelen van toepassingen op hoog niveau (C programmeer taal- niveau) toe, terwijl op hetzelfde moment de processor organisatie kan worden aangepast aan de specifieke eisen (zowel statisch als dynamisch) van verschil- lende toepassingen. Onze voorgestelde aanpasbare VLIW processor, genaamd ρ-VEX, kan tijdens design-time evenals tijdens run-time aangepast worden. De instructie set archi- tectuur (ISA) is gebaseerd op de VEX ISA en een toolchain (geparametriseerde C compiler en simulator) is publiek beschikbaar gesteld door Hewlett Packard (HP) voor architectuur exploratie en code generatie. De design-time parame- ters omvatten de processor issue-breedte, de aard van verschillende functionele eenheden (FU’s) en hun latencies, het type en grootte van multiported regis- ter files, de mate van pipelining, de grootte van instructie en data geheugens, het type interrupt en exceptie systemen, selectie van standaard aangepaste bew- erkingen, het delen van het datapad. Indien het gedrag van applicaties niet bek- end is tijdens design-time of wanneer een applicatie verschillende fases kent met verschillende eisen, kan het zijn dat een vaste processor niet efficiënt is in het uitvoeren van alle applicaties/fasen. Daartoe stellen we een run-time her- configureerbare processor voor die zijn organisatie tijdens het berekenen dy- namisch kan aanpassen. De run-time parameters omvatten de processor issue- breedte, het type en aantal verschillende FUs, en het register bestandsgrootte. Daarnaast stellen we voor de ρ-VEX processor herconfigureerbare fouttoler- antie technieken voor. De ontwerper kan kiezen voor wel of geen fouttolerantie in de processor tijdens design-time. Wanneer fouttolerantie is inbegrepen, kan deze permanent ingeschakeld worden of ingeschakeld/uitgeschakeld tij- dens run-time. Al deze opties geven de gebruikers de mogelijkheid om een afweging te maken tussen hardware area/resources, prestatie, stroom/energie verbruik en betrouwbaarheid. De processor is als open-source beschikbaar. ii Prepositions 1. All hardware and software should be reconfigurable. 2. Hardwired multiported memories are a must for the efficient implemen- tation of parallel hardware in FPGA. 3. Software comes from heaven when you have good hardware. (Ken Olsen) 4. The distinction between VLIW and superscalar processors is vanishing. 5. Normal life starts after the PhD study. 6. A good idea means nothing by itself; a good implementation is equally important. 7. Will is more important than competence to achieve something. 8. You are not doing research when you know what you are doing. 9. “Freedom of expression” should not be considered as unlimited. 10. Without improving the primary education system in Pakistan, spending billions in higher education is of little use. 11. Tolerance is the only thing the Pakistani nation needs nowadays. 12. A good way to learn new things is to be unlucky. These propositions are regarded as opposable and defendable, and have been approved as such by the promotor Prof. dr. K.L.M. Bertels. iii Stellingen 1. Alle hardware en software zou herconfigureerbaar moeten zijn. 2. Hardwired multiported geheugens zijn een vereiste voor het efficiënt im- plementeren van parallel hardware op FPGA. 3. Software komt van de hemel wanneer je goede hardware hebt. (Ken Olsen) 4. Het verschil tussen VLIW en superscalar processoren is aan het verdwi- jnen. 5. Het normale leven starts na de PhD studie. 6. Een goede idee betekent opzichzelfstaand niets, een goede implemen- tatie is even belangrijk. 7. Wil hebben is belangrijker dan competentie om iets te bereiken. 8. Je bent geen onderzoek aan het doen als je weet wat je aan het doen bent. 9. "Vrijheid van meningsuiting" moet niet als onbeperkt worden beschouwd. 10. Zonder het verbeteren van het primair onderwijs in Pakistan is het uit- geven van miljarden in hoger onderwijs van weinig nut. 11. Vandaag de dag is tolerantie het enige dat de Pakistaanse natie nodig heeft. 12. Een goede manier om nieuwe dingen te leren is om een pechvogel te zijn. Deze stellingen worden opponeerbaar en verdedigbaar geacht en zijn als zo- danig goedgekeurd door de promotor Prof. dr. K.L.M. Bertels. iv Acknowledgments Here comes the end to my formal student life. That was a fun by itself. Find- ing this opportunity, I would like to express my gratitude to all those who contributed directly or indirectly to the work reported in this thesis. First of all, I would like to thank my supervisor Stephan Wong who provided me the opportunity to perform research in the Computer Engineering (CE) Lab. His guidance and consistent involvement in all phases of my PhD research project is truly remarkable. We had many brainstorming sessions and long technical meetings that helped me a lot in my work. Special thanks go to the promotor of my thesis Koen Bertels. He always offered his help through out my stay at the university. I am also very grateful to all the faculty members of CE who provided me help and guidance from time to time. The members of my PhD committee also deserve appreciation. I thank them for devoting some of their time
Load more

Recommended publications
  • A Superscalar Out-Of-Order X86 Soft Processor for FPGA
    A Superscalar Out-of-Order x86 Soft Processor for FPGA Henry Wong University of Toronto, Intel [email protected] June 5, 2019 Stanford University EE380 1 Hi! ● CPU architect, Intel Hillsboro ● Ph.D., University of Toronto ● Today: x86 OoO processor for FPGA (Ph.D. work) – Motivation – High-level design and results – Microarchitecture details and some circuits 2 FPGA: Field-Programmable Gate Array ● Is a digital circuit (logic gates and wires) ● Is field-programmable (at power-on, not in the fab) ● Pre-fab everything you’ll ever need – 20x area, 20x delay cost – Circuit building blocks are somewhat bigger than logic gates 6-LUT6-LUT 6-LUT6-LUT 3 6-LUT 6-LUT FPGA: Field-Programmable Gate Array ● Is a digital circuit (logic gates and wires) ● Is field-programmable (at power-on, not in the fab) ● Pre-fab everything you’ll ever need – 20x area, 20x delay cost – Circuit building blocks are somewhat bigger than logic gates 6-LUT 6-LUT 6-LUT 6-LUT 4 6-LUT 6-LUT FPGA Soft Processors ● FPGA systems often have software components – Often running on a soft processor ● Need more performance? – Parallel code and hardware accelerators need effort – Less effort if soft processors got faster 5 FPGA Soft Processors ● FPGA systems often have software components – Often running on a soft processor ● Need more performance? – Parallel code and hardware accelerators need effort – Less effort if soft processors got faster 6 FPGA Soft Processors ● FPGA systems often have software components – Often running on a soft processor ● Need more performance? – Parallel
    [Show full text]
  • Implementation, Verification and Validation of an Openrisc-1200
    (IJACSA) International Journal of Advanced Computer Science and Applications, Vol. 10, No. 1, 2019 Implementation, Verification and Validation of an OpenRISC-1200 Soft-core Processor on FPGA Abdul Rafay Khatri Department of Electronic Engineering, QUEST, NawabShah, Pakistan Abstract—An embedded system is a dedicated computer system in which hardware and software are combined to per- form some specific tasks. Recent advancements in the Field Programmable Gate Array (FPGA) technology make it possible to implement the complete embedded system on a single FPGA chip. The fundamental component of an embedded system is a microprocessor. Soft-core processors are written in hardware description languages and functionally equivalent to an ordinary microprocessor. These soft-core processors are synthesized and implemented on the FPGA devices. In this paper, the OpenRISC 1200 processor is used, which is a 32-bit soft-core processor and Fig. 1. General block diagram of embedded systems. written in the Verilog HDL. Xilinx ISE tools perform synthesis, design implementation and configure/program the FPGA. For verification and debugging purpose, a software toolchain from (RISC) processor. This processor consists of all necessary GNU is configured and installed. The software is written in C components which are available in any other microproces- and Assembly languages. The communication between the host computer and FPGA board is carried out through the serial RS- sor. These components are connected through a bus called 232 port. Wishbone bus. In this work, the OR1200 processor is used to implement the system on a chip technology on a Virtex-5 Keywords—FPGA Design; HDLs; Hw-Sw Co-design; Open- FPGA board from Xilinx.
    [Show full text]
  • Softcores for FPGA: the Free and Open Source Alternatives
    Softcores for FPGA: The Free and Open Source Alternatives Jeremy Bennett and Simon Cook, Embecosm Abstract Open source soft cores have reached a degree of maturity. You can find them in products as diverse as a Samsung set-top box, NXP's ZigBee chips and NASA's TechEdSat. In this article we'll look at some of the more widely used: the OpenRISC 1000 from OpenCores, Gaisler's LEON family, Lattice Semiconductor's LM32 and Oracle's OpenSPARC, as well as more bleeding edge research designs such as BERI and CHERI from Cambridge University Computer Laboratory. We'll consider the technology, the business case, the engineering risks, and the licensing challenges of using such designs. What do we mean by “free” “Free” is an overloaded term in English. It can mean something you don't pay for, as in “this beer is free”. But it can also mean freedom, as in “you are free to share this article”. It is this latter sense that is central when we talk about free software or hardware designs. Of course such software or hardware designs may also be free, in the sense that you don't have to pay for them, but that is secondary. “Free” software in this sense has been around for a very long time. Explicitly since 1993 and Richard Stallman's GNU Manifesto, but implicitly since the first software was written and shared with colleagues and friends. That freedom is achieved by making the source code available, so others can modify the program, hence the more recent alternative name “open source”, but it is freedom that remains the key concept.
    [Show full text]
  • Openpiton: an Open Source Manycore Research Framework
    OpenPiton: An Open Source Manycore Research Framework Jonathan Balkind Michael McKeown Yaosheng Fu Tri Nguyen Yanqi Zhou Alexey Lavrov Mohammad Shahrad Adi Fuchs Samuel Payne ∗ Xiaohua Liang Matthew Matl David Wentzlaff Princeton University fjbalkind,mmckeown,yfu,trin,yanqiz,alavrov,mshahrad,[email protected], [email protected], fxiaohua,mmatl,[email protected] Abstract chipset Industry is building larger, more complex, manycore proces- sors on the back of strong institutional knowledge, but aca- demic projects face difficulties in replicating that scale. To Tile alleviate these difficulties and to develop and share knowl- edge, the community needs open architecture frameworks for simulation, synthesis, and software exploration which Chip support extensibility, scalability, and configurability, along- side an established base of verification tools and supported software. In this paper we present OpenPiton, an open source framework for building scalable architecture research proto- types from 1 core to 500 million cores. OpenPiton is the world’s first open source, general-purpose, multithreaded manycore processor and framework. OpenPiton leverages the industry hardened OpenSPARC T1 core with modifica- Figure 1: OpenPiton Architecture. Multiple manycore chips tions and builds upon it with a scratch-built, scalable uncore are connected together with chipset logic and networks to creating a flexible, modern manycore design. In addition, build large scalable manycore systems. OpenPiton’s cache OpenPiton provides synthesis and backend scripts for ASIC coherence protocol extends off chip. and FPGA to enable other researchers to bring their designs to implementation. OpenPiton provides a complete verifica- tion infrastructure of over 8000 tests, is supported by mature software tools, runs full-stack multiuser Debian Linux, and has been widespread across the industry with manycore pro- is written in industry standard Verilog.
    [Show full text]
  • Small Soft Core up Inventory ©2019 James Brakefield Opencore and Other Soft Core Processors Reverse-U16 A.T
    tool pip _uP_all_soft opencores or style / data inst repor com LUTs blk F tool MIPS clks/ KIPS ven src #src fltg max max byte adr # start last secondary web status author FPGA top file chai e note worthy comments doc SOC date LUT? # inst # folder prmary link clone size size ter ents ALUT mults ram max ver /inst inst /LUT dor code files pt Hav'd dat inst adrs mod reg year revis link n len Small soft core uP Inventory ©2019 James Brakefield Opencore and other soft core processors reverse-u16 https://github.com/programmerby/ReVerSE-U16stable A.T. Z80 8 8 cylcone-4 James Brakefield11224 4 60 ## 14.7 0.33 4.0 X Y vhdl 29 zxpoly Y yes N N 64K 64K Y 2015 SOC project using T80, HDMI generatorretro Z80 based on T80 by Daniel Wallner copyblaze https://opencores.org/project,copyblazestable Abdallah ElIbrahimi picoBlaze 8 18 kintex-7-3 James Brakefieldmissing block622 ROM6 217 ## 14.7 0.33 2.0 57.5 IX vhdl 16 cp_copyblazeY asm N 256 2K Y 2011 2016 wishbone extras sap https://opencores.org/project,sapstable Ahmed Shahein accum 8 8 kintex-7-3 James Brakefieldno LUT RAM48 or block6 RAM 200 ## 14.7 0.10 4.0 104.2 X vhdl 15 mp_struct N 16 16 Y 5 2012 2017 https://shirishkoirala.blogspot.com/2017/01/sap-1simple-as-possible-1-computer.htmlSimple as Possible Computer from Malvinohttps://www.youtube.com/watch?v=prpyEFxZCMw & Brown "Digital computer electronics" blue https://opencores.org/project,bluestable Al Williams accum 16 16 spartan-3-5 James Brakefieldremoved clock1025 constraint4 63 ## 14.7 0.67 1.0 41.1 X verilog 16 topbox web N 4K 4K N 16 2 2009
    [Show full text]
  • Design of the RISC-V Instruction Set Architecture
    Design of the RISC-V Instruction Set Architecture Andrew Waterman Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report No. UCB/EECS-2016-1 http://www.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-1.html January 3, 2016 Copyright © 2016, by the author(s). All rights reserved. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. Design of the RISC-V Instruction Set Architecture by Andrew Shell Waterman A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Computer Science in the Graduate Division of the University of California, Berkeley Committee in charge: Professor David Patterson, Chair Professor Krste Asanovi´c Associate Professor Per-Olof Persson Spring 2016 Design of the RISC-V Instruction Set Architecture Copyright 2016 by Andrew Shell Waterman 1 Abstract Design of the RISC-V Instruction Set Architecture by Andrew Shell Waterman Doctor of Philosophy in Computer Science University of California, Berkeley Professor David Patterson, Chair The hardware-software interface, embodied in the instruction set architecture (ISA), is arguably the most important interface in a computer system. Yet, in contrast to nearly all other interfaces in a modern computer system, all commercially popular ISAs are proprietary.
    [Show full text]
  • Evaluation of Synthesizable CPU Cores
    Evaluation of synthesizable CPU cores DANIEL MATTSSON MARCUS CHRISTENSSON Maste r ' s Thesis Com p u t e r Science an d Eng i n ee r i n g Pro g r a m CHALMERS UNIVERSITY OF TECHNOLOGY Depart men t of Computer Engineering Gothe n bu r g 20 0 4 All rights reserved. This publication is protected by law in accordance with “Lagen om Upphovsrätt, 1960:729”. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior permission of the authors. Daniel Mattsson and Marcus Christensson, Gothenburg 2004. Evaluation of synthesizable CPU cores Abstract The three synthesizable processors: LEON2 from Gaisler Research, MicroBlaze from Xilinx, and OpenRISC 1200 from OpenCores are evaluated and discussed. Performance in terms of benchmark results and area resource usage is measured. Different aspects like usability and configurability are also reviewed. Three configurations for each of the processors are defined and evaluated: the comparable configuration, the performance optimized configuration and the area optimized configuration. For each of the configurations three benchmarks are executed: the Dhrystone 2.1 benchmark, the Stanford benchmark suite and a typical control application run as a benchmark. A detailed analysis of the three processors and their development tools is presented. The three benchmarks are described and motivated. Conclusions and results in terms of benchmark results, performance per clock cycle and performance per area unit are discussed and presented. Sammanfattning De tre syntetiserbara processorerna: LEON2 från Gaisler Research, MicroBlaze från Xilinx och OpenRISC 1200 från OpenCores utvärderas och diskuteras.
    [Show full text]
  • Small Soft Core up Inventory ©2014 James Brakefield Opencore and Other Soft Core Processors Only Cores in the "Usable" Category Included
    Small soft core uP Inventory ©2014 James Brakefield Opencore and other soft core processors Only cores in the "usable" category included Most Prolific Authors ©2014 James Brakefield John Kent micro8a, micro16b, system05, system09, system11, system68 6 Daniel Wallner ax8, ppx16, t65, t80 4 Ulrich Riedel 68hc05, 68hc08, tiny64, tiny8 4 Jose Ruiz ion, light52, light8080 3 Lazaridis Dimitris mips_fault_tolerant, mipsr2000, mips_enhanced 3 Shawn Tan ae18, aeMB, k68 3 Most FPGA results (e.g. easy to compile, place & route on any FPGA family) ©2014 James Brakefield eco32 cyclone-4, arria-2, spartan-3, spartan-6, kintex-7 5 navre cyclone-4, arria-2, cyclone-5, spartan-6, kintex-7 5 leros cyclone-4, spartan-3, spartan-6, kintex-7 4 openmsp430 cyclone-4, stratix-3, spartan-6, virtex-6 4 Most Clones ©2014 James Brakefield ion, minimips, mips_fault_tolerant, misp32r1, misp789, mipsr2000, plasma, ucore, yacc, MIPS 10 m1_core 6502 ag_6502, cpu6502_true_cycle, free6502, lattice6502, m65c02, t65, t6507lp, m65 8 PIC16 free_risc8, lwrisc, minirisc, p16c5x, ppx16, recore54, risc16f84, risc5x 8 microblaze aeMB, mblite, microblaze, myblaze, openfire_core, secretblaze 6 6800 hd63701, system68, system05, 68hc05, 68hc08 5 8051 dalton_8051, light52, mc8051, t51, turbo8051 5 avr avr_core, avr_hp, avr8, navre, riscmcu 5 z80 nextz80, t80, tv80, wb_z80, y80e 5 openrisc altor32, minsoc, or1k, or1200_hp 4 6809 6809_6309, system09, mc6809e 3 8080 cpu8080, light8080, t80 3 68000 ao68000, tg68, v1_coldfire 3 PDP-8 pdp8, pdp8l, pdp8verilog 3 picoblaze copyblaze, pacoblaze,
    [Show full text]
  • Open-Source 32-Bit RISC Soft-Core Processors
    IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 2, Issue 4 (May. – Jun. 2013), PP 43-46 e-ISSN: 2319 – 4200, p-ISSN No. : 2319 – 4197 www.iosrjournals.org Open-Source 32-Bit RISC Soft-Core Processors Rahul R.Balwaik, Shailja R.Nayak, Prof. Amutha Jeyakumar Department of Electrical Engineering, VJTI, Mumbai-19, INDIA Abstract: A soft-core processor build using a Field-Programmable Gate Array (FPGA)’s general-purpose logic represents an embedded processor commonly used for implementation. In a large number of applications; soft-core processors play a vital role due to their ease of usage. Soft-core processors are more advantageous than their hard-core counterparts due to their reduced cost, flexibility, platform independence and greater immunity to obsolescence. This paper presents a survey of a considerable number of soft core processors available from the open-source communities. Some real world applications of these soft-core processors are also discussed followed by the comparison of their several features and characteristics. The increasing popularity of these soft-core processors will inevitably lead to more widespread usage in embedded system design. This is due to the number of significant advantages that soft-core processors hold over their hard-core counterparts. Keywords: Field-Programmable Gate Array (FPGA), Application-Specific Integrated Circuit (ASIC), open- source, soft-core processors. I. INTRODUCTION Field-Programmable Gate Array (FPGA) has grown in capacity and performance, and is now one of the main implementation fabrics for designs, particularly where the products do not demand for custom integrated circuits. And in recent past due to the increased capacity and falling cost of the FPGA’s relatively fast and high density devices are today becoming available to the general public.
    [Show full text]
  • Porting Debian to the RISC-V Architecture Tales from a Long Quest
    Porting Debian to the RISC-V architecture Tales from a long quest. Karsten Merker <[email protected]> February 2, 2019 These slides are licensed under the Creative Commons \CC-BY-4.0" license. 1 What is RISC-V? • RISC-V is a freely licensed CPU Instruction Set Architecture (ISA) originating from the University of California, Berkeley (UCB). • Everybody is free to implement processors based on the RISC-V ISA without royalty payments for using the ISA. • The ISA specification is available under CC-BY license. • Conformance to the specification is secured via trademarks. Only implementations that fully conform to the specification may call themselves \RISC-V". • Available in 32bit, 64bit and (not yet fully specified) 128bit flavours • Designed to scale from microcontrollers to supercomputers by using a modular design. • The ISA design aims at using only techniques that are patent-free, although there is no legal guarantee for that. 2 What is RISC-V not? RISC-V • is not a microprocessor implementation. • doesn't require implementations to be freely licensed, i.e. there can be (and are) non-free RISC-V implementations. • doesn't have an open stewardship in the way open-source projects define \open", only in the way the semiconductor industry defines \open": • The specifications are released under a DFSG-free license (CC-BY), but contributing to standard working groups and access to pre-release documents requires a RISC-V foundation membership. • The RISC-V foundation is a US 501(c)(6) non-profit (i.e. an industry consortium), not a US 501(c)(3) non-profit (i.e.
    [Show full text]
  • The RISC-V Instruction Set Manual Volume I: User-Level ISA Document Version 2.2
    The RISC-V Instruction Set Manual Volume I: User-Level ISA Document Version 2.2 Editors: Andrew Waterman1, Krste Asanovi´c1;2 1SiFive Inc., 2CS Division, EECS Department, University of California, Berkeley [email protected], [email protected] May 7, 2017 Contributors to all versions of the spec in alphabetical order (please contact editors to suggest corrections): Krste Asanovi´c,Rimas Aviˇzienis,Jacob Bachmeyer, Christopher F. Batten, Allen J. Baum, Alex Bradbury, Scott Beamer, Preston Briggs, Christopher Celio, David Chisnall, Paul Clayton, Palmer Dabbelt, Stefan Freudenberger, Jan Gray, Michael Hamburg, John Hauser, David Horner, Olof Johansson, Ben Keller, Yunsup Lee, Joseph Myers, Rishiyur Nikhil, Stefan O'Rear, Albert Ou, John Ousterhout, David Patterson, Colin Schmidt, Michael Taylor, Wesley Terpstra, Matt Thomas, Tommy Thorn, Ray VanDeWalker, Megan Wachs, Andrew Waterman, Robert Wat- son, and Reinoud Zandijk. This document is released under a Creative Commons Attribution 4.0 International License. This document is a derivative of \The RISC-V Instruction Set Manual, Volume I: User-Level ISA Version 2.1" released under the following license: c 2010{2017 Andrew Waterman, Yunsup Lee, David Patterson, Krste Asanovi´c. Creative Commons Attribution 4.0 International License. Please cite as: \The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 2.2", Editors Andrew Waterman and Krste Asanovi´c,RISC-V Foundation, May 2017. Preface This is version 2.2 of the document describing the RISC-V user-level architecture. The document contains the following versions of the RISC-V ISA modules: Base Version Frozen? RV32I 2.0 Y RV32E 1.9 N RV64I 2.0 Y RV128I 1.7 N Extension Version Frozen? M 2.0 Y A 2.0 Y F 2.0 Y D 2.0 Y Q 2.0 Y L 0.0 N C 2.0 Y B 0.0 N J 0.0 N T 0.0 N P 0.1 N V 0.2 N N 1.1 N To date, no parts of the standard have been officially ratified by the RISC-V Foundation, but the components labeled \frozen" above are not expected to change during the ratification process beyond resolving ambiguities and holes in the specification.
    [Show full text]
  • Basic Custom Openrisc System Hardware Tutorial
    DE NAYER Instituut J. De Nayerlaan 5 B-2860 Sint-Katelijne-Waver Tel. (015) 31 69 44 Fax. (015) 31 74 53 e-mail: [email protected] [email protected] [email protected] website: emsys.denayer.wenk.be Basic Custom OpenRISC System Hardware Tutorial Xilinx Version 1.00 HOBU-Fund Project IWT 020079 Title : Embedded systemdesign based upon Soft- and Hardcore FPGA’s Projectleader : Ing. Patrick Pelgrims Projectassistants : Ing. Dries Driessens Ing. Tom Tierens Copyright (c) 2004 by Patrick Pelgrims, Tom Tierens and Dries Driessens. This material may be distributed only subject to the terms and conditions set forth in the Open Publication License, v1.0 or later (the latest version is presently available at http://www.opencontent.org/openpub/). I Introduction Purpose of this tutorial is to help you compose and implement a custom, OpenRISC based, embedded system in the easiest way possible. Unexperienced users should be warned that the OpenRISC processor is quite a difficult processor : the lack of a self-configuring embedded system-package and the more ‘open’ nature of the OpenRISC compared to other open-source processors like the Leon SPARC is one of the reasons for this. Before proceeding, check if you have the following software and hardware: Hardware: - Linux-PC or Windows-PC - Development board with Xilinx FPGA (minimum 3100 Slices), UART and 6 available pins. Software: - OpenRISC-GNU Toolchain - Xilinx ISE Webpack or ISE for Windows or Linux - For Windows : WinCVS 1.2 (http://prdownloads.sourceforge.net/cvsgui/WinCvs120.zip) If you experience problems building the OpenRISC-GNU Toolchain, there is also an OpenRISC Software tutorial available from our website (http://emsys.denayer.wenk.be).
    [Show full text]