Fakhar Anjam

Run-time Adaptable VLIW Processors

Resources, Performance, Power Consumption, and Reliability Trade-offs

Run-time Adaptable VLIW Processors

Resources, Performance, Power Consumption, and Reliability Trade-offs

PROEFSCHRIFT

ter verkrijging van de graad van doctor aan de Technische Universiteit Delft, op gezag van de Rector Magnificus prof. ir. K..A.M. Luyben, voorzitter van het College voor Promoties, in het openbaar te verdedigen

op dinsdag 27 augustus 2013 om 15:00 uur

door

Fakhar ANJAM

Master of Science in Information Technology Pakistan Institute of Engineering and Applied Sciences (PIEAS), Islamabad

geboren te Karak, Pakistan Dit proefschrift is goedgekeurd door de promotor: Prof. dr. K.L.M. Bertels

Copromotor: Dr. ir. J.S.S.M. Wong

Samenstelling promotiecommissie:

RectorMagnificus voorzitter Prof.dr.K.L.M.Bertels TechnischeUniversiteitDelft,promotor Dr. ir. J.S.S.M. Wong Technische Universiteit Delft, copromotor Prof.dr.E.Charbon TechnischeUniversiteitDelft Prof.dr.L.Carro UniversidadeFederaldoRioGrandedoSul, Brazilië Prof.Dr.-Ing.H.Blume LeibnizUniversitätHannover,Duitsland Prof.Dr.-Ing.M.Hübner Ruhr-UniversitätBochum,Duitsland Prof. dr. ir. G.N.Gaydadjiev ChalmersUniversityofTechnology, Zweden Prof.dr.G.J.T.Leus TechnischeUniversiteitDelft,reservelid

This thesis has been completed in partial fulfillment of the requirements of the Delft University of Technology (Delft, The Netherlands) for the award of PhD degree. The research described in this thesis was supported in parts by: (1) CE Lab. Delft University of Technology, (2) HEC Pakistan.

Publishedanddistributedby: FakharAnjam Email: [email protected]

ISBN: 978-94-6186-191-7

Keywords: , Parallel Execution, Softcore Processors, VLIW Processors, Run-time Reconfiguration, Fault Tolerance, Customization, Parametriza- tion, FPGAs, Trade-offs

Cover page designed by Hanike (www.hanike.nl).

Copyright c 2013 Fakhar Anjam

All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without permission of the author.

Printed in The Netherlands To my father and all other members of my family Summary

In this dissertation, we propose to combine programmability with reconfig- urability by implementing an adaptable programmable VLIW in a reconfigurable hardware. The approach allows applications to be developed at high-level (C language level), while at the same time, the processor organiza- tion can be adapted to the specific requirements (both static and dynamic) of different applications. Our proposed customizable VLIW processor called ρ-VEX can be adapted at design-time as well as at run-time. Its instruction set architecture (ISA) is based on the VEX ISA and a toolchain (parametrized C compiler and sim- ulator) is publicly available from Hewlett Packard (HP) for architectural ex- ploration and code generation. The design-time parameters include the pro- cessor’s issue-width, the type of different functional units (FUs) and their la- tencies, the type and size of multiported register files, degree of pipelining, size of instruction and data memories, type of interrupt and exception systems, selection of default custom operations, sharing. If the behavior of applications is not known at design-time or an application has different phases with distinct requirements, a fixed processor may not perform efficiently for all the applications/phases. To this end, we propose a run-time reconfigurable processor that can adapt its organization dynamically during execution. The run-time parameters include the processor’s issue-width,