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Front cover Eserver IBM p5 590 and 595 System Handbook Component-based description of the hardware architecture A guide for machine type 9119 models 590 and 595 Capacity on Demand explained Peter Domberg Nia Kelley TaiJung Kim Ding Wei ibm.com/redbooks International Technical Support Organization IBM Eserver p5 590 and 595 System Handbook March 2005 SG24-9119-00 Note: Before using this information and the product it supports, read the information in “Notices” on page xv. First Edition (March 2005) This edition applies to the IBM Sserver p5 9119 Models 590 and 595. © Copyright International Business Machines Corporation 2005. All rights reserved. Note to U.S. Government Users Restricted Rights -- Use, duplication or disclosure restricted by GSA ADP Schedule Contract with IBM Corp. Contents Figures . ix Tables . xiii Notices . xv Trademarks . xvi Preface . xvii The team that wrote this redbook. xvii Become a published author . xix Comments welcome. xx Chapter 1. System overview. 1 1.1 Introduction . 2 1.2 What’s new . 2 1.3 General overview and characteristics . 4 1.3.1 Microprocessor technology . 6 1.3.2 Memory subsystem . 8 1.3.3 I/O subsystem . 9 1.3.4 Media bays . 10 1.3.5 Virtualization . 11 1.4 Features summary . 12 1.5 Operating systems support . 13 1.5.1 AIX 5L . 13 1.5.2 Linux . 14 Chapter 2. Hardware architecture . 17 2.1 Server overview. 18 2.2 The POWER5 microprocessor . 18 2.2.1 Simultaneous multi-threading . 20 2.2.2 Dynamic power management . 21 2.2.3 The POWER chip evolution . 21 2.2.4 CMOS, copper, and SOI technology. 24 2.2.5 Processor books . 24 2.2.6 Processor clock rate . 25 2.3 Memory subsystem . 26 2.3.1 Memory cards . 28 2.3.2 Memory placement rules. 28 2.4 Central electronics complex . 30 © Copyright IBM Corp. 2005. All rights reserved. iii 2.4.1 CEC backplane . 33 2.5 System flash memory configuration . 36 2.6 Vital product data and system smart chips . 36 2.7 I/O drawer. 37 2.7.1 EEH adapters and partitioning . 38 2.7.2 I/O drawer attachment. 38 2.7.3 Full-drawer cabling . 40 2.7.4 Half-drawer cabling . 41 2.7.5 blind-swap hot-plug cassette. 43 2.7.6 Logical view of a RIO-2 drawer . 44 2.7.7 I/O drawer RAS . 46 2.7.8 Supported I/O adapters in p5-595 and p5-590 systems . 47 2.7.9 Expansion units 5791, 5794, and 7040-61D . 50 2.7.10 Configuration of I/O drawer ID and serial number. 54 Chapter 3. POWER5 virtualization capabilities. 57 3.1 Virtualization features . 58 3.2 Micro-Partitioning . 58 3.2.1 Shared processor partitions . 59 3.2.2 Types of shared processor partitions . 62 3.2.3 Typical usage of Micro-Partitioning technology. 64 3.2.4 Limitations and considerations . 64 3.3 Virtual Ethernet . 65 3.3.1 Virtual LAN . 66 3.3.2 Virtual Ethernet connections . 70 3.3.3 Dynamic partitioning for virtual Ethernet devices . 72 3.3.4 Limitations and considerations . 72 3.4 Shared Ethernet Adapter. 73 3.4.1 Connecting a virtual Ethernet to external networks. 73 3.4.2 Using Link Aggregation (EtherChannel) to external networks . 77 3.4.3 Limitations and considerations . 79 3.5 Virtual I/O Server. 79 3.6 Virtual SCSI. 81 3.6.1 Limitations and considerations . 82 Chapter 4. Capacity on Demand . 85 4.1 Capacity on Demand overview . 86 4.2 What’s new in Capacity on Demand? . 86 4.3 Preparing for Capacity on Demand . 87 4.3.1 Step 1. Plan for future growth with inactive resources . 87 4.3.2 Step 2. Choose the amount and desired level of activation . 88 4.4 Types of Capacity on Demand . 89 4.5 Capacity BackUp. 90 iv IBM Eserver p5 590 and 595 System Handbook 4.6 Capacity on Demand activation procedure . 91 4.7 Using Capacity on Demand. 93 4.7.1 Using Capacity Upgrade on Demand . 93 4.7.2 Using On/Off Capacity On Demand . 94 4.7.3 Using Reserve Capacity on Demand . 98 4.7.4 Using Trial Capacity on Demand . 99 4.8 HMC Capacity on Demand menus . 100 4.8.1 HMC command line functions . 103 4.9 Capacity on Demand configuration rules . 103 4.9.1 Processor Capacity Upgrade on Demand configuration rules . 103 4.9.2 Memory Capacity Upgrade on Demand configuration rules . 104 4.9.3 Trial Capacity on Demand configuration rules . 104 4.9.4 Dynamic processor sparing. 105 4.10 Software licensing considerations . 105 4.10.1 License entitlements for permanent processor activations . 106 4.10.2 License entitlements for temporary processor activations . 107 4.11 Capacity on Demand feature codes . ..
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