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Implementation of Designed Encoder and Decoder for Golay Code

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Implementation of Designed Encoder and Decoder for Golay Code International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 04 Issue: 11 | Nov -2017 www.irjet.net p-ISSN: 2395-0072 Implementation of Designed Encoder and Decoder for Golay Code vaibhav chandrakar1,Mr. sanjeev shrivastava2, Dr. Mohit gangwar3, Mr. Suresh Gawande4 ---------------------------------------------------------------------------------***----------------------------------------------------------------------------- Abstract— In the wireless communication system the interference, attenuation, bit synchronization problems, receiver has the ability to detect and correct the error from wireless multipath fading, etc. By choosing strong signal the received information. Receiving the error is an strength the BER may be improved (unless this causes more important issue, so it provides the processor for correcting bit errors and cross-talk), by choosing a robust modulation the information of the data. There are some different scheme and slow or line coding scheme, and by applying methods for the implementation of the hardware and channel coding schemes such as redundant forward error software. The communication distance between transmitter correction codes. An efficient hardware implementation of and receiver play an important role because the encoding the algorithm in field FPGA prototype for both transmission of data between transmitter and receiver binary Golay code (g23) and extended binary golay code depends on length of communication. Multiple bits of (g24). The high speeds architecture with low latency have information transmitted from transmitter changed due to been designed and implemented in a virtex-4 which are the effect of noise in transmitted signal. This causes intense explained in reference [1]. This hardware’s module for both loss in many of the cases. This paper presents the brief the encoder and decoder may be good candidates for explanation of FPGA (Field Programmable Gate Array) different application in high speed communication link, photo based simulation and design of Golay Code (G23) and spectroscopy, and ultrasonography. extended Golay code (G24) Encoding scheme. For encoding the data packet this paper use the Golay Encoder for the II. GOLAY CODE optimization of the time delay of the operational circuit design to encode the data packet. A binary Golay code is represented by (23, 12, 7) shows length of the codeword is 23 bit while message is shown by I. INTRODUCTION 12 bits and the minimum distance between two binary Golay code is7. Build a binary codes in Galois field denoted by GF(2) In digital transmission, bit errors were begin due to the which support the different binary operation. The coding change of bits at the time of transmission of data over sequence is generated by Generator polynomial [13] over communication channels and the bit has been changed due GF(2) for Golay code (23, 12, 7) code are x11 + x10 + x6 + x5 to noise, distortions, interference, or bits synchronization + x4 + x2 + x1 and x11+ x9+ x7+ x6+ x5+ x1+ 1 error. This can be explaining by taking an example of transmitted bits sequence as follows: This paper shows AE3h as characteristic polynomial which is of 12 bit binary number can be encoded into a 23-bit Golay code by using the long division method to generate check bits 0 1 1 0 1 0 1 0 1 1 (11-bit) information and 12 bit data together make the Golay code of 12-bit information data. A extended Golay code (24, 12, 8) produced by adding a parity bit with the binary Golay And the following received bit sequence: code or using as a generator matrix G. Matrix G is defined by [I, B] or [I, B] where I is shown as Identity matrix and B is 0 0 1 1 1 1 1 0 0 1 shown as Matrix. The matrix B is shown in figure below- Figure 1.2- Transmitted and Received bit sequence 110111000101 101110001011 011100010111 The number of bit error (the colored bit) in this case, 4. 111000010111 The Bit Errors Rate is 4 incorrect bits divided by 10 110001011011 reassigns the bits, resultant in a BER of 0.4 or 40%. Here B= 100010110111 the description of bits error rate (BER) is the number of 000101101111 bits error per unit time. The bits error ratio (also BER) is 001011011101 010110111001 defined as the number of bit errors divided by the total 101101110001 numbers of transferred bits during a considered time 011011100011 interval. BER is expressed in percentage. 111111111110 In digital communication systems, BER at the receiver side Figure 3.1-Matrix-B may be affected by transmission channel noise, distortion, © 2017, IRJET | Impact Factor value: 6.171 | ISO 9001:2008 Certified Journal | Page 1454 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 04 Issue: 11 | Nov -2017 www.irjet.net p-ISSN: 2395-0072 The steps of algorithm required to achieve the encoding The proposed encoder algorithm clearly follows the basic procedure as follows- CRC generation process and includes a method for converting binary Golay code to extended Golay code before proceeding A characteristic polynomial is preferred for check bits for designing architecture. An example of Golay code word generation. ‘M’ bit of data contribute in long division generation based on the above mentioned algorithm is shown method with the characteristic polynomial. So 11 zero are in Fig. 1. Let us say, the message to be encoded is A27h. appended to the right of the m bit of data. Checks bit for Hence, M(x) = A27h and P(x) in binary format is represented G(23) are achieved by MSB result at the end of the long as 1010 0010 0111 0000 0000 000. Finally, the generated division method. By appending the check bits with the check bits in hexadecimal format are 435h. Hence, the message the encoded Golay code (23, 12, 7) codeword are encoded codeword for the message bits (A27h) is A27435h. obtained. A parity bit is added for conversion of binary This is a binary Golay code word. To convert it into an Golay code into extended binary Golay code (24, 12, 8). If extended Golay code, a parity bit 1 is appended, as weight of the weight of binary Golay codes are odd then parity bits 1 A27435h is 11 (odd). Finally, the generated Golay (24, 12, 8) is appended, otherwise 0 is appended. codeword is (1010 0010 0111 10000110 101 1). The validity of the generated Golay code can be tested by measuring the III. ALGORITHM, PROPOSED ARCHITECTURE, AND weight of the code. The weight of every G24 code should be a COMPARISON OF RESULTS FOR GOLAY ENCODER multiple of four and greater than equal to eight. The generated code word shown in the example has a weight of A. Proposed Algorithm for Encoder 12, which is a multiple of four and greater than eight. Hence, the generated code is valid and thus the algorithm. The steps required to accomplish the encoding procedure are enlisted as follows. B. Proposed Architecture for Binary Golay Code and Extended Golay Code 1) A characteristic polynomial G(x) is chosen for check bits generation. In this section, optimized architectures for encoder are shown in Figs. 2 and 3. The whole architecture is partitioned 2) 11 zeros are appended to the right of message M(x), into two parts, one for G23 generation and the other showing such that resultant polynomial P(x) participates in conversion of G23 to G24. In each step during polynomial long division process with G(x). division, simply binary XOR operation occurs for modulo-2 subtraction. The residual result obtained at each step during 3) The remainder bits except the most significant bit the division process is circularly left shifted by number of (MSB) resulted at the end of the division operation leading zeros present in the result. A 12:4 priority encoder is used to detect efficiently the number of leading zeros before are the check bits for G . Appending check bits with 23 first 1 bit in the residual result in each step. A circular shift the message gives us the encoded Golay (23, 12, 7) register is used to shift the intermediate result by the output codeword. of priority encoder. A 2:1 multiplexer is used to select the initial message or the circularly shifted intermediate result. 4) A parity bit is added to convert the binary Golay code The control signal used for the multiplexer and the controlled into extended binary Golay code (24, 12, 8). If the subtractor is denoted as p, which is bit wise OR operation of weight of binary Golay code is even, then parity bit 0 priority encoder output. A controlled subtractor is used for is appended, otherwise 1 is appended. loop control mechanism. Initially, one input of subtractor is initialized with 11, which is the number of zeros appended in the first step of the long division process and it gets updated with the content of R7 register due to multiplexer selection after each iteration. The output of the priority encoder is the other input to the subtractor. After the final iteration, the result of subtractor is zero, which is stored in register R7. The register R6 is loaded when the content of register R7 becomes zero, which depicts the end of the division process and hence the check bits generation process. The Ld control signal controls the loading of the R3 [10:0] Fig. 3.1. Example of check bits generation. © 2017, IRJET | Impact Factor value: 6.171 | ISO 9001:2008 Certified Journal | Page 1455 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 04 Issue: 11 | Nov -2017 www.irjet.net p-ISSN: 2395-0072 Data (12-bit) Appended zeros Operation S[11] = w[23] xor w[11] xor w[10] xor w[8] xor w[7] xor w[6] xor w[2] xor w[0] 101000100111
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