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Cyclic Redundancy Code Theory

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Cyclic Redundancy Code Theory Appendix A CYCLIC REDUNDANCY CODE THEORY “It is hard to establish . who did what first. E. N. Gilbert of the Bell Telephone Laboratories derived much of linear theory a year or so earlier than either Zierler, Welch, or myself, . the first investigation of linear recurrence relations modulo p goes back as far as Lagrange, in the eighteenth century, and an excellent modern treatment was given ( . purely mathematical . ) by Marshall Hall in 1937.” — Solomon W. Golomb [264]. Cyclic redundancy code theory is described in this appendix because it is im- portant for built-in self-testing (BIST), and for Memory ROM testing. Cyclic re- dundancy codes have been extensively used for decades in the computer industry to guarantee correct recording of blocks on disk and magnetic tape drives. They also are extensively used for encoding and decoding communication channel burst errors, where a transient fault causes several adjacent data errors. Preliminaries. We express the binary vector as the polynomial As an example, 10111 is written as [36, 37]. The degree of the polynomial is the superscript of the highest non-zero term. Polynomial addition and subtraction arithmetic is performed similarly to integer arithmetic, except that the arithmetic is modulo 2. In this case, addition and subtraction will have the same effect. As an example, let (degree 3) and (degree 2.) We can describe the remainders of polynomials modulus a polynomial. Two polynomials r(x) and s(x) will be congruent modulus polynomial n(x), written 616 Appendix A. CYCLIC REDUNDANCY CODE THEORY as mod n(x) if a polynomial q(x) such that We find the residue (the remainder) by dividing r(x) by n(x). For example: So, Irreducible polynomials cannot be factored and are analogous to the prime integer numbers. A.1 Polynomial Multiplier Figure A.1 (a) shows a polynomial multiplier, used as an encoding circuit to create a cyclic code. The code has the property that any end-around shift of a code word produces another code word. The code has these properties: • It has a Boolean generator polynomial G(x) of degree n – k or greater, where n is the number of bits in the complete code word and k is the number of bits in the original information to be encoded. Coefficients of G(x) are 0 or 1. This is called an (n, k) cyclic code, and it is able to detect all single errors and all multiple adjacent errors in transmission of the code word. • The cyclic code represents data as a Boolean polynomial, as described above. The code word is the coefficients of a polynomial so An n-bit code word is represented by a polynomial of degree n – 1 or less. V(x) is called the code polynomial of the code word V. We generate code polynomials by multiplying a polynomial representing the data to be encoded by the generator polynomial. Example A.1 We wish to encode the binary word (1101) In this case, the generator polynomial is The code polynomial is: The code is the coefficient set (1010001). A.2 Polynomial Divider 617 Figure A.1: Boolean polynomial multiplier and realization. Cyclic codes are non-separable codes, which means that it is not possible to decode the data by simply dropping extra code bits. The Hamming distance is the distance between adjacent code words, in terms of the number of bit changes. This is found for a cyclic code by comparing all possible code word pairs and determining the min- imum Hamming distance between any two code words. The system of Figure A.1 (a) performs polynomial multiplication for the generator In this number system, we implement multiplication by x with a time shift using a D flip-flop, and we implement the modulo-2 addition operator with an EXCLUSIVE-OR logic gate. The data to be encoded appears serially on D(x), and the bits of the encoded word appear serially on V(x). Initially, the registers in the circuit must be initialized to 0 before encoding can occur. Figure A.1(b) is an implementation of the polynomial multiplier of Figure A.1 (a). Table A.1 shows the code words generated by this system. A.2 Polynomial Divider Figure A.2(a) shows a polynomial divider, used as a decoding circuit. It is the companion circuit to the encoder of Figure A.1 (a). In the decoding procedure, we treat the code word as a Boolean polynomial, but now we divide it by the generator polynomial and determine the remainder, as well as the quotient, of the division. If the remainder is 0, then the code word was valid. A non-zero remainder indicates a transmission error. Here the code word again represents the polynomial We obtained S(x) when we encoded the data D(x) by multiplying by the generator G(x), using is the syndrome polynomial, which should be 0 during encoding. Figure A.2(a) shows the conceptual division circuit, again using 618 Appendix A. CYCLIC REDUNDANCY CODE THEORY Here, so: Since this is a modulo-2 addition system, adding the same quantity to both sides of the equation has the same effect as subtracting the same quantity from both sides of the equation. Figure A.2(b) shows the division circuit, and Table A.2 shows the results of decoding a code word V(x). Figure A.2: Boolean polynomial divider and realization. Appendix B PRIMITIVE POLYNOMIALS OF DEGREE 1 TO 100 The primitive polynomials shown below in Table B.1 were taken from the book by Bardell et al. [67]. They, in turn, obtained the first 100 polynomials from Stahnke [633]. To decode the table, consider that the entry 12: 7430 represents the polynomial as each table entry represents a term exponent. Since there is always a term for it is not represented. Notice that there is always an term, but it is shown for consistency reasons. In the unlikely event that a polynomial of degree greater than 100 is needed, consult Bardell et al. [67] for polynomials of degree up to 300. 620 Appendix B. PRIMITIVE POLYNOMIALS OF DEGREE 1 TO 100 Appendix C BOOKS ON TESTING C.1 General and Tutorial • M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design. Piscataway, New Jersey: IEEE Press, 1994. Revised printing. • V. D. Agrawal and S. C. Seth, Tutorial: Test Generation for VLSI Chips. Los Alamitos, California: IEEE Computer Society Press, 1988. • J. DiGiacomo, editor, VLSI Handbook. New York: McGraw-Hill, 1989. • N. G. Einspruch, editor, VLSI Handbook. Orlando, Florida: Academic Press, 1985. • W. G. Fee, Tutorial: LSI Testing. Los Alamitos, California: IEEE Computer Society Press, 1978. • A. D. Friedman and P. R. Menon, Fault Detection in Digital Circuits. Upper Saddle River, New Jersey: Prentice-Hall, 1971. • H. Fujiwara, Logic Testing and Design for Testability. Cambridge, Massachusetts: MIT Press, 1985. • Z. Kohavi, Switching and Automata Theory. New York: McGraw-Hill, 1978. • L. Lavagno and A. Sangiovanni-Vincentelli, Algorithms for Synthesis and Testing of Asynchronous Circuits. Boston: Kluwer Academic Publishers, 1993. • F. Lombardi and M. Sami, editors, Testing and Diagnosis of VLSI and ULSI. Boston: Kluwer Academic Publishers, 1988. • R. E. Massara, editor, Design & Test Techniques for VLSI & WSI Circuits. London, United Kingdom: Peter Peregrinus, 1989. • E. J. McCluskey, Logic Design Principles With Emphasis on Testable Semicustom Cir- cuits. Upper Saddle River, New Jersey: Prentice-Hall, 1986. • A. Miczo, Digital Logic Testing and Simulation. New York: Harper & Row, 1986. • D. M. Miller, Developments in Integrated Circuit Testing. San Diego, California: Aca- demic Press, 1987. • S. Mourad and Y. Zorian, Principles of Testing Electronic Systems. Somerset, New Jersey: John Wiley & Sons Inc., 2000. • H. K. Reghbati, Tutorial: VLSI Testing & Validation Techniques. Los Alamitos, Cali- fornia: IEEE Computer Society Press, 1985. • G. Russel and I. L. Sayers, Advanced Simulation and Test Methodologies for VLSI Design. London, United Kingdom: Van Nostrand Reinhold, 1989. • B. R. Wilkins, Testing Digital Circuits, An Introduction. Berkshire, United Kingdom: Van Nostrand Reinhold, 1986. 622 Appendix C. BOOKS ON TESTING • T. W. Williams, editor, VLSI Testing. Amsterdam, The Netherlands: North-Holland, 1986. C.2 Analog and Mixed-Signal Circuit Test • A. Afshar, Principles of Semiconductor Network Testing. Boston: Butterworth- Heinemann, 1995. • M. Burns and G. Roberts, Introduction to Mixed-Signal IC Test and Measurement. New York: Oxford University Press, 2000. • B. Kaminska and B. Courtois, editors, Special Issue on Analog and Mixed Signal Testing, volume 9 of Journal of Electronic Testing: Theory and Applications. Boston: Kluwer Academic Publishers, August-October 1996. • R. W. Liu, editor, Selected Papers on Analog Fault Diagnosis. Piscataway, New Jersey: IEEE Press, 1987. • R. W. Liu, editor, Testing and Diagnosis of Analog Circuits and Systems. New York: Van Nostrand Reinhold, 1991. • M. Mahoney, DSP-Based Testing of Analog and Mixed-Signal Circuits. Los Alamitos, California: IEEE Computer Society Press, 1987. • A. Osseiran, Analog and Mixed-Signal Boundary-Scan. Boston: Kluwer Academic Pub- lishers: 1999. • T. Ozawa, editor, Analog Methods for Computer-Aided Circuit Analysis and Diagnosis. New York: Marcel Dekker, 1988. • G. W. Roberts and A. K. Lu, Analog Signal Generation for Built-In Self-Test of Mixed- Signal Integrated Circuits. Boston: Kluwer Academic Publishers, 1995. • M. Soma, editor, Special Issue on Analog and Mixed-Signal Testing, volume 4 of Journal of Electronic Testing: Theory and Applications. Boston: Kluwer Academic Publishers, November 1993. • B. Vinnakota, editor, Analog and Mixed-Signal Test. Upper Saddle River, New Jersey: Prentice-Hall PTR, 1998. C.3 ATE, Test Programming, and Production Test • J. H. Arabian, Computer Integrated Electronics Manufacturing and Testing. New York: Marcel Dekker, 1989. • J. Bateson, In-Circuit Testing. New York: Van Nostrand Reinhold, 1985.
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