DOCSLIB.ORG

Operating Systems Summary Bibliography

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Operating Systems Summary Bibliography Today memories NVRAM NVRAM and operating systems Summary Bibliography Operating System Implications of Fast, Cheap, Non-Volatile Memory Adam Morawski MIMUW 2012-01-16 Adam Morawski Operating System Implications of Fast, Cheap, Non-Volatile Memory Today memories Hard disk NVRAM Flash memory NVRAM and operating systems SRAM Summary DRAM Bibliography Hard disk Very cheap, very big capacities available Very big latencies (3000000ns) Read and write only whole blocks (512B - few kB) Very bad performance while using randomly placed small amounts of data (can’t be operating memory) Delicate, high power mechanical device Adam Morawski Operating System Implications of Fast, Cheap, Non-Volatile Memory Today memories Hard disk NVRAM Flash memory NVRAM and operating systems SRAM Summary DRAM Bibliography Flash memory Cheap, big capacities on small chips available Fast read (70ns), even small randomly placed data Slow write (2500ns/block), only whole blocks - can’t be operating memory Limited durability (104 - 107 single block writes - high voltage, data retention of about 20 years) Adam Morawski Operating System Implications of Fast, Cheap, Non-Volatile Memory Today memories Hard disk NVRAM Flash memory NVRAM and operating systems SRAM Summary DRAM Bibliography SRAM Static Random Access Memory random access to single bytes/words can be very fast (2ns), while not writing current can be very low (memory cells are made of logic gates) volatile (can’t be reliable data store) expensive, small capacities, memory cells are big Adam Morawski Operating System Implications of Fast, Cheap, Non-Volatile Memory Today memories Hard disk NVRAM Flash memory NVRAM and operating systems SRAM Summary DRAM Bibliography DRAM Dynamic RAM like SRAM but a little bit slower cheap, big capacities available, small cells size volatile must be refreshed, clock frequency can’t be changed in wide range not neglible power consumption (cells are made of capacitors and driving transistors) Adam Morawski Operating System Implications of Fast, Cheap, Non-Volatile Memory Today memories NVRAM Resistance-based memories NVRAM and operating systems Other ideas Summary Bibliography MRAM Magnetoresistive RAM In development from 90-ies Resistance change depending on magnetization Random access, non-volatile, fast, durable Commercially available but can’t compete with DRAM EverSpin Technologies MR2A16AVYS35: 4Mb, 35ns, $20 (500 pcs) - $30 (1 pc) Adam Morawski Operating System Implications of Fast, Cheap, Non-Volatile Memory Today memories NVRAM Resistance-based memories NVRAM and operating systems Other ideas Summary Bibliography Memristor Fourth fundamental passive electronic component Resistance as a function of previous charge flow Theoretically predicted in 1971 Made in 2008 (HP Labs, titanium dioxide) Memory: non-volatile, random access, can be clocked up to 1GHz In november 2011 commercial availability in 18 mounths announced Adam Morawski Operating System Implications of Fast, Cheap, Non-Volatile Memory Today memories NVRAM Resistance-based memories NVRAM and operating systems Other ideas Summary Bibliography Phase Change Memory Resistance change depending on way of heating material Promising predictions but big current needed to write Prototypes: IBM, june 2011, 200kb, good properties Hybrid technologies (with MEMS) - 512Mb prototypes Limited durability! (108 writes - heat) Adam Morawski Operating System Implications of Fast, Cheap, Non-Volatile Memory Today memories NVRAM Resistance-based memories NVRAM and operating systems Other ideas Summary Bibliography FeRAM Ferroelectric RAM Changing crystal properties with current, read as energy measuring while writing Non-volatile, random access, low power, fast (< 10ns) Durability up to 1016 cycles, has to be refreshed after read, big cell size Fujitsu MB85R1002ANC-GE1: 1Mb, 150ns, ok $10 Adam Morawski Operating System Implications of Fast, Cheap, Non-Volatile Memory In 2008 working 3-bit prototype (IBM) Today memories NVRAM Resistance-based memories NVRAM and operating systems Other ideas Summary Bibliography Racetrack memory Magnetic domains movement in thin ferromagnetic wire Non-volatile, almost random access, durable Predictions: access time down to 30ns, density like in HDDs, throughput worse than in DRAM Adam Morawski Operating System Implications of Fast, Cheap, Non-Volatile Memory Today memories NVRAM Resistance-based memories NVRAM and operating systems Other ideas Summary Bibliography Racetrack memory Magnetic domains movement in thin ferromagnetic wire Non-volatile, almost random access, durable Predictions: access time down to 30ns, density like in HDDs, throughput worse than in DRAM In 2008 working 3-bit prototype (IBM) Adam Morawski Operating System Implications of Fast, Cheap, Non-Volatile Memory Possible architectures Today memories System kernel NVRAM File system NVRAM and operating systems Machine state Summary Data portability Bibliography Safety, privacy etc Possible architectures NVRAM as data store NVRAM and DRAM in common address space (NUMA) only NVRAM Adam Morawski Operating System Implications of Fast, Cheap, Non-Volatile Memory Possible architectures Today memories System kernel NVRAM File system NVRAM and operating systems Machine state Summary Data portability Bibliography Safety, privacy etc System kernel Taking into account memory cells wearing-off (wear-leveling) No need of swapping Is there a need of paging? Adam Morawski Operating System Implications of Fast, Cheap, Non-Volatile Memory Possible architectures Today memories System kernel NVRAM File system NVRAM and operating systems Machine state Summary Data portability Bibliography Safety, privacy etc File system Capability of random access, not only to whole blocks Common address space with executed code and program-allocated memory Other bottle-necks, optimalisations In some cases there is no need to load some data to memory Is there a need for virtual memory (malloc) and data-store (fopen) division? Are files needed at all? Adam Morawski Operating System Implications of Fast, Cheap, Non-Volatile Memory Possible architectures Today memories System kernel NVRAM File system NVRAM and operating systems Machine state Summary Data portability Bibliography Safety, privacy etc Machine state Machine/program state more durable than with volatile memory In memory we can store program state (with code), not only code that is loaded to memory and executed to initialise this program state More options while rebooting/powering off - some pieces of system can save their state Wrong program can destroy itself unrecoverably - data structures corruption is non-volatile too Mayby some repair mechanisms are needed (checkpoints+event log) Adam Morawski Operating System Implications of Fast, Cheap, Non-Volatile Memory Possible architectures Today memories System kernel NVRAM File system NVRAM and operating systems Machine state Summary Data portability Bibliography Safety, privacy etc Machine state - installation, update, repair Installing program as image, state (checkpoint), stopped program doesn’t have to be present in other form than running - program starting is not needed Saving checkpoints (to repair or update) - while there is as few dependencies of system as possible How to update - parallel checkpoints, hot-patching, old way - restart needed Existing mechanisms of running programs moving between machines can be used (COW...) Adam Morawski Operating System Implications of Fast, Cheap, Non-Volatile Memory Possible architectures Today memories System kernel NVRAM File system NVRAM and operating systems Machine state Summary Data portability Bibliography Safety, privacy etc Data portability Single address space make harder direct data migration between machines Sending data only through network, with specialised protocols or.. as files Adam Morawski Operating System Implications of Fast, Cheap, Non-Volatile Memory Possible architectures Today memories System kernel NVRAM File system NVRAM and operating systems Machine state Summary Data portability Bibliography Safety, privacy etc Safety, privacy etc Cold-boot attack prone Easier investigation after failure/attack (checkpoints, durable program state) Programmer have to has control of data (non)volatility Maybe some volatile memory has to be leaved for encryption keys etc Adam Morawski Operating System Implications of Fast, Cheap, Non-Volatile Memory Today memories NVRAM Almost as NVRAM - PalmOS NVRAM and operating systems NVRAM opportunities Summary Bibliography Almost as NVRAM - PalmOS Everything in battery-supported DRAM No normal filesystem - only programs and their databases Execution in place Program state saved between application starts/context changes though there is no multitasking Program state can survive even cold-reset or be back-uped while synchronizing Palm with PC User point of view: there is no file saving operation - you are working on the only existing copy Adam Morawski Operating System Implications of Fast, Cheap, Non-Volatile Memory Today memories NVRAM Almost as NVRAM - PalmOS NVRAM and operating systems NVRAM opportunities Summary Bibliography Almost as NVRAM - PalmOS ”Turning off”: stopping CPU and some other pieces of hardware ”Turning on”: partial hardware initialisation, return to recently executed code Differences with NVRAM are visible while battery is disconnected or exhausted: data durability, no cold-boot attack risk Adam Morawski Operating System Implications of Fast, Cheap, Non-Volatile Memory there can be a chance while DRAM will reach physical boundaries Today memories NVRAM
Load more

Recommended publications
  • Multilevel-Cell Phase-Change Memory - Modeling and Reliability Framework
    MULTILEVEL-CELL PHASE-CHANGE MEMORY - MODELING AND RELIABILITY FRAMEWORK THÈSE NO 6801 (2016) PRÉSENTÉE LE 14 JANVIER 2016 À LA FACULTÉ DES SCIENCES ET TECHNIQUES DE L'INGÉNIEUR LABORATOIRE DE SYSTÈMES MICROÉLECTRONIQUES PROGRAMME DOCTORAL EN GÉNIE ÉLECTRIQUE ÉCOLE POLYTECHNIQUE FÉDÉRALE DE LAUSANNE POUR L'OBTENTION DU GRADE DE DOCTEUR ÈS SCIENCES PAR Aravinthan ATHMANATHAN acceptée sur proposition du jury: Prof. G. De Micheli, président du jury Prof. Y. Leblebici, Dr M. Stanisavljevic, directeurs de thèse Dr E. Eleftheriou, rapporteur Dr R. Bez, rapporteur Dr J. Brugger, rapporteur Suisse 2016 All birds find shelter during a rain . But eagle avoids rain by flying above the clouds . Problems are common, but attitude makes the difference . — Dr. A. P.J. Abdul Kalam To my parents and wife. Acknowledgements This accomplishment would not have been possible without the wonderful people who have inspired me on my journey towards the PhD. This PhD challenge would have been more of an academic title than a great adventure if not for them. I consider myself fortunate to have spent the last four years of my life in a great research atmosphere for learning, and also working with some exceptional individuals during the course of my doctoral studies. I am greatly indebted to my supervisor, Prof. Yusuf Leblebici, who gave me the independence to pursue my ideas freely, while at the same time mentoring by example. I am especially grateful to my manager, Dr. Evangelos Eleftheriou, for giving me this wonderful opportunity to pursue my PhD thesis with IBM Research. His energy and enthusiasm have been an inspiration for me to aim ever higher in my pursuits.
    [Show full text]
  • ROSS: a Design of Read-Oriented STT-MRAM Storage for Energy
    ROSS: A Design of Read-Oriented STT-MRAM Storage for Energy-Efficient Non-Uniform Cache Architecture Jie Zhang, Miryeong Kwon, Chanyoung Park, Myoungsoo Jung, and Songkuk Kim School of Integrated Technology, Yonsei Institute Convergence Technology, Yonsei University [email protected], [email protected], [email protected], [email protected], [email protected] Abstract high leakage power. With increasing demand for larger caches, SRAM is struggling to keep up with the density Spin-Transfer Torque Magnetoresistive RAM (STT- and energy-efficiency requirements set by state-of-the- MRAM) is being intensively explored as a promis- art system designs. ing on-chip last-level cache (LLC) replacement for Thanks to the device-level advantages of STT-MRAM SRAM, thanks to its low leakage power and high stor- such as high-density structure, zero leakage current, and age capacity. However, the write penalties imposed by very high endurance, it comes out as an excellent candi- STT-MRAM challenges its incarnation as a successful date to replace age-old SRAM for LLC design. However, LLC by deteriorating its performance and energy effi- the performance of STT-MRAM is critically sensitive to ciency. This write performance characteristic unfortu- write frequency due to its high write latency and energy nately makes STT-MRAM unable to straightforwardly values. Therefore, an impulsive replacement of SRAM substitute SRAM in many computing systems. with high-density STT-MRAM, simply for increasing In this paper, we propose a hybrid non-uniform cache LLC capacity, can deteriorate cache performance and in- architecture (NUCA) by employing STT-MRAM as a troduce poor energy consumption behavior.
    [Show full text]
  • Non-Volatile Memory Databases
    15-721 ADVANCED DATABASE SYSTEMS Lecture #24 – Non-Volatile Memory Databases Andy Pavlo // Carnegie Mellon University // Spring 2016 @Andy_Pavlo // Carnegie Mellon University // Spring 2017 2 ADMINISTRIVIA Final Exam: May 4th @ 12:00pm → Multiple choice + short-answer questions. → I will provide sample questions this week. Code Review #2: May 4th @ 11:59pm → We will use the same group pairings as before. Final Presentations: May 9th @ 5:30pm → WEH Hall 7500 → 12 minutes per group → Food and prizes for everyone! CMU 15-721 (Spring 2017) 3 TODAY’S AGENDA Background Storage & Recovery Methods for NVM CMU 15-721 (Spring 2017) 4 NON-VOLATILE MEMORY Emerging storage technology that provide low latency read/writes like DRAM, but with persistent writes and large capacities like SSDs. → AKA Storage-class Memory, Persistent Memory First devices will be block-addressable (NVMe) Later devices will be byte-addressable. CMU 15-721 (Spring 2017) 5 FUNDAMENTAL ELEMENTS OF CIRCUITS Capacitor Resistor Inductor (ca. 1745) (ca. 1827) (ca. 1831) CMU 15-721 (Spring 2017) 6 FUNDAMENTAL ELEMENTS OF CIRCUITS In 1971, Leon Chua at Berkeley predicted the existence of a fourth fundamental element. A two-terminal device whose resistance depends on the voltage applied to it, but when that voltage is turned off it permanently remembers its last resistive state. TWO CENTURIES OF MEMRISTORS Nature Materials 2012 CMU 15-721 (Spring 2017) 7 FUNDAMENTAL ELEMENTS OF CIRCUITS Capacitor Resistor Inductor Memristor (ca. 1745) (ca. 1827) (ca. 1831) (ca. 1971) CMU 15-721 (Spring 2017) 8 MERISTORS A team at HP Labs led by Stanley Williams stumbled upon a nano-device that had weird properties that they could not understand.
    [Show full text]
  • Non-Volatile Memory Technology Continue to Scale Up
    MEMORY Non-volatile Memory Technology Continue to Scale Up The emergence of new Non-Volatile memory technology promises to improve performance, efficiency that matches with ideal characteristics. The article reviews some of new non-volatile memory technologies. PADAM RAO RAM, DRAM and Flash are three Landscape dominating memory technologies and With respect to ideal characteristics of memory each technology has some advantages technology described above, till now all known and disadvantages. The ideal memory S memory/storage technologies address only some technology should have low power of the characteristics. Static RAM (SRAM) is very consumption, high performance, high reliability, fast, but it's expensive, has low density and is not high density, low cost, and the ability to be used in any semiconductor memory application. persistent. Dynamic RAM (DRAM) has better Besides computers, today’s portable electronics densities and is cheaper (but still expensive) at the have become computationally intensive devices as cost of being a little slower, and it's not persistent as the user interface has migrated to a fully well. Disks are cheap, highly dense and persistent, multimedia experience. To provide the but very slow. Flash memory is between DRAM and performance required for these applications, the disk; it is a persistent solid-state memory with higher portable electronics designer uses multiple types of densities than DRAM, but its write latency is much memories: a medium-speed random access higher than the latter. memory for continuously changing data, a high- Fortunately, it is possible to design a memory system speed memory for caching instructions to the CPU, that incorporates all these different technologies in and a slower, non-volatile memory for long-term a single memory hierarchy.
    [Show full text]
  • Eighth Edition (2006) Core Level
    International Patent Classification Eighth Edition (2006) Core Level Volume 4 Section H Electricity World Intellectual Property Organization BASIC INFORMATION ON IPC REFORM The eighth edition (2006) of the Classification represents its first publication after the basic period of IPC reform which was carried out from 1999 to 2005. The following major changes were introduced in the Classification in the course of the reform: (a) the Classification was divided into a core and an advanced level, in order to better satisfy the needs of different categories of users; (b) different revision methods were introduced for the core and the advanced level, namely, a three-year revision cycle for the core level and continuous revision for the advanced level; (c) when the Classification is revised, patent documents are reclassified according to the amendments to the core and the advanced levels; (d) additional data illustrating classification entries or explaining them in more detail, such as classification definitions, structural chemical formulae and graphic illustrations, were introduced in the electronic layer of the Classification; (e) general principles of classification and classification rules were reconsidered and revised where appropriate. Industrial property offices are required to classify their published patent documents either at the core level or at the advanced level. The core level represents a relatively small and stable part of the eighth edition. It includes approximately 20,000 entries at hierarchically high levels of the Classification: sections, classes, subclasses, main groups and, in some technical fields, subgroups with a small number of dots. Revision amendments are not included in the core level of the IPC until its next edition.
    [Show full text]
  • Fast Read/Write • Non-Volatile • Infinite Endurance
    MRAM Magnetoresistive Random Access Memory Fast Read/Write • Non-Volatile • Infinite Endurance High Endurance, Non-volatility Ideal for RAID Applications High Performance, Unlimited En- durance for Industrial and Human Machine Interface Applications Reliability - the Foremost Require- ments in Gaming Systems Performance and Reliability in Demanding Automotive Applications www.everspin.com The MRAM Company Everspin’s State-of-the-Art MRAM Technology How Everspin’s Patented MRAM Memory Technology Works Everspin MRAM is Integrated with Standard CMOS Processing The MTJ device has a low resistance when the magnetic moment of the free layer is parallel to the fixed layer and a high resistance when the free Everspin MRAM is based on magnetic storage elements integrated layer moment is oriented anti-parallel to the fixed layer moment. This with CMOS processing. Each storage element uses a magnetic tun- change in resistance with the magnetic state of the device is an effect nel junction (MTJ) device for a memory cell. known as magnetoresistance, hence the name “magnetoresistive” RAM. Everspin MRAM Technology is Reliable Unlike most other semiconductor memory technologies, the data is stored as a magnetic state rather than a charge, and sensed by measuring The Magnetic Tunnel Junction Storage Element the resistance without disturbing the magnetic state. Using a magnetic state for storage has two main benefits. First, the magnetic polariza- The magnetic tunnel junction (MTJ) storage element is composed tion does not leak away over time like charge does, so the information of a fixed magnetic layer, a thin dielectric tunnel barrier and a free is stored even when the power is turned off.
    [Show full text]
  • Everspin Offers MRAM Shield for Embedded System Developers Using Arduino-Derived Platforms
    Everspin Offers MRAM Shield for Embedded System Developers using Arduino-derived Platforms Everspin to display the 1Mb Quad SPI MR10Q010-EVAL at Embedded World 2015 with the NUCLEO- F411RE from STMicroelectronics Chandler, AZ, February 24, 2015 — Everspin Technologies, Inc., the world's leading developer and manufacturer of discrete and embedded MRAM, today announced a new MRAM-based shield evaluation board that is designed for compatibility with any Arduino-derived host platform featuring a UNO expansion interface. The MR10Q010-EVAL from Everspin allows developers with an Arduino-derived host board to quickly and easily evaluate the benefits of SPI- and QSPI-based Magnetoresistive RAM (MRAM) products from Everspin. Everspin plans to display their new MR10Q010-EVAL shield evaluation board, populated with Everspin’s MR10Q010 1Mb Quad-SPI MRAM, with the STMicroelectronics ARM®-Cortex®-based NUCLEO- F411RE at the Embedded World 2015 show in Nurnberg, Germany from February 24-26 in Hall 5, Booth 428. “The MR10Q010-EVAL is the first MRAM-based shield for the vast Arduino-derived development community,” said Scott Emley, Vice President of Marketing at Everspin. “Developers looking for fast, non-volatile memory with virtually unlimited endurance and high data retention – designed for robust storage, industrial, and transportation markets – now have a simple method to evaluate MRAM for their next project.” The MR10Q010-EVAL shield can stack onto any Arduino-derived host board built to accept Everspin’s MR10Q010-EVAL MRAM shield with shields with a standard UNO expansion STMicroelectronic’s NUCLEO-F411RE Arduino- interface. Qualified designers can request a derived evaluation board. sample of the MR10Q010-EVAL, as well as download gerbers, schematics, quick start software, and documentation directly from Everspin’s website by visiting www.everspin.com/MR10Q010-EVAL.
    [Show full text]
  • Dr. B.R. AMBEDKAR POST GRADUATE CENTRE
    UNIVERSITY OF MYSORE Dr. B.R. AMBEDKAR POST GRADUATE CENTRE SUVARNAGANGOTRI, CHAMARAJANAGARA DEPARTMENT OF PHYSICS Choice Based Credit System (CBCS) 1 ABOUT THE DIRECTOR Prof. Shivabasavaiah completed Ph.D in Zoology, working has Professor (DOS in Zoology) in University of Mysore. His research interest are endocrinology, cancer biology and environmental biology and published so many research articles in national and international journals. He is the founder director of Dr. B.R. Ambedkar PG Centre, Suvarnagangotri, Chamarajanagara. Prof. Shivabasavaiah has been guiding for the overall development of thisPG centre and also supporting the teaching staffs for their academic development. PROF. SHIVABASAVAIAH MSc, PhD, FNESA FOUNDER DIRECTOR ABOUT THE DEPARTMENT Department of Physicswas established in the year 2019 in the main building of Dr. B.R. Ambedkar PG Centre, Suvarnagangotri, Chamarajanagara under the University of Mysore. The department offers two years MSc Physics Under Choice Based Credit System (CBCS). Initially, the department was started with 16 students in the year 2019-20 and the intake is 30 students.This departmentproviding quality education for the students with the collection of knowledgeable information on Physics. Everyday, the faculties are guiding the students for clearing the KSET and NET exams and also introduce the research skills for science and technology. The director of the centre Prof. Shivabasavaiah has been guiding the overall development of this department and his immense support for the installation of the Physics labs. 2 LOCATION The department of Physicsis located at the landmark of Bedarapura in Dr. B.R. Ambedkar PG Centre, Suvarnagangotri, Chamarajanagara. 3 ACADEMIC YEAR 2019-2020 1. STUDENTS DETAILS SC ST CAT1 2A 2B 3A 3B GM TOTAL GRAND YEAR M F M F M F M F M F M F M F M F M F TOTAL I 3 5 0 1 1 0 0 2 0 0 4 1 1 0 0 0 9 9 18 II 2 3 0 0 0 0 0 0 0 1 0 2 5 3 0 0 7 9 16 2.
    [Show full text]
  • Recent Progress and Future Prospects for Magnetoresistive Ram Technology
    RECENT PROGRESS AND FUTURE PROSPECTS FOR MAGNETORESISTIVE RAM TECHNOLOGY Jon Slaughter Everspin Technologies, Inc Chandler, Arizona USA Center for Embedded Systems IAB Meeting Chandler, Arizona, 22 Jan 2013 Outline • MRAM overview • Field-switched MRAM: “Classical Spintronics” • Spin-torque MRAM: Spin-Torque-Transfer Spintronics • Critical device properties and effect of materials • Status: Fully-functional 64Mb, DDR3 ST-MRAM • Summary Everspin – The MRAM Company • MRAM - Magnetic Random Access Memory • Fastest non-volatile memory with unlimited endurance • Only company to have commercialized MRAM • Founded 2008, 100%+ annual revenue growth • Fundamental & essential MRAM IP • 200+ US patents granted, 600+ WW patents & applications • Backed by top-tier VC firms MRAM - Technology Comparison Toggle Write Spin-Torque Write Write with magnetic fields from Write with spin polarized current current-carrying lines. passing through the MTJ. High-performance, nonvolatile, Lower write current enables unlimited endurance higher memory density AlOx / NiFe-based MTJ MgO / CoFeB-based MTJ In volume production 64Mb sampling to customers 4 Everspin Toggle MRAM Attributes Parameter Capability Non-volatile capability • Data retention >20 years Performance • Symmetric read/write – 35ns Endurance • Unlimited cycling endurance • Easily integrates in manufacturing back-end CMOS integration • Compatible with embedded designs • No impact on CMOS device performance Temperature range, • -40ºC < T < 150ºC operation demonstrated reliability • Intrinsic reliability
    [Show full text]
  • Memory Technology for Space
    Aerospace Data Storage and Processing Systems Memory Technology for Space Ian Troxel SEAKR Engineering, Inc. Seminar Day Military and Aerospace Programmable Logic Devices (MAPLD) NASA Goddard Space Flight Center August 31, 2009 Product names that appear in this presentation are for identification purposes only. All trademarks and registered trademarks are the property of their respective owners. Motivation Aerospace Data Storage and Processing Systems J When considering PLD performance, peripheral devices must be included J After the processor, memory is often the device limiting space system capability c/o Flickr Memory Devices for Space Applications 2 of 36 MAPLD 2009 Overview Aerospace Data Storage and Processing Systems JMemory types covered • Non-volatile –EEPROM –Flash EEPROM Flash –Other Programmable • Volatile Logic Device Other –SRAM SRAM DRAM –DRAM JOther special types are used as well JAll results from the open literature and “ITAR safe” JInternal PLD memory not included in this discussion Memory Devices for Space Applications 3 of 36 MAPLD 2009 Memory Specialization Aerospace Data Storage and Processing Systems J Specialization seen in commercial systems also prevalent in space systems J Non-volatile memory • Persistent values, also… • Greater capacity • Lower power dissipation • Slower access times, throughput • Apps: start-up memory, persistent storage J Volatile memory c/o Scholarpedia.com • Values are not persistent, also … • Decreased capacity • Increased power dissipation • Fast access times, throughput • Apps: run-time
    [Show full text]
  • Synthesis and Resistive Switching of Nanocrystalline Vanadium Oxide Films †
    Abstract Synthesis and Resistive Switching of Nanocrystalline Vanadium Oxide Films † Roman V. Tominov 1, Artyom A. Avakyan 1, Zakhar E. Vakulov 2, Vadim I. Avilov 1, Vladimir A. Smirnov 1,* and Oleg A. Ageev 1 1 Institute of Nanotechnologies, Electronics and Electronic Equipment Engineering, Southern Federal University, 347922 Taganrog, Russia; [email protected] (R.V.T.); [email protected] (A.A.A.); [email protected] (V.I.A.); [email protected] (O.A.A.) 2 Federal Research Centre, The Southern Scientific Centre of the Russian Academy of Sciences, 344006 Rostov-on-Don, Russia; [email protected] * Correspondence: [email protected]; Tel.: +7-863-437-1629 † Presented at the 2nd International Online-Conference on Nanomaterials, 15–30 November 2020; Available online: https://iocn2020.sciforum.net/. Abstract: This work is devoted to the study of the modes of synthesis of films of nanocrystalline vanadium oxide for the manufacture of resistive memory elements (ReRAM) of neuromorphic sys- tems. The regularities of the influence of pulsed laser deposition modes on the morphology and electrophysical properties of vanadium oxide films were experimentally established considering the technological parameters of the substrate temperature and temperature of postgrowth annealing. Fabrication modes of nanocrystalline vanadium oxide films were determined with the high-re- sistance state RHRS = (123.42 ± 21.77) × 103 Ω, the low-resistance state RLRS = (5.12 ± 1.36) × 102 Ω, and the ratio RHRS/RLRS = 253, for the creation of elements of resistive memory with low power consump- tion and a wide range of accepted possible resistance values. The results obtained can be used in Citation: Tominov, R.V.; Avakyan, the development of technological processes for the formation of nanocrystalline films of vanadium A.A.; Vakulov, Z.E.; Avilov, V.I.; oxides for resistive memory elements in neuromorphic systems.
    [Show full text]
  • Evaluation of Magnetoresistive RAM for Space Applications
    National Aeronautics and Space Administration Evaluation of Magnetoresistive RAM for Space Applications Jason Heidecker Jet Propulsion Laboratory Pasadena, California Jet Propulsion Laboratory California Institute of Technology Pasadena, California JPL Publication 14-1 1/14 ii National Aeronautics and Space Administration Evaluation of Magnetoresistive RAM for Space Applications NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance Jason Heidecker Jet Propulsion Laboratory Pasadena, California NASA WBS: 104593 JPL Project Number: 104593 Task Number: 40.49.01.09 Jet Propulsion Laboratory 4800 Oak Grove Drive Pasadena, CA 91109 http://nepp.nasa.gov 1/14 i This research was carried out at the Jet Propulsion Laboratory, California Institute of Technology, and was sponsored by the National Aeronautics and Space Administration Electronic Parts and Packaging (NEPP) Program. Reference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise, does not constitute or imply its endorsement by the United States Government or the Jet Propulsion Laboratory, California Institute of Technology. ©2014. California Institute of Technology. Government sponsorship acknowledged. ii TABLE OF CONTENTS 1.0 Introduction ............................................................................................................................................................ 1 2.0 Devices Under Test (DUTs) .................................................................................................................................
    [Show full text]