RECENT PROGRESS AND FUTURE PROSPECTS FOR MAGNETORESISTIVE RAM TECHNOLOGY
Jon Slaughter
Everspin Technologies, Inc Chandler, Arizona USA
Center for Embedded Systems IAB Meeting Chandler, Arizona, 22 Jan 2013 Outline
• MRAM overview
• Field-switched MRAM: “Classical Spintronics”
• Spin-torque MRAM: Spin-Torque-Transfer Spintronics
• Critical device properties and effect of materials
• Status: Fully-functional 64Mb, DDR3 ST-MRAM
• Summary
Everspin – The MRAM Company • MRAM - Magnetic Random Access Memory • Fastest non-volatile memory with unlimited endurance
• Only company to have commercialized MRAM
• Founded 2008, 100%+ annual revenue growth
• Fundamental & essential MRAM IP • 200+ US patents granted, 600+ WW patents & applications
• Backed by top-tier VC firms MRAM - Technology Comparison
Toggle Write Spin-Torque Write
Write with magnetic fields from Write with spin polarized current current-carrying lines. passing through the MTJ. High-performance, nonvolatile, Lower write current enables unlimited endurance higher memory density AlOx / NiFe-based MTJ MgO / CoFeB-based MTJ In volume production 64Mb sampling to customers
4 Everspin Toggle MRAM Attributes
Parameter Capability
Non-volatile capability • Data retention >20 years
Performance • Symmetric read/write – 35ns Endurance • Unlimited cycling endurance • Easily integrates in manufacturing back-end CMOS integration • Compatible with embedded designs • No impact on CMOS device performance Temperature range, • -40ºC < T < 150ºC operation demonstrated reliability • Intrinsic reliability > 20 years lifetime at 125ºC • MRAM cell radiation tolerant Soft error immunity • Soft error rate from alpha radiation too low to measure (<0.1 FIT/Mb) Environmentally • No battery, RoHS compliant, low power friendly
5 MRAM Market Segments
MRAM benefits
Storage & Server Better Reliability Fast Power Off/On • RAID, NAS, SAN & DAS Storage No Batteries/Caps • Rack & Blade Servers Lower TCO
Energy & Infrastructure Better Reliability Industrial Temp Single-Board Computer, Routers, POS, Gaming No Batteries/Caps SmartGrid, SmartMeter, Solar, Wind … Lower TCO
Automotive and Transportation Better Reliability Automotive Temp • Power Train, Brakes, Safety, Data Logging Endurance • MultiMedia, Navigation, Camera, Black Box Lower TCO
6 Current MRAM products All Based on Toggle Switching
16-bit I/O 48-BGA Part Number Density Configuration • x8 Asynchronous parallel I/O MR4A16B 16Mb 1Mx16 • x16 Asynchronous parallel I/O MR2A16A 4Mb 256Kx16 • x8 Asynchronous parallel 1.8V I/O MR0A16A 1Mb 64Kx16 44-TSOPII, 54-TSOP 8-bit I/O • x8 Asynchronous parallel I/O Part Number Density Configuration • x16 Asynchronous parallel I/O MR4A08B 16Mb 2Mx8 8-DFN MR2A08A 4Mb 512Kx8 • SPI-compatible serial I/O MR0A08B 1Mb 128Kx8 • 40 MHz; No write delay MR256A08B 256Kb 32kX8 MR0D08B 1Mb 128KX8, 1.8v I/O 32-SOIC MR256D08 256Kb 32KbX8, 1.8v I/O • x8 Asynchronous parallel I/O
SPI I/O Extended -40 to +105 ºC Part Number Density Configuration Automotive -40 to +125 ºC MR25H40 4Mb 512Kx8 MR25H10 1Mb 128Kx8 Commercial 0 to +70 ºC MR25H256 256Kb 32Kx8 Industrial -40 to +85 ºC
7 Tunneling Magnetoresistance
The tunneling is spin-dependent: spin-up and spin-down have different probabilities.
Low R DV EF First MTJ material with d band MR>10%: AlOx based in 1995 s band • Miyazaki & Tezuka, JMMM 139 • Moodera, et al. PRL 74 V First MTJ material with MR~200% in 2004 • Parkin, et al., Nat. Mat. 10.1038 High R • Yuasa, et al., Nat. Mat. 10.1038 DV EF
d band s band MR= DR/Rlow
MR~ 2P1P2/(1-P1 P2)
8 Discovery to Commercial Application: TMR
• Magnetic Tunnel Junctions with high Tunneling Magnetoresistance in 1995* led to first commercial MRAM in 2006+ • Tunneling resistance can be matched to CMOS transistors • Also used in HDD sensors
*J.S. Moodera, et al., PRL 74, 1995 *T. Miyazaki and N. Tezuka, JMMM 139, 1995 + Freescale/Everspin 4Mb Toggle MRAM Discovery to Commercial Application: STT
• Two major developments spurred the second wave of MRAM development 1. Spin-torque demonstrations • M. Tsoi, et al. 1998 and J.A. Katine, et al. 2000 2. MTJ material with MR~200% • Parkin, et al. and Yuasa, et al. 2004 • Technology Demonstrations Include • M. Hosomi, et al., IEDM 2005 • R. Beach, et al. and T. Kishi, et al., IEDM 2008 • S. Chung, et al. and D. C. Worledge, et al., IEDM 2010 • W. Kim, et al., IEDM 2011 • First Product Sampling: Everspin 64Mb 2012 Recent Progress in Magnetic Switching
• MgO/CoFeB-based MTJs with perpendicular magnetization • S. Ikeda et al., (2010) • D.C. Worledge, et al., (2011) • Very active area of R&D worldwide • Other recent discoveries show potential for continued rapid improvement • Voltage-controlled interface anisotropy • Voltage-controlled magnetism • Spin Hall effect
Outline
• MRAM overview
• Field-switched MRAM: “Classical Spintronics”
• Spin-torque MRAM: Spin-Torque-Transfer Spintronics
• Critical device properties and effect of materials
• Status: Fully-functional 64Mb, DDR3 ST-MRAM
• Summary
1 T-1 MTJ MRAM Write Operation
Write Mode Easy Axis Field
IEasy Free Layer Tunnel Barrier Fixed Layer
Hard Axis Field IHard Isolation Transistor “OFF”
13 Figure 4
MTJ bits
i1
i2
14 Conventional MRAM Bit Selection
• Bit disturb margin • Need many sigma separation between unselected and ½-selected distributions
• All bits along selected current lines have reduced energy barrier during programming • Susceptible to disturb from thermal agitation
15 Conventional Operating Region
Theoretical Experimental from 256k
1.0 3.0 3.1
3.2 3.3 Min.
3.4
0 0
c c
3.5 Fail bits
0.5 / H / / H / 3.6
3.7 easy easy measurement
3.8 H H simulation operating region ibit 3.9 0.0 4.0 0.0 0.5 1.0 4.0 3.9 3.8 3.7 3.6 3.5 3.4 3.3 3.2 3.1 3.0 idigit H / H 0 hard c • Challenge: Programming window sits between 2 distributions. • Challenge: Thermal activation shrinks the window.
16 Toggle Write Operation Low-R High-R State H1 H1 + H2 H2 State
I2 I2 pinned pinned I 1 I1
MTJ
I1
I2
Advantages: Eliminates disturb - Large operating window US Patent 6,545,906, Savtchenko et al. (2003)
17 Toggle-Bit Selection
• High bit disturb margin
• All bits along ½-selected current lines have increased energy barrier during programming
18 Toggle-bit Array Characteristics
Switching map for a 4Mb Toggle MRAM circuit Saturation Errors H2
IV I Lower Hsat leads to errors at high write currents toggling • Sets upper bound of operating region No disturb 100% toggle • Not a half-select problem No disturb Cause
• Top and bottom moments can switch
bit bit i No disturb i places when free SAF is close to saturation No disturb No switch Htog ~ sqrt(Hsat), so operation region toggling opens up with increasing Hsat III II idigit
19 Outline
• MRAM overview
• Field-switched MRAM: “Classical Spintronics”
• Spin-torque MRAM: Spin-Torque-Transfer Spintronics
• Critical device properties and effect of materials
• Status: Fully-functional 64Mb, DDR3 ST-MRAM
• Summary
Spin-Torque MRAM
Use spin momentum from current to change direction of S, m.
5500 Rmax 5000
DS ) Ω
( 4500 Free
4000 layer m 3500 MR Tunnel 3000
Resistance Resistance Rmin Barrier 2500 2000 -0.4 -0.2 0 0.2 0.4 Fixed Current (mA) Layer Need low resistance tunnel barrier to pass the required large DS 2 Torque current density, Jc > 1 MA/cm Dt
21 Desired Scaling of Switching Current
• Today: Reduce Jc for reliability and smaller transistors • Continued scaling: maintain energy barrier and manage distributions while reducing Jc
1000 I (array) Scaling should maintain or sw reduce Jc, then:
IC (MTJ) • IC scales favorably to 100 transistor current Id-sat (transistor) Maintain Eb/kT for non- volatility and control Main Challenge: Current (uA) Current 10 distributions Reduce I (J ) sw c Maintain Distributions Maintain Energy Barrier 1 0 20 40 60 80 100 Technology Node (nm)
2 Ic calculated for Jc=2MA/cm 22 IC scaling with bit size
10000 J RA Ic Area I c C R Jc constant over range of bit sizes 120nm wide
•Data points = Ic for
A) different bit sizes
m 1000
(
C I 50nm wide •Bit width: 120nm →50nm •Aspect ratio: 1.7 → 3.5
But need to maintain energy barrier for non- 100 volatility! 0.1 1 10 Bit resistance R (kW)
23 Paths to lower Ic • For in-plane magnetization:
2e MVs IHMC( k 2 s )
Compensate for thin- Increase spin- film demagnetization torque efficiency field with PMA η
Lower damping () Lower Ms and/or free layer material thinner free layer (Eb limited)
See for example, Katine & Fullerton, Journal of Magnetism and Magnetic Materials 320 (2008) 1217–1226
24 Paths to lower Ic
• For in-plane magnetization:
2e MVs IHMC( k 2 s )
Compensate for thin- Increase spin- film demagnetization torque efficiency field with PMA η
Lower damping () Lower Ms and/or free layer material thinner free layer (Eb limited)
25 Ic with Perpendicular Magnetization
Bit shape Thin-film demagnetization term
2e MV in plane I H 2Ms H 2) c k
Material with large perpendicular anisotropy can offset the demag. field
• Two cases:
1. H < 4Ms , in-plane with perpendicular assist • Energy barrier to reversal dominated by bit shape
2. H > 4Ms , perpendicular magnetization • Energy barrier to reversal dominated by H • Ic ~ Energy Barrier
26 Reduced In-Plane Ic with Perpendicular Assist
Large demagnetization Magnetic Modeling Results Bit shape term dominates I c H = 0 kOe 1.8 2e MV in plane 1.6 Ic Hk 2Ms H 2) H = 2 kOe
1.4
1.2 Material with large perpendicular 1 anisotropy can offset the demag. field H = 4 kOe
0.8 Ic (mA) Ic
0.6 Moment must tilt out of plane during (normalized) Ic H = 6 kOe switching, but energy used to overcome 0.4 demag. field is wasted 0.2
0 30 60 90 120 Short axis (nm)
For bits with: AR=2, 4M=8kOe, Eb /kT=52
27 Engineered materials for Low Jc
0.5 1.5 • Pulsed Permeameter Baseline free measurements show layer material magnetic oscillations in the 0 1 material • Low frequency indicates low perpendicular -0.5 0.5 anisotropy Engineered low-PMA • Decay rate of oscillation Amplitude free layer material shows magnitude of -1 0 damping
-1.5 -0.5 -1 1 3 5 time (ns)
28 Scaling Perpendicular ST-MRAM Devices y
x • Advantages over in-plane devices
• Eb depends on crystalline or interface anisotropy, not shape • Circular bits may allow decreased cell size
• Materials with large H enable acceptable Eb for very small bits • Remaining challenges for perpendicular devices
Ic MV H 4M)
Eb MV H 4M) 2
• Ic Eb current does not scale if Eb is maintained • Need further improvements to continue scaling, such as very low damping
29 Outline
• MRAM overview
• Field-switched MRAM: “Classical Spintronics”
• Spin-torque MRAM: Spin-Torque-Transfer Spintronics
• Critical device properties and effect of materials
• Status: Fully-functional 64Mb, DDR3 ST-MRAM
• Summary
Magnetoresistance Signal and Distributions
Array: Rcell Histogram
1 Rlow Rhigh MR = DR/Rlow , DR=Rhigh– Rlow 7sD R
0.8 Rref
• Signal = Rcell – Rref 0.6 DRuse • ½ of DR available for sensing 6s • Circuit works at finite bias 0.4frequency • MR is reduced by bias dependence of MR 0.2 • Must sense all bits in the 0 array 15 16 17 18 19 20 21 Cell Resistance (kW) • Circuit must work with bits in tails of the R distribution Resistance distribution reduces useable MR.
For six-sigma yield in the array, need: DR/2 > 6s
31 Uniformity of Tunneling Current Density
• Tunneling current density has tunneling “hot spots” • Result is statistical variation in bit resistance
Tunneling AFM and Standard AFM of the same area Tunneling Current Topography
5µm 5µm
32 Defect model for resistance and breakdown distributions
Each defect has associated Random spatial distribution of dielectric strength drawn from defects 1 normal distribution 800 0.9
700 0.8
0.7 600
0.6 500
m) 0.5 400
μ Largest bit size 0.4 300 Y ( Y Defect σ 0.3
200 Number defects of Number 0.2 Smallest bit size 100 μ 0.1 0 0 1 1.2 1.4 1.6 1.8 2 2.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Dielectric strength X (μm)
• Breakdown mediated by weakest defect found in device
33 Read Distribution within an Array
Resistance of bits in a 4Mb array 2500 Critical Factors: Low State 1. Tunnel barrier quality High State 2. Pattern fidelity 2000 DR/s = 30 Optimized for MRAM typical 1500
s~0.8%
#bits 1000
500
10 nm V1/2~+0.7/-0.55 V 0 14 15 16 17 18 19 Bit Resistance [kW]
34 SPIN-TORQUE SWITCHING QUALITY
Single-bit data from probe of short-flow process wafers (not integrated with CMOS) with optimized structures and custom electronics for high-speed pulsing
Integrated memory array data from 16Mb test vehicle fabricated in 90nm CMOS logic process.
35 Distribution Considerations
Separation of distributions • Separation of V & V Key criteria for working memory C bd • Reliable switching MB memory >12σ separation • Tunnel barrier reliability
V V Vread C break- • Separation of Vread & VC down • Avoid read-disturb errors • Bigger issue for smaller bits,
lower IC
σb σs • Switching distribution
σr width increased by: Log(N) 6*(σs+σb) • Shorter write pulses • Smaller bits • Extrinsic switching behavior V 6*(σs+σr) sw V V Separation bd C s avg Applied Voltage
36 Improved Switching in Arrays at High Speed
• Optimized free layer material has better high-speed behavior • Less increase in switching sigma for short pulses • Reduced single-bit sigma and less bit-to-bit variation • Less rise of Vc for short pulses • Fewer bits with anomalously high error rate
Standard Free Layer Standard Free Layer
Optimized Optimized Free Layer Free Layer
Data for integrated arrays of ~80nm bits
37 Reliable High-Speed Switching
• Reliable high-speed switching 1.02 with Everspin’s engineered Engineered material MTJ material 1 • Reliable switching down 0.98 to 2ns Standard 0.96 • Standard CoFeB free layers MgO/CoFeB have degraded switching at 0.94 higher speed (shorter pulses) 0.92 • Extrinsic bits cause SwitchingProbability trouble even for high 0.9 applied bias. 0.88 1 10 100 1000 pulse width (ns)
38 Switching Distribution Anomaly
• Some bits have non-Gaussian switching distributions • ‘Ballooning’ effect results in higher write voltage requirement • Defect related. Caused by intermediate metastable magnetic state • Worse at high speed, not all bits exhibit this behavior
Single-bit switching distribution for 20,000 write cycles Pulse width = 25ns
39 Continued improvements in switching quality
• Optimized free layer improves both single-bit switching quality and bit-to-bit variation
Write Error Rate (WER) out of 10,000 attempts for 9 bits, ~ 85nm x 240 nm , with write pulses of 25ns duration applied P-to-AP (V<0) and AP-to-P (V>0). The black line is a fit of the experimental data assuming a Gaussian distribution of WER.
40 Putting it all together
• Demonstrated large separation of switching and breakdown in16 kb arrays integrated with CMOS
• Large separation >30s • Key figure of merit for: • functionality • manufacturability Separation • reliability
85 nm wide bits Outline
• MRAM overview
• Field-switched MRAM: “Classical Spintronics”
• Spin-torque MRAM: Spin-Torque-Transfer Spintronics
• Critical device properties and effect of materials
• Status: Fully-functional 64Mb, DDR3 ST-MRAM
• Summary
IEDM Conference, San Francisco, December 2012 44 IEDM Conference, San Francisco, December 2012 45 IEDM Conference, San Francisco, December 2012 Conclusions
• Toggle MRAM is a highly reliable, high-performance, nonvolatile memory, with unlimited endurance • Product densities ranges from 256kb-16Mb • Spin-Torque MRAM technology is advancing to enable higher densities and lower power • Continued developments and innovation in nano- magnetic switching provide a strong R&D pipeline for scaling and performance improvement. • Demonstrated a fully-functional 64Mb DDR3 ST-MRAM and delivered working samples to customers • Read and write with no errors • Gaussian switching distributions to ppm level • Arrays with >30-sigma separation of Vc and Vbd