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Picojava-II™ Microarchitecture Guide picoJava-II™ Microarchitecture Guide Sun Microsystems, Inc. 901 San Antonio Road Palo Alto, CA 94303 USA 650 960-1300 Part No.: 960-1160-11 March 1999 Copyright 1999 Sun Microsystems, Inc. 901 San Antonio Road, Palo Alto, California 94303 U.S.A. All rights reserved. The contents of this document are subject to the current version of the Sun Community Source License, picoJava Core (“the License”). You may not use this document except in compliance with the License. You may obtain a copy of the License by searching for “Sun Community Source License” on the World Wide Web at http://www.sun.com. See the License for the rights, obligations, and limitations governing use of the contents of this document. Sun, Sun Microsystems, the Sun logo and all Sun-based trademarks and logos, Java, picoJava, and all Java-based trademarks and logos are trademarks, registered trademarks, or service marks of Sun Microsystems, Inc. in the U.S. and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the U.S. and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. DOCUMENTATION IS PROVIDED “AS IS” AND ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD TO BE LEGALLY INVALID. THIS PUBLICATION COULD INCLUDE TECHNICAL INACCURACIES OR TYPOGRAPHICAL ERRORS. CHANGES ARE PERIODICALLY ADDED TO THE INFORMATION HEREIN; THESE CHANGES WILL BE INCORPORATED IN NEW EDITIONS OF THE PUBLICATION. SUN MICROSYSTEMS, INC. MAY MAKE IMPROVEMENTS AND/OR CHANGES IN THE PRODUCT(S) AND/OR THE PROGRAM(S) DESCRIBED IN THIS PUBLICATION AT ANY TIME. Please Recycle Contents Preface xix 1. Overview 1 1.1 Purpose 1 1.2 Components 2 1.2.1 Instruction Cache Unit (ICU) 3 1.2.2 Integer Unit (IU) 3 1.2.3 Floating Point Unit (FPU) 4 1.2.4 Data Cache Unit (DCU) 4 1.2.5 Stack Manager Unit (SMU) 5 1.2.6 Bus Interface Unit (BIU) 5 1.2.7 Powerdown, Clock, and Scan Unit (PCSU) 5 2. Instruction Cache Unit (ICU) 7 2.1 Structure 10 2.2 Functionalities 10 2.2.1 Instruction Cache Control (ic_cntl)10 2.2.2 Instruction Buffer (I-Buffer) 11 2.2.3 I-Buffer Control (ibuf_cntl)12 2.2.4 Instruction Cache Datapath (icu_dpath)12 iii 2.3 Cache Transactions 12 2.3.1 Cache Read Hits 12 2.3.2 Cache Read Misses 13 2.3.3 Noncacheable (NC) Reads 14 2.3.4 Cache Indexed Flushing 14 2.3.5 Error Transactions 14 2.3.6 Diagnostic Accesses 14 2.4 Power Management 15 2.5 Interface Signals 15 3. Integer Unit (IU) 19 3.1 Instruction Pipeline 20 3.2 Instruction Folding Unit (IFU) 21 3.2.1 I-Buffer Interface 22 3.2.2 Folding Logic 22 3.2.3 Folding Groups 23 3.3 Register Control Unit (RCU) 25 3.3.1 RCU Datapath 25 3.3.2 Interface Signals 27 3.4 Datapath 29 3.4.1 Functionalities 30 3.4.2 Interface Signals 31 3.5 Pipe Control Unit 32 3.5.1 Stall Types 33 3.5.2 Interface Signals 34 3.6 Microcode 35 3.6.1 Interface Protocol 36 3.6.2 Control Logic 37 3.6.3 Datapath 38 iv picoJava-II Microarchitecture Guide • March 1999 4. Floating Point Unit (FPU) 41 4.1 Structure 41 4.1.1 ALU 43 4.1.2 Multiply/Divide (MDIV) 43 4.1.3 Microcode Sequencer 43 4.2 Pipeline 43 4.3 Add and Subtract 44 4.4 Multiply and Divide 45 4.5 IEEE 754 Compliance 45 4.5.1 Deviation From IEEE 754 Specification 46 4.5.2 NaN Operations 46 4.6 Opcodes 47 4.6.1 FADD and FSUB Operations 47 4.6.2 FMUL and DMUL Operations 47 4.6.3 FDIV, FREM, DDIV, and DREM Operations 47 4.6.4 FConvert Operations 47 4.7 Power Management 48 4.8 Interface 48 4.8.1 Input Operations 48 4.8.2 Output Operations 50 4.8.3 Data Forwarding 51 4.9 Critical Paths 51 4.10 Signals 52 5. Data Cache Unit (DCU) 53 5.1 Dependencies 55 5.2 Data Cache 55 5.3 Functionalities 57 5.3.1 Arbiter 57 5.3.2 Address Control 57 Contents v 5.3.3 Aligner Control 57 5.3.4 Miss Control 58 5.3.5 Writeback Control 58 5.3.6 Data Cache Datapath 58 5.4 Pipeline 58 5.4.1 Cache Reads 59 5.4.2 Cache Writes 59 5.4.3 Cache Fills 60 5.4.4 Writebacks 62 5.4.5 Noncacheable (NC) Loads 63 5.4.6 Noncacheable (NC) Stores 63 5.5 Cache Transactions 64 5.5.1 Arbitration of Requests 64 5.5.2 Replacements 64 5.5.3 Cache Compare Flushing 65 5.5.4 Cache Indexed Flushing 65 5.5.5 Cache Invalidate Flushing 65 5.5.6 Zeroing of Cache Lines 65 5.5.7 Nonallocating Writes 66 5.5.8 Nonfetching Allocates 66 5.5.9 Diagnostic Accesses 66 5.6 Interface Signals 66 5.7 Power Management 68 5.8 Critical Timing Path 68 6. Stack Manager Unit (SMU) 71 6.1 Functionalities 73 6.2 Dribbling Operations 74 6.2.1 Spills and Fills 75 6.2.2 Stack Overflow 75 vi picoJava-II Microarchitecture Guide • March 1999 6.2.3 Stack Underflow 76 6.2.4 Stack Cache Write Misses 76 6.3 Pipeline 77 6.4 Interface Signals 77 7. Bus Interface Unit (BIU) 79 7.1 Functionalities 79 7.2 Arbitration 80 7.3 Interfaces 81 7.4 Power Management 82 7.5 Interface Signals 83 8. Powerdown, Clock, Reset, and Scan Unit (PCSU) 85 8.1 Power Management 85 8.1.1 Normal Mode 85 8.1.2 Standby Mode 86 8.2 Clock Management 88 8.3 Reset Management 88 8.4 Scan and Test Features 89 8.5 Interface Signals 91 8.6 Debug and Trace Features 92 8.7 JTAG Support 93 8.7.1 Full Internal Scan 93 8.7.2 Breakpoints and External Halt Mode 93 8.7.3 Single-Stepping 94 8.7.4 Nonscannable Arrays 95 9. External Interface 97 9.1 Core Interface Signals 97 9.1.1 Processor Interface Signals 100 Contents vii 9.1.2 Memory Interface Signals 101 9.1.3 Trace and Debug Signals 103 9.2 picoJava-II Transactions 105 9.2.1 Boot Mode 105 9.2.2 Read-Type Transactions 106 9.2.3 Write-Type Transactions 108 9.3 Endianness and Cacheability 111 9.4 Customizable Features 111 10. Traps and Interrupts 113 10.1 Definitions 113 10.2 Traps 114 10.3 Trap Control 114 10.4 Interrupts 114 10.4.1 Nonmaskable Interrupts (NMI) 115 10.4.2 Maskable Interrupts 115 10.5 Interrupt Control 116 11. Megacells 117 11.1 Instruction Cache Data RAM 117 11.1.1 I/O Pins 120 11.1.2 I/O Signals 121 11.1.3 Timing 122 11.1.4 RAM Redundancy 124 11.1.5 Testing 124 11.2 Instruction Cache Tag RAM 125 11.2.1 I/O Pins 128 11.2.2 I/O Signals 130 11.2.3 Timing 130 11.2.4 Implementation 133 viii picoJava-II Microarchitecture Guide • March 1999 11.2.5 RAM Redundancy 133 11.2.6 Testing 133 11.3 Data Cache Data RAM 134 11.3.1 I/O Pins 136 11.3.2 I/O Signals 137 11.3.3 Timing 138 11.3.4 Implementation 140 11.3.5 RAM Redundancy 140 11.3.6 Testing 140 11.4 Data Cache Tag RAM 141 11.4.1 I/O Pins 144 11.4.2 I/O Signals 145 11.4.3 Timing 146 11.4.4 Implementation 149 11.4.5 RAM Redundancy 149 11.4.6 Testing 149 11.5 Stack Cache RAM 150 11.5.1 I/O Pins 150 11.5.2 I/O Signals 151 11.5.3 Timing 152 11.5.4 Testing 154 11.6 Floating Point Unit (FPU) ROM 154 11.6.1 I/O Pins 156 11.6.2 I/O Signals 157 11.6.3 Timing 158 11.6.4 Implementation 160 11.6.5 ROM Contents 160 11.6.6 RAM Redundancy 160 11.6.7 Testing 160 Contents ix 11.7 Integer Unit (IU) ROM 161 11.7.1 I/O Signals 162 11.7.2 Timing 162 11.7.3 Implementation 163 11.7.4 ROM Contents 163 11.7.5 RAM Redundancy 163 11.7.6 Testing 163 Index 165 x picoJava-II Microarchitecture Guide • March 1999 Figures FIGURE 1-1 picoJava-II Core 2 FIGURE 1-2 Basic Pipeline 3 FIGURE 2-1 Instruction Cache Unit (ICU) Interaction with Other Units 8 FIGURE 2-2 Aligners 9 FIGURE 2-3 Program Counter 9 FIGURE 2-4 Instruction Buffer 11 FIGURE 2-5 A Miss State Transaction 13 FIGURE 3-1 Integer Unit (IU) 20 FIGURE 3-2 Instruction Pipeline in the IU 21 FIGURE 3-3 Instruction Folding Unit (IFU) Datapath 24 FIGURE 3-4 Register Control Unit (RCU) Datapath (Register Access Part for RS1) 26 FIGURE 3-5 Integer Unit (IU) Datapath 30 FIGURE 3-6 pipe_dpath (PC Pipe and OPTOP Pipe) 33 FIGURE 3-7 Microcode Interface with the Main IU Datapath 35 FIGURE 4-1 Floating Point Unit (FPU) 42 FIGURE 4-2 Double-Precision Operation Using Two Cycles 44 FIGURE 4-3 Simplified ALU Section of the Floating Point Unit (FPU) 44 FIGURE 4-4 Multiply and Divide (MDIV) Section of the FPU 45 FIGURE 4-5 Floating Point Interface 48 xi FIGURE 4-6 FPU Timing 49 FIGURE 4-7 Critical Paths in the FPU 51 FIGURE 5-1 Data Control Unit (DCU) Interaction with Other Units 54 FIGURE 5-2 16-Kbyte Data Cache (512x256) 56 FIGURE 5-3 A Pipeline Read Transaction 59 FIGURE 5-4 A Cache Write Transaction 60 FIGURE 5-5 A Cache Fill Transaction 61 FIGURE 5-6 A Writeback Transaction 62 FIGURE 5-7 A Noncacheable Load 63 FIGURE 5-8 A Noncacheable Store 64 FIGURE 5-9 Critical Timing Path in the DCU 69 FIGURE 6-1 Stack Manager Unit (SMU) Interaction with Other Units 72 FIGURE 6-2 Stack Cache 74 FIGURE 7-1 Bus Interface Unit (BIU) 80 FIGURE 7-2 BIU Arbiter 80 FIGURE 7-3 Bus Interface Unit (BIU) Interaction with Other Units 82 FIGURE 8-1 Protocol for the PCSU Standby Mode 86 FIGURE 8-2 Test-Related Vendor Issue 90 FIGURE 8-3 Tracing the Instruction Flow Using the picoJava-II Core 92 FIGURE 8-4 Single-Step Timing Through Scan Mode 94 FIGURE 8-5 Single-Stepping Using Breakpoints 95 FIGURE 8-6 Single-Stepping Using pj_halt 95 FIGURE 9-1 The picoJava-II External Interface 98 FIGURE 9-2 An Example of a System Based on the picoJava-II Core 104 FIGURE 9-3 A Cached Read Transaction Followed by a Noncached Read Transaction 107 FIGURE 9-4 A Cached Write Transaction Followed by a Noncached Write Transaction 108 FIGURE 9-5 A Cached Load Miss 109 FIGURE 9-6 A Noncached Write 110 xii picoJava-II Microarchitecture Guide • March 1999 FIGURE 9-7 A Writeback and Cached Read Miss 110 FIGURE 9-8 An Example of How To Use the picoJava-II
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