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Tiny Register Machine (TRM) Reconfigurable Computing Systems (252-2210-00L) Fall 2012 Tiny Register Machine (TRM) L. Liu Department of Computer Science, ETH Zürich Fall semester, 2012 11 Introduction Jumping up a few levels of Application program s abstraction. Software O perating device drivers Architecture: the programmer’s System s view of the computer instructions Architecture Defined by instructions (operations) registers and operand locations Micro- datapaths architecture controllers Microarchitecture: how to adders Logic implement an architecture in m em ories Digital AND gates hardware C ircuits NOT gates Analog am plifiers C ircuits filters transistors Devices diodes Physics electrons Adapted from Digital Design and Computer Architecture, 2 David Money Harris & Sarah L. Harris @2007 Elsevier Assembly Language To command a computer, you must understand its language. Instructions: words in a computer’s language Instruction set: the vocabulary of a computer’s language Instructions indicate the operation to perform and the operands to use. Assembly language: human-readable format of instructions Machine language: computer-readable format (1’s and 0’s) Assembler: a tool to translate assembly code into machine code TRM (Tiny Register Machine) architecture: Designed by Prof. Niklaus Wirth and implemented on Xilinx Spartan-3, Virtex-5 and Spartan-6 by Ling Liu. A RISC processor that only contains the necessary instructions to run an application written in a high-level language. Once you’ve learned one architecture, it’s easy to learn others. 3 Architecture Design Principles Underlying design principles, as articulated by Hennessy and Patterson: 1. Simplicity favors regularity 2. Make the common case fast 3. Smaller is faster 4. Good design demands good compromises 4 Design Principle 1 Simplicity favors regularity - Consistent instruction format - Same number of operands, easier to encode and handle in hardware 5 TRM instruction encoding Design Principle 2 Make the common case fast - ALU operations are performed on registers and constants - TRM is a reduced instruction set computer (RISC) , with a small number of simple instructions. - The main characteristic of RISC architecture is to allow most instructions to be executed in one clock cycle. 6 Design Principle 3 Smaller is Faster - TRM includes only a small number of registers - Just as retrieving data from a few books on your table is faster than sorting through 1000 books, retrieving data from 32 registers is faster than retrieving it from 1000 registers or a large memory. 7 Design Principle 4 Good design demands good compromises - Multiple instruction formats allow flexibility - ADD , SUB : use 2 register operands - LD , ST : use 2 register operands and a constant - Number of instruction formats kept small - to adhere to design principles 1 and 3 (simplicity favors regularity and smaller is faster). 8 TRM Machine Language Computers only understand 1’s and 0’s Machine language: binary representation of instructions 18-bit instructions Three instruction types: Type a : arithmetical and logical operations Type b : load and store instructions Type c : branch instructions (for jumping) 9 Type a: Arithmetical and Logical Instructions 1 or 2 register operands: Rs : source registers Rd : destination register n: immediate, zero-extended Other fields: op : the operation code or opcode regSel : bit 10 (1 means source operand comes from Rs register) 10 The TRM Registers Name Register Number Usage R0~R7 0 ~ 7 Working register R7 7 Normally used as link register R6 6 Normally used as stack pointer PC Program pointer C Carry flag (1 bit) N Sign flag (1 bit) Z Zero flag (1 bit) V Overflow flag (1 bit) 11 can be ignored The Power of the Stored Program 18-bit instructions and 32-bit data stored in memory Sequence of instructions: only difference between two applications (for example, a text editor and a video game) To run a new program: No rewiring required Simply store new program in memory The processor hardware executes the program: fetches (reads) the instructions from instruction memory in sequence performs the specified operation The program counter (PC) keeps track of the current instruction In TRM, programs start at memory address 0x000 13 The Stored Program Assembly Code Machine Code LD R2, [R0+32] 0x31100 ADD R1, R2 0x08C02 SUB R0, 12 0x0C00C SUB R0, R5 0x0C405 Stored Program Address Instructions 003 0C405 002 0C00C 001 08C02 000 31100 PC Instruction Memory 14 Type b: Load and Store Instructions memory base address register ( Rs ) 7-bit offset (n), zero-extended Bit 10 is always 0 for TRM, 1 for VTRM 15 op instruction operation code (binary) 1100 LD Rd, Rs, n If Rs = R7 then 1100ddd0nnnnnnnsss Rd := mem[n] else Rd := mem[Rs+n] 1101 ST Rd, Rs, n If Rs = R7 then 1101ddd0nnnnnnnsss Mem[n] := Rd else Mem[Rs+n] := Rd Type c: Branch Instructions Jump conditions (cond ) 10/14-bit address offset operand ( off ) 17 Branch Instructions op instruction operation code (binary) 1110 Bc n PC := PC + 1 + n, 1110ccccnnnnnnnnnn on condition c 1111 BL n R7 := PC + 1; 1111nnnnnnnnnnnnnn PC := PC +1+n 18 Branching Allows a program to execute instructions out of sequence. Types of branches: Conditional branches • branch if equal ( BEQ ) • branch if not equal ( BNE ) Unconditional branches • BT • jump register ( BR ) • jump and link ( BL, BLR ) 19 cond condition meaning Mnemonic 0000 Z Zero / equal BEQ (BZS) 0001 ~Z Non-zero / unequal BNE (BZC) 0010 C Carry / above or equal (unsigned) BAE (BCS) 0011 ~C No carry / below (unsigned) BB (BCC) 0100 N Negative BN (BNS) 0101 ~N Not negative BNN (BNC) 0110 V Overflow BO (BVS) 0111 ~V No overflow BNO (BVC) 1000 ~(~C | Z) Carry and no zero / above (unsigned) BA 1001 ~C | Z No carry or zero / below or equal (unsigned) BBE 1010 ~(N ≠V) N=V / greater or equal (signed) BGE 1011 N≠V N≠V / less (signed) BLT 1100 ~((N ≠V) | Z) greater or equal and ~ZF / greater (signed) BGT 1101 (N ≠V) | Z less or Z / less or equal (signed) BLE 1110 TRUE Always BT (B) 1111 FALSE Never BF N = bit 31 of result Z = all 32 bits are zero C = carry V = overflow Conditional Branching (*TRM assembly*) MOV R0, 4 (*R0 = 4*) MOV R1, 1 (*R1 = 1*) SUB R0, R1 (*R0 = R0 – R1 = 3*) BNE target (*branch is taken*) ADD R1, 3 (*not executed*) target: (*label*) ADD R1, R1 (*R1 = 1+1 = 2*) Labels indicate instruction locations in a program. 21 The Branch Not Taken (*TRM assembly*) MOV R0, 4 (*R0 = 4*) MOV R1, 1 (*R1 = 1*) SUB R0, R1 (*R0 = R0 – R1 = 3*) BEQ target (*branch is not taken*) ADD R1, 3 (*executed*) target: (*label*) ADD R1, R1 (*R1 = 1+1 = 2*) 22 Unconditional Branching / Jumping ( BT) (*TRM assembly*) MOV R0, 4 (*R0 = 4*) MOV R1, 1 (*R1 = 1*) BT target (*jump to target*) ROR R1 2 (* not executed*) target: ADD R1, R0 (*R1 = 1 + 4 = 5*) 23 Review: Instruction Formats 24 High-Level Code Constructs if statements if/else statements while loops for loops 25 If Statement High-level code TRM assembly code (* R0 = f, R1 = g, R2 = h R3 = i, R4 = j*) IF i = j THEN f := g + h; f := f – i; 26 If Statement High-level code TRM assembly code (* R0 = f, R1 = g, R2 = h R3 = i, R4 = j*) IF i = j THEN SUB R4, R3 f := g + h; BNE L1 ADD R1, R2 f := f – i; MOV R0, R1 L1: SUB R0, R3 Done: BT Done Notice that the assembly tests for the opposite case ( i != j ) than the test in the high-level code ( i == j ). 27 If / Else Statement High-level code TRM assembly code (* R0 = f, R1 = g, R2 = h R3 = i, R4 = j *) IF i = j THEN f := g + h; ELSE f := f – i; 28 If / Else Statement High-level code TRM assembly code (* R0 = f, R1 = g, R2 = h R3 = i, R4 = j*) IF i = j THEN SUB R4, R3 f := g + h; BNE L1 ELSE ADD R1, R2 f := f – i; MOV R0, R1 BT Done L1: SUB R0, R3 Done: BT Done 29 While Loops High-level code TRM assembly code (* determines the power (*R0 = pow, R1 = x*) of x such that 2 x = 128*) VAR pow, x: INTEGER; BEGIN pow := 1; x := 0; WHILE pow # 128 DO pow := pow * 2; x := x + 1; END END 30 While Loops High-level code TRM assembly code (* determines the power (*R0 = pow, R1 = x*) of x such that 2 x = 128*) MOV R0, 1 VAR pow, x: INTEGER; MOV R1, 0 BEGIN while: MOV R2, R0 pow := 1; SUB R2, 128 x := 0; BEQ done ADD R0, R0 WHILE pow # 128 DO ADD R1, 1 pow := pow * 2; BT while x := x + 1; done: BT done END END Notice that the assembly tests for the opposite case ( pow == 128 ) than the test in the high-level code ( pow != 128 ). 31 For Loops The general form of a for loop is: FOR initialization TO condition BY loop operation DO loop body END initialization: executes before the loop begins condition: is tested at the beginning of each iteration loop operation: executes at the end of each iteration loop body: executes each time the condition is met 32 For Loops High-level code TRM assembly code (* add the numbers from 0 (*R0 = i, R1 = sum*) to 9*) VAR sum, i: INTEGER BEGIN sum := 0; FOR i:=0 TO 9 BY 1 DO sum := sum + i; END END 33 For Loops High-level code TRM assembly code (* add the numbers from 0 (*R0 = i, R1 = sum*) to 9*) MOV R1, 0 VAR MOV R0, 0 sum, i: INTEGER for: MOV R2, R0 BEGIN SUB R2, 10 BEQ done sum := 0; ADD R1, R0 ADD R0, 1 FOR i:=0 TO 9 BY 1 DO BT for sum := sum + i; done: BT done END END Notice that the assembly tests for the opposite case ( i == 10 ) than the test in the high-level code ( i != 10 ).
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