Non-Volatile STT-RAM: a True Universal Memory
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Universal Memory
BRIEFING No.4 ICT UNIVERSAL MEMORY Memory is an integral part of information processing devices and is needed for short‐term stor‐ age such as when computer programs are being executed or text documents are processed. Currently, three main types of memory exist: SRAM offers very high speed at a high cost, DRAM is average in terms of speed and cost, and Flash memory is a low cost, low speed solution for applications that need to retain the data even when power is disconnected. A group of emerg‐ ing memory devices called universal memory aim to combine all these features in a single de‐ vice.1 Developments in universal memory devices may eventually lead to the introduction of novel October 2010 October memory architectures that offer increased performance, enable smaller mobile devices, and offer novel features in traditional products such as cars or domestic appliances. Nanotechnol‐ ogy is an integral part of emerging memory research as it is becoming increasingly difficult to enhance the performance of current devices by scaling the technology further. It is unlikely that a single technology will emerge as the universal memory technology; however, the develop‐ ments in this sector will enhance the energy efficiency and performance of memory devices. Currently, the Integrated Circuit (IC) market is dominated by US and Asia based companies. Uni‐ versal memory and nanotechnology based solutions could provide an opportunity for Europe to gain ground in the sector. Background volatility. Its disadvantage compared to SRAM and DRAM is speed. None of the existing memory technologies provide all of the required properties. -
Nanotechnology ? Nram (Nano Random Access
International Journal Of Engineering Research and Technology (IJERT) IFET-2014 Conference Proceedings INTERFACE ECE T14 INTRACT – INNOVATE - INSPIRE NANOTECHNOLOGY – NRAM (NANO RANDOM ACCESS MEMORY) RANJITHA. T, SANDHYA. R GOVERNMENT COLLEGE OF TECHNOLOGY, COIMBATORE 13. containing elements, nanotubes, are so small, NRAM technology will Abstract— NRAM (Nano Random Access Memory), is one of achieve very high memory densities: at least 10-100 times our current the important applications of nanotechnology. This paper has best. NRAM will operate electromechanically rather than just been prepared to cull out answers for the following crucial electrically, setting it apart from other memory technologies as a questions: nonvolatile form of memory, meaning data will be retained even What is NRAM? when the power is turned off. The creators of the technology claim it What is the need of it? has the advantages of all the best memory technologies with none of How can it be made possible? the disadvantages, setting it up to be the universal medium for What is the principle and technology involved in NRAM? memory in the future. What are the advantages and features of NRAM? The world is longing for all the things it can use within its TECHNOLOGY palm. As a result nanotechnology is taking its head in the world. Nantero's technology is based on a well-known effect in carbon Much of the electronic gadgets are reduced in size and increased nanotubes where crossed nanotubes on a flat surface can either be in efficiency by the nanotechnology. The memory storage devices touching or slightly separated in the vertical direction (normal to the are somewhat large in size due to the materials used for their substrate) due to Van der Waal's interactions. -
Fast Non-Volatile RAM Products Superior Price and Performance from a Source You Can Trust
Fast Non-Volatile RAM Products Superior price and performance from a source you can trust www.freescale.com/MRAM The Future of Non-Volatile Read/Write Memory is Magnetic Freescale Semiconductor delivers the world’s non-volatile for greater than 20 years. Commercial MRAM Products Selector Guide Freescale MRAM Features first commercial magnetoresistive random SRAM-compatible packaging assures Part Number Density Configuration Voltage Speed Grades Temperature Package RoHS Compliant • 35 ns read/write cycle time access memory (MRAM) products. Our alternate sourcing from other suppliers. MR2A16ATS35C 4 Mb 256 Kb x 16 3.3V 35 ns 0 to 70°C 44-TSOP Type II √ • Unlimited read/write endurance MRAM products store data using magnetic MR1A16AYS35 2 Mb 128 Kb x 16 3.3V 35 ns 0 to 70°C 44-TSOP Type II √ • 3.3V ± 10 percent power supply polarization rather than electric charge. Extended Temperature Range and MR0A16AYS35 1 Mb 64 Kb x 16 3.3V 35 ns 0 to 70°C 44-TSOP Type II √ • Always non-volatile with greater than MRAM stores data for decades while reading Superior Reliability 20-year retention and writing at SRAM speed without wear- MRAM delivers a 3 volt high-density out. MRAM products use small, simple • Magnetically shielded to greater than non-volatile RAM that operates over extended cells to deliver the highest density and best 25 oersted (Oe) temperature. MRAM does not exhibit the price/performance in the non-volatile RAM • Commercial, Industrial and Extended charge storage failure modes that limit the marketplace. With our new expanded product Temperature Options data retention or endurance of line, we serve a growing portion of the other technologies. -
Nanotechnology Trends in Nonvolatile Memory Devices
IBM Research Nanotechnology Trends in Nonvolatile Memory Devices Gian-Luca Bona [email protected] IBM Research, Almaden Research Center © 2008 IBM Corporation IBM Research The Elusive Universal Memory © 2008 IBM Corporation IBM Research Incumbent Semiconductor Memories SRAM Cost NOR FLASH DRAM NAND FLASH Attributes for universal memories: –Highest performance –Lowest active and standby power –Unlimited Read/Write endurance –Non-Volatility –Compatible to existing technologies –Continuously scalable –Lowest cost per bit Performance © 2008 IBM Corporation IBM Research Incumbent Semiconductor Memories SRAM Cost NOR FLASH DRAM NAND FLASH m+1 SLm SLm-1 WLn-1 WLn WLn+1 A new class of universal storage device : – a fast solid-state, nonvolatile RAM – enables compact, robust storage systems with solid state reliability and significantly improved cost- performance Performance © 2008 IBM Corporation IBM Research Non-volatile, universal semiconductor memory SL m+1 SL m SL m-1 WL n-1 WL n WL n+1 Everyone is looking for a dense (cheap) crosspoint memory. It is relatively easy to identify materials that show bistable hysteretic behavior (easily distinguishable, stable on/off states). IBM © 2006 IBM Corporation IBM Research The Memory Landscape © 2008 IBM Corporation IBM Research IBM Research Histogram of Memory Papers Papers presented at Symposium on VLSI Technology and IEDM; Ref.: G. Burr et al., IBM Journal of R&D, Vol.52, No.4/5, July 2008 © 2008 IBM Corporation IBM Research IBM Research Emerging Memory Technologies Memory technology remains an -
Magnetic Storage- Magnetic-Core Memory, Magnetic Tape,RAM
Magnetic storage- From magnetic tape to HDD Juhász Levente 2016.02.24 Table of contents 1. Introduction 2. Magnetic tape 3. Magnetic-core memory 4. Bubble memory 5. Hard disk drive 6. Applications, future prospects 7. References 1. Magnetic storage - introduction Magnetic storage: Recording & storage of data on a magnetised medium A form of „non-volatile” memory Data accessed using read/write heads Widely used for computer data storage, audio and video applications, magnetic stripe cards etc. 1. Magnetic storage - introduction 2. Magnetic tape 1928 Germany: Magnetic tape for audio recording by Fritz Pfleumer • Fe2O3 coating on paper stripes, further developed by AEG & BASF 1951: UNIVAC- first use of magnetic tape for data storage • 12,7 mm Ni-plated brass-phosphorus alloy tape • 128 characters /inch data density • 7000 ch. /s writing speed 2. Magnetic tape 2. Magnetic tape 1950s: IBM : patented magnetic tape technology • 12,7 mm wide magnetic tape on a 26,7 cm reel • 370-730 m long tapes 1980: 1100 m PET –based tape • 18 cm reel for developers • 7, 9 stripe tapes (8 bit + parity) • Capacity up to 140 MB DEC –tapes for personal use 2. Magnetic tape 2014: Sony & IBM recorded 148 Gbit /squareinch tape capacity 185 TB! 2. Magnetic tape Remanent structural change in a magnetic medium Analog or digital recording (binary storage) Longitudinal or perpendicular recording Ni-Fe –alloy core in tape head 2. Magnetic tape Hysteresis in magnetic recording 40-150 kHz bias signal applied to the tape to remove its „magnetic history” and „stir” the magnetization Each recorded signal will encounter the same magnetic condition Current in tape head proportional to the signal to be recorded 2. -
Process Variation Aware DRAM (Dynamic Random Access Memory) Design Using Block-Based Adaptive Body Biasing Algorithm
CORE Metadata, citation and similar papers at core.ac.uk Provided by DigitalCommons@USU Utah State University DigitalCommons@USU All Graduate Theses and Dissertations Graduate Studies 12-2012 Process Variation Aware DRAM (Dynamic Random Access Memory) Design Using Block-Based Adaptive Body Biasing Algorithm Satyajit Desai Utah State University Follow this and additional works at: https://digitalcommons.usu.edu/etd Part of the Computer Engineering Commons Recommended Citation Desai, Satyajit, "Process Variation Aware DRAM (Dynamic Random Access Memory) Design Using Block- Based Adaptive Body Biasing Algorithm" (2012). All Graduate Theses and Dissertations. 1419. https://digitalcommons.usu.edu/etd/1419 This Thesis is brought to you for free and open access by the Graduate Studies at DigitalCommons@USU. It has been accepted for inclusion in All Graduate Theses and Dissertations by an authorized administrator of DigitalCommons@USU. For more information, please contact [email protected]. PROCESS VARIATION AWARE DRAM (DYNAMIC RANDOM ACCESS MEMORY) DESIGN USING BLOCK-BASED ADAPTIVE BODY BIASING ALGORITHM by Satyajit Desai A thesis submitted in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE in Computer Engineering Approved: Dr. Sanghamitra Roy Dr. Koushik Chakraborty Major Professor Committee Member Dr. Reyhan Bhaktur Dr. Mark R. McLellan Committee Member Vice President for Research and Dean of the School of Graduate Studies UTAH STATE UNIVERSITY Logan, Utah 2012 ii Copyright c Satyajit Desai 2012 All Rights Reserved iii Abstract Process Variation Aware DRAM (Dynamic Random Access Memory) Design Using Block-Based Adaptive Body Biasing Algorithm by Satyajit Desai, Master of Science Utah State University, 2012 Major Professor: Dr. -
Qt2t0089x7 Nosplash Af5b9567
UNIVERSITY OF CALIFORNIA Los Angeles Interface Engineering of Voltage-Controlled Embedded Magnetic Random Access Memory A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy in Electrical and Computer Engineering by Xiang Li 2018 © Copyright by Xiang Li 2018 ABSTRACT OF THE DISSERTATION Interface Engineering of Voltage-Controlled Embedded Magnetic Random Access Memory by Xiang Li Doctor of Philosophy in Electrical and Computer Engineering University of California, Los Angeles, 2018 Professor Kang Lung Wang, Chair Magnetic memory that utilizes spin to store information has become one of the most promising candidates for next-generation non-volatile memory. Electric-field-assisted writing of magnetic tunnel junctions (MTJs) that exploits the voltage-controlled magnetic anisotropy (VCMA) effect offers great potential for high density and low power memory applications. This emerging Magnetoelectric Random Access Memory (MeRAM) based on the VCMA effect has been investigated due to its lower switching current, compared with traditional current-controlled devices utilizing spin transfer torque (STT) or spin-orbit torque (SOT) for magnetization switching. It is of great promise to integrate MeRAM into the advanced CMOS back-end-of-line (BEOL) processes for on-chip embedded applications, and enable non-volatile electronic systems with low static power dissipation and instant-on operation capability. To achieve the full potential of MeRAM, it is critical to design magnetic materials with high voltage-induced ii writing efficiency, i.e. VCMA coefficient, to allow for low write energy, low write error rate, and high density MeRAM at advanced nodes. In this dissertation, we will first discuss the advantage of MeRAM over other memory technologies with a focus on array-level memory performance, system-level 3D integration, and scaling at advanced nodes. -
DRAM and Storage-Class Memory (SCM) Overview
Page 1 of 7 DRAM and Storage-Class Memory (SCM) Overview Introduction/Motivation Looking forward, volatile and non-volatile memory will play a much greater role in future infrastructure solutions. Figure 1 illustrates a typical processor with its DDR DRAM memory modules (e.g. DIMMs) connected to it. Notice that the integrated memory controller within the processor supports the DDR DRAM bus protocol and only DDR DRAM devices, or those that operate like DDR DRAM, are supported. The tight coupling of computing resources (CPUs, GPUs, FPGAs, etc.) with memory resources pose challenges to memory’s expanding importance. These challenges include: Memory capacity requirements are increasing, driven by in-memory workloads, server virtualization, etc. Compute capacity of CPUs are increasing, requiring more memory controllers and channels per socket Fewer high speed DIMMs per channel require more memory controllers and channels to maintain capacity Design/support lifecycles for compute and memory resources are tightly coupled making each dependent on the other Memory capacity is dependent on the number of CPUs, yielding over-provisioned compute for many workloads Gen-Z is a new data access technology that can significantly enhance memory solutions built with existing or emerging memory technologies. The following sections are designed to unveil the features and capabilities of the Gen-Z architecture by first describing the foundational features and building on these to illustrate the next generation components and system solutions that are made possible by Gen-Z technology. Note: many components require byte-addressable memory (e.g. CPU, SoC, GPUs, FPGAs, gateways, etc.), but, in this document, the term “processor” will be used to generically describe these roles. -
The Effects of Magnetic Fields on Magnetic Storage Media Used in Computers
NITED STATES ARTMENT OF MMERCE NBS TECHNICAL NOTE 735 BLICATION of Magnetic Fields on Magnetic Storage Media Used in Computers — NATIONAL BUREAU OF STANDARDS The National Bureau of Standards^ was established by an act of Congress March 3, 1901. The Bureau's overall goal is to strengthen and advance the Nation's science and technology and facilitate their effective application for public benefit. To this end, the Bureau conducts research and provides: (1) a basis for the Nation's physical measure- ment system, (2) scientific and technological services for industry and government, (3) a technical basis for equity in trade, and (4) technical services to promote public safety. The Bureau consists of the Institute for Basic Standards, the Institute for Materials Research, the Institute for Applied Technology, the Center for Computer Sciences and Technology, and the Office for Information Programs. THE INSTITUTE FOR BASIC STANDARDS provides the central basis within the United States of a complete and consistent system of physical measurement; coordinates that system with measurement systems of other nations; and furnishes essential services leading to accurate and uniform physical measurements throughout the Nation's scien- tific community, industry, and commerce. The Institute consists of a Center for Radia- tion Research, an Office of Measurement Services and the following divisions: Applied Mathematics—Electricity—Heat—Mechanics—Optical Physics—Linac Radiation^—Nuclear Radiation^—Applied Radiation-—Quantum Electronics' Electromagnetics^—Time and Frequency'—Laboratory Astrophysics'—Cryo- genics'. THE INSTITUTE FOR MATERIALS RESEARCH conducts materials research lead- ing to improved methods of measurement, standards, and data on the properties of well-characterized materials needed by industry, commerce, educational institutions, and Government; provides advisory and research services to other Government agencies; and develops, produces, and distributes standard reference materials. -
Semiconductor Memory
Semiconductor Memory Seong-Ook Jung 2011. 4. 1. [email protected] VLSI SYSTEM LAB, YONSEI University School of Electrical & Electronic Engineering Contents 1. Current Memory 2. Future of NAND Flash 3. Universal memory 1. PRAM 2. STT-MRAM 2 YONSEI Univ. School of EEE Current Memory Memory Hierarchy by Samsung electronics 4 YONSEI Univ. School of EEE Volatile vs. Non-Volatile Volatile memory DRAM: fast speed, high density Main memory SRAM: very fast speed, very low density Cache memory Non-volatile memory NOR: very slow speed, low density Program memory Flash: very slow speed, very high density Storage memory 5 YONSEI Univ. School of EEE Charge Based vs. Resistance Based Charge based device (Current memory) DRAM SRAM Flash Resistance base memory (Future memory Universal memory) PRAM RRAM 6 YONSEI Univ. School of EEE SRAM Cache hierarchy in Lynnfield L1 ; 32KB (1core) L2 ; 256KB (1core) L3 ; 8MB (shared) Intel processor ; Lynnfield Layout of Lynnfield SRAM cell 7 YONSEI Univ. School of EEE DRAM SAMSUNG DDR3 4GB DRAM DRAM cell 8 YONSEI Univ. School of EEE DRAM Cell 9 YONSEI Univ. School of EEE Flash Memory Samsung 256GB SSD Flash memory cell Samsung 32GB USB memory 10 YONSEI Univ. School of EEE Comparison by Korea Institute of Science & Technology Information (KISTI) 11 YONSEI Univ. School of EEE DRAM and SRAM Trend Improve performance and capacity of DRAM and SRAM Technology scaling Design technique Function and role of DRAM and SRAM are not changed. SRAM ; cache memory in processor DRAM ; main memory unit in system NGM XDR DRAM diff? DDR4 DDR3 DRDRAM Bandwidth DDR2 DDR SDRAM 1996 2000 2004 2008 2012 Year by Intel Technology Journal 12 YONSEI Univ. -
Memory and Storage Systems
CHAPTER 3 MEMORY AND STORAGE SYSTEMS Chapter Outline Chapter Objectives 3.1 Introduction In this chapter, we will learn: 3.2 Memory Representation ∑ The concept of memory and its 3.3 Random Access Memory representation. 3.3.1 Static RAM ∑ How data is stored in Random Access 3.3.2 Dynamic RAM Memory (RAM) and the various types of 3.4 Read Only Memory RAM. 3.4.1 Programmable ROM ∑ How data is stored in Read Only Memory 3.4.2 Erasable PROM (ROM) and the various types of ROM. 3.4.3 Electrically Erasable PROM ∑ The concept of storage systems and the 3.4.4 Flash ROM various types of storage systems. 3.5 Storage Systems ∑ The criteria for evaluating storage 3.6 Magnetic Storage Systems systems. 3.6.1 Magnetic Tapes 3.6.2 Magnetic Disks 3.7 Optical Storage Systems 3.1 INTRODUCTION 3.7.1 Read only Optical Disks 3.7.2 Write Once, Read Many Disks Computers are used not only for processing of data 3.8 Magneto Optical Systems for immediate use, but also for storing of large 3.8.1 Principle used in Recording Data volume of data for future use. In order to meet 3.8.2 Architecture of Magneto Optical Disks these two specifi c requirements, computers use two 3.9 Solid-State Storage Devices types of storage locations—one, for storing the data 3.9.1 Structure of SSD that are being currently handled by the CPU and the 3.9.2 Advantages of SSD other, for storing the results and the data for future 3.9.3 Disadvantages of SSD use. -
James A. Bain the Oracle at Delphi Outline • Logistics of the Advising and Mentoring Process
JamesJames A.A. BainBain Courses:Courses: Professor Department of ECE 18-202: Mathematical Foundations of EE Data Storage Systems Center 18-416: information Storage Systems http://www.ece.cmu.edu/~jbain 18-517: Information Storage Systems Design Probe Information Storage Device Physics V Recording Information Storage Device Physics Ti/A Field STM Cr-SrZrO3 Tip Emission • Energy localization SrRuO3 • Storage materials SrTiO3 Magnetic • Hysteretic phenomena Medium • High frequency switching 6 4 2 Magnetic 2 3 Marks Heat Assisted Magnetic Recording 0 -2 4 ∆R MFM -4 Perovskites Voltage (V)Voltage (V) 1 -6 -8 -1.0 -0.5 0.0 0.5 1.0 Current (mA) [email protected] ECE Advising: Getting Your Questions Answered James A. Bain The Oracle at Delphi Outline • Logistics of the advising and mentoring process • Objectives of the advising and mentoring process • Advising summary • Data storage technology overview ... Logistics of Advising Process • Fall Sophomore Year – Take 18-200: Emerging Trends in ECE – Receive advisor assignment – Complete advising preparation worksheet – Meet with advisor (possibly more than once) – Select classes for Spring 05 • Spring Sophomore Year – Meet with advisor (possibly more than once) – Request/select a faculty mentor – Meet with faculty mentor – Select classes for Fall 06 • Junior and Senior Years – Meet with faculty mentor as desired – Select classes for each semester – Plan for post-graduation: internships, jobs, fellowships, grad schools, etc. ECE Undergraduate Advising Committee Undergraduate Program Staff Susan Farrington - [email protected] HH 1118, 8-6955 Director of Alumni and Student Relations Structures relationships with students during and after ECE, student organizations, profession societies, alumni events Janet Peters- [email protected] HH 1110, 8-3666 Assistant for Undergraduate Education Monitors student academic progress, handles procedural and policy information and information on Co-op, IMB, Bruce Krogh Double Majors and Minors, Career Center, Health Center, etc.