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Application-Specific Hardware Application-Specific Hardware: Computing Without CPUs Mihai Budiu [email protected] Abstract ¯ Today’s processors use extremely complicated hard- ware structures to enable the exploitation of the In this paper we propose a new architecture for general- instruction-level parallelism (ILP) in large win- purpose computing which combines a reconfigurable- dows; however, the sustained performance is rather hardware substrate and compiler technology to gener- low [15]. ate Application-Specific Hardware (ASH). The novelty of In Section 2 we propose an alternative approach to im- this architecture is that resources are not shared: each dif- plement general-purpose computation, which consists of ferent static program instruction can have its own dedi- synthesizing — at compile time — application-specific cated hardware implementation. ASH enables the syn- hardware, on a reconfigurable-hardware substrate. We thesis of circuits with only local computation structures, argue that such hardware can be more efficient than a which promise to be fast, inexpensive and use very lit- general-purpose CPU, and can solve or alleviate all of tle power. This paper also presents a scalable compiler the above problems. We call this model ASH, from framework for ASH, which generates hardware from pro- Application-Specific Hardware. grams written in C and some evaluations of the resources We propose a way to synthesize directly custom, necessary for implementing realistic programs. application-specific dataflow machines in hardware. The ASH machines have low overhead, as they implement the whole application in reconfigurable hardware, and avoid 1 Introduction time-multiplexing hardware resources. The main component of the ASH framework is CASH, For five decades the relentless pace of technology, ex- a Compiler for ASH, presented in Section 3. CASH spans pressed as Moore’s law, has supplied computer architects both the realm of traditional compilation and hardware with ample materials in the quest for high performance. synthesis. The abundance of resources has translated into increased In Section 4 we evaluate the hardware resources needed complexity1. This complexity has already become un- to implement realistic programs within the ASH model of manageable in several respects: computation. Section 6 describes some implications of the ASH architecture on computer system design. ¯ The verification and testing cost escalates dramati- cally with each new hardware generation. ¯ Manufacturing costs (both plant costs and non- recurring engineering costs) have skyrocketed. 2 Application-Specific Hardware ¯ Defect density control becomes very expensive as In this section we give an overview of the ASH model of the feature size shrinks; in the near future we will computation. The core of ASH is a reconfigurable fab- be unable to manufacture large defect-free integrated ric; compilation subsumes the role of traditional software circuits. compilation and hardware synthesis, translating high- ¾ ¯ The dissipated power density (watts/mm ) of state- level language programs into hardware configurations. of-the-art microprocessors has already reached val- Reconfigurable hardware devices are hardware devices ues that make air-cooling infeasible [4]. whose functionality can be changed dynamically (see [10] ¯ The clock frequency has increased to a value where for a survey). The most common type of device is a Field- global signals across the entire chip are infeasible Programmable Gate Array and features a set of univer- (the propagation delay exceeds the clock cycle [1]). sal logic gates connected by a switched interconnection ¯ The number of exceptions which require manual network. The logic gates are implemented as look-up ta- interventions generated by the CAD tools grows bles from small memories; by changing the contents of quickly with design complexity [16]. each memory we change the function computed by each 1In this paper we will be mostly concerned with the complexity of gate. Configuration bits also control the switches on the microprocessors. interconnection network; by choosing which switches are 1 3 Program SAM has predictable latency ; moreover, the SAM local memory has predictable access times. CASH SAMs are inspired by the Threaded Abstract Machine Compile−time model [11]; like TAMs, whenever a SAM needs to ex- Split−phase Abstract Machines ecute an operation that has unpredictable latency it uses the inter-SAM communication network: remote memory Local Placer−Router accesses, and control-flow transfers between SAMs are transformed into messages routed dynamically on the net- Object files work. SAMs roughly approximate the procedures in a defect Link−time high-level programming language (however, in our im- Global Placer−Router map plementation a procedure can be decomposed into several Configuration SAMs). During the program execution, at each instant a SAM Virtualization layer can be in one of three states: Run−time Reconfigurable hardware + RAM ¯ Inactive SAMs are not being executed and do not have any live state. These SAMs do not need to consume any power and, if hardware virtualization is Figure 1: The ASH tool-flow. available, can be swapped out of the reconfigurable hardware. ¯ One active SAM is actively switching and consum- open and which are closed we effectively connect the ing power and should be entirely swapped in; it is logic gates to each other. Reconfigurable hardware thus analogous to the procedure on the top of the stack features the flexibility of general-purpose programmable (currently being executed) in a traditional model of systems and computation speeds comparable to raw hard- computation4. ware. ¯ Passive SAMs are mostly quiescent: they store live Figure 1 summarizes our framework. Programs writ- values, but are blocked waiting for the completion ten in general-purpose high-level languages are the in- of a “callee” SAM. They dissipate only static power put to the CASH compiler. After applying traditional most of the time5 and correspond roughly to the pro- program-optimization techniques, CASH decomposes the cedures in the current call chain, which have been program into small fragments, called Split-phase Abstract started in execution, but have not been completed. Machines, or SAMs. Each SAM is optimized, synthesized, placed, and routed independently. The placed SAMs that compose the 2.2 An example 2 complete program are fed to a global placer and router Figure 2 shows a simple C program and the equivalent which decides how to lay-out the machines and how to translation into three SAMs. This figure has been auto- connect them using an interconnection network. The re- matically generated by an early version of our prototype sulting “executable” is a configuration for the reconfig- CASH compiler using the VCG graph layout tool [18] as urable hardware. At run time the configuration is loaded a back-end. This figure illustrates just one possible imple- on the reconfigurable-hardware substrate and executed. mentation, and a rather suboptimal one. If the configuration is too large, a run-time hardware- The compiler creates three SAMs from this program: virtualization method may be used. In this paper we only present the CASH component SAM 1 implements the initialization of the variables i from Figure 1. and j with 0. It receives as input the “program counter” (PC), which indicates the caller SAM. The shaded empty oval receives a control token which en- 2.1 Split-phase Abstract Machines ables the current SAM to start execution. The lightly shaded rectangles with a sharp sign are output regis- The Split-phase Abstract Machine (SAM) is the main ters, containing data that is passed to SAM 2. abstraction of our intermediate program representation. The compiled program is partitioned into a collection of 3SAMs can also invoke remote operations, which have unpredictable latencies. SAMs, which communicate asynchronously with each 4Currently we only consider programs which have a single thread of other. Each SAM contains computation and possibly a execution; a parallel model of execution might have several active SAMs small local memory. The computation implemented in a at one moment. 5There may be some concurrent activity between the passive SAMs 2The global placer can use a defect map of the target chip to provide and the active one, because of “instructions” that can be executed in fault-tolerance, by avoiding the defective regions. parallel with the “call”. 2 Legend plexors (represented by the ?: diamonds) that select the values for i and j based on the flow of control: #@−>3 predicate enabling SAM 3 either the initial value or the result from the incre- #−>2 output register sent to SAM 2 ment operation. The multiplexors have two data in- int main(void) first input puts and two control inputs (dotted lines) each; the { second input shades correspond: when the dark dotted line is as- int i, j=0; mux selector predicate for (i=0; i<10; i++) serted, the dark input is selected. The boxes marked j+= i; "Start" predicate with sharp signs # are registers holding the state, rep- return j; i j } j input variable resented by the values of and . #j loop register for variable j SAM 2 is executed as long as the loop condition is true (i.e., i<10). When the loop condition be- multiplexor comes false, control is transfered to the SAM 3. SAM 3 executes just the return instruction. It receives from SAM 2 the value of j and the PC and uses them as arguments to the return “instruction”. Because the #−>2 #@−>2 #−>2 return instruction has a side-effect, it has a third in- put, a predicate, which indicates when the instruction is safe to execute. Because this return is executed un- i j conditionally, the predicate is fed directly from the SAM 1 enabling token. This return instruction uses the PC value to return the control to the SAM that had orig- inally invoked SAM 1. 2.3 Benefits of the ASH Model #i #j The ASH model has better scalability properties than tra- ditional CPU architectures. For instance: ¯ The verification and testing of a homogeneous re- configurable fabric is much simpler.
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