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A Hybrid Systolic-Dataflow Architecture for Inductive Matrix A Hybrid Systolic-Dataflow Architecture for Inductive Matrix Algorithms Jian Weng, Sihao Liu, Zhengrong Wang, Vidushi Dadu, Tony Nowatzki University of California, Los Angeles Los Angeles, California, US fjian.weng, sihao, seanzw, vidushi.dadu, [email protected] Inductive Workloads Non-inductive Workloads Abstract—Dense linear algebra kernels are critical for wireless, 25% and the oncoming proliferation of 5G only amplifies their dsp cpu gpu importance. Due to the inductive nature of many such algorithms, 20% parallelism is difficult to exploit: parallel regions have fine- 15% grain producer/consumer interaction with iteratively changing 10% dependence distance, reuse rate, and memory access patterns. This causes a high overhead both for multi-threading due to 5% 0% fine-grain synchronization, and for vectorization due to the non- % of Ideal Performance avg avg 12 24 32 12 24 32 12 24 32 12 24 32 37 12 24 48 64 rectangular iteration domains. CPUs, DSPs, and GPUs perform svd qr cho sol fir 147 199 mm fft 512 order-of-magnitude below peak. 1024 Fig. 1: Percent ideal performance. CPU: Xeon 4116–Intel MKL, Our insight is that if the nature of inductive dependences DSP: TI C6678–TI DSPLIB, GPU: TITAN V–NVIDIA libraries and memory accesses were explicit in the hardware/software interface, then a spatial architecture could efficiently execute parallel code regions. To this end, we first extend the traditional (a) Solver Code (b) Solver’s Iteration Space i (inner loop) dataflow model with first class primitives for inductive depen- for (j=0; j<n; ++j) j dences and memory access patterns (streams). Second, we develop 5 units work a hybrid spatial architecture combining systolic and dataflow b[j] = b[j]/a[j,j] execution to attain high utilization at low energy and area cost. for (i=j+1; i<n; ++i) 4 units work Finally, we create a scalable design through a novel vector-stream b[i] -= b[j]*a[j,i] 3 units work control model which amortizes control overhead both in time and Forward Dep. Loop Carried 2 units work spatially across architecture lanes. ... Obser- Many fine grain dependences Parallel Work is Inductive: We evaluate our design, REVEL, with a full stack (compiler, vations: across program regions Work degree depends inductively on j ISA, simulator, RTL). Across a suite of linear algebra kernels, Fig. 2: Inductive Workload Example: Triangular Linear Solver REVEL outperforms equally-provisioned DSPs by 4.6×—37×. Compared to state-of-the-art spatial architectures, REVEL is mean 3.4× faster. Compared to a set of ASICs, REVEL is only with the same computation resources as the DSP (methodology 2× the power and half the area. in Section VII). An order of magnitude of performance is lost. Keywords-Spatial Architecture; Reconfigurable Accelerator; The primary challenge comes from the commonly inductive Software/Hardware Codesign; Digital Signal Processor nature of the parallelism present, coupled with the com- monly small matrices in this domain. Informally, many DSP algorithms are inductive in that they build on intermediate I. INTRODUCTION computations iteratively and at a fine-grain. A simple inductive Dense linear algebra kernels, like matrix factorization, mul- workload is the triangular solver in Figure2(a), which updates tiplication, decomposition and FFT, have for decades been a shrinking subset of a vector repeatedly based on a division the computational workhorses of signal processing across in the outer loop. Figure2(b) shows the dependences between standards, specifications, and device settings. The oncom- iterations of the inner and outer loop. This contrasts sharply ing proliferation of 5G wireless is only further pushing the with a non-inductive workload like dense matrix multiplica- computational demands, both in performance and energy tion, where all parallelism is available immediately and there efficiency [1], [2]. Driven by needs of higher capacity [3] are no dependences (besides reduction). and applications like augmented and virtual reality [4], new Though simple, this workload demonstrates two common standards will require signal processing at more than an order- properties: 1. fine-grain producer/consumer relationships be- of-magnitude higher throughput and lower latency. Relying tween program regions and 2. many aspects of the program on fixed-function ASICs alone has many drawbacks: design execution are a function of an outer loop induction variable effort, extra on-chip area, and lack of flexibility; these are es- – in this case that includes the amount of parallel work, the pecially relevant for wireless, where standards are continually rate of data reuse, the dependence distance, and the memory changing (4G,LTE,5G,etc). access pattern. Hence, we refer to any aspect of execution that Despite their ubiquity, many important dense matrix oper- varies with an outer-loop induction variable as inductive. ations are far from trivial to parallelize and compute at high CPUs, GPUs, and DSPs rely heavily on vectorization and hardware efficiency on programmable architectures. Figure1 multithreading; both are hindered by inductive behavior. Vec- shows the throughput of a modern CPU, DSP, and GPU torization has a high overhead because the total iterations of running common DSP algorithms, compared to an ideal ASIC parallel work changes inductively, therefore the iteration count REVEL Accelerator Shared SPAD Local Control Our contributions are: • Identification of fine-grain inductive behavior as a primary SPAD SPAD ... SPAD challenge for many dense linear algebra kernels. Hybrid Hybrid Hybrid • Taxonomy of spatial architectures which explains their FIFOs with Systolic- Systolic- Systolic- Program- tradeoffs for DSP workloads. Dataflow Dataflow Dep. Dataflow able Reuse • Inductive dataflow execution model which expresses induc- Inter-lane Inter-lane XFER XFER XFER Vector Lane 1 Vector Lane 2 Vector Lane N tive memory and dependences as a first-class primitive to Broadcast reduce control overhead and make vectorization profitable. Streams A[0:n] Memory B[0:n-i] Inductive • A novel hybrid systolic-dataflow architecture to specialize Stream Memory Vector-Stream Stream × × / Control Core / for the exposed inductive parallelism. × × Switch / + √ √ + √ √ • REVEL accelerator design and its novel vector-stream √ × config REVEL Program + √ 1|1 + / produce | × mem expressed as a series control model which amortizes control in time and space. × 1|n-i / dep of streams vectorized + consume wait / Inductive rate Systolic Dataflow across lanes. • Full stack implementation, open-source compiler, simula- Reuse Dep. PE PE Ctrl Program 1 1.Inductive Dataflow Model 2.Hybrid Systolic-Dataflow Arch. 3.Vector-Stream Control tor , and comparison against state-of-the art DSPs, CPUs, reduces control overhead for inductive parallelism for efficient scaling GPUs and spatial architectures. Fig. 3: Proposed Architecture and Three Novel Aspects Results: A single 1.25GHz REVEL unit can outperform a will frequently not be divisible by the vector length, causing 2.1GHz OOO core running highly-optimized MKL code on under-utilization. Frequent dependences between program re- DSP workloads by mean 9.6×, with an area normalized gions due to inductive updates make thread-synchronization speedup of 1089×. Compared to a DSP, REVEL achieves overhead too high. between 4.6×-37× lower latency, It is half the area of an Dataflow models and their corresponding architectures [5]– equivalent set of ASICs and within 2× average power. [7] are promising because they can express dependences with Paper Organization: We characterize the workloads and inductive patterns, enabling parallelism of regions even with challenges for existing architectures in SectionII, and the fine-grain dependences. Spatial dataflow architectures [8]– promise and challenges for spatial architectures in Section III. [12] help make dataflow architectures practical and energy- We then develop inductive dataflow and the hybrid architecture efficient. However, we demonstrate quantitatively that these in SectionIV. Our accelerator, REVEL, and its vector-stream are still factors under peak performance due to either control control model is described in SectionV, and its compiler is overheads or serialization. in SectionVI. Finally, we cover methodology, evaluation and Goal and Approach: Our goal is to create the next-generation additional related work in Sections VII, VIII, andIX. programmable DSP architecture, capable of both inductive and non-inductive parallelism, by leveraging principles of dataflow, II. WORKLOAD CHARACTERIZATION spatial architectures and specialization. We summarize the In this section, we explain how the inductive nature of many proposed design, REVEL (Reconfigurable Vector Lanes), and linear algebra workloads creates parallelism that is difficult novel aspects of this work (see Figure3): to exploit. We start with workload background, then discuss First, we create an inductive dataflow execution model, inductive workload characteristics and why they hamper tra- which extends dataflow execution with first class primitives ditional architectures. for inductive dependences and memory access streams. This specialization enables effective vectorization through implicit A. Why these particular DSP workloads? masking based on the relationship of stream to vector length, Figure4 shows typical 4G/5G transmitter/receiver stages: and allows expression of inductive behavior at low control overhead. General Matrix Mult: Matrix size Downlink depends on # of antennas&beams Second, we develop a hybrid systolic/dataflow architecture,
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