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Systolic Computing on Gpus for Productive Performance Systolic Computing on GPUs for Productive Performance Hongbo Rong Xiaochen Hao Yun Liang Intel Intel, Peking University Peking University [email protected] [email protected] [email protected] Lidong Xu Hong H Jiang Pradeep Dubey Intel Intel Intel [email protected] [email protected] [email protected] Abstract an SIMT (single-instruction multiple-threads) programming We propose a language and compiler to productively build interface, and rely on an underlying compiler to transparently high-performance software systolic arrays that run on GPUs. map a wrap of threads to SIMD execution units. If data need to Based on a rigorous mathematical foundation (uniform re- be exchanged among threads in the same wrap, programmers currence equations and space-time transform), our language have to write explicit shuffle instructions [19]. has a high abstraction level and covers a wide range of ap- This paper proposes a new programming style that pro- plications. A programmer specifies a projection of a dataflow grams GPUs as building software systolic arrays. Systolic ar- compute onto a linear systolic array, while leaving the detailed rays have been extensively studied since 1978 [15], and shown implementation of the projection to a compiler; the compiler an abundance of practice-oriented applications, mainly in implements the specified projection and maps the linear sys- fields dominated by iterative procedures [32], e.g. image and tolic array to the SIMD execution units and vector registers signal processing, matrix arithmetic, non-numeric applica- of GPUs. In this way, both productivity and performance are tions, relational database [7, 8, 10, 11, 16, 17, 30], and so on. achieved in the same time. This approach neatly combines A systolic array is composed of many hardware PEs (Pro- loop transformations, data shuffling, and vector register al- cessing Elements) that have the same instructions and works location into a single framework. Meanwhile, many other rhythmically: every time step, the PEs typically read inputs optimizations can be applied as well; the compiler composes from some neighbors, process the inputs, and forward the the optimizations together to generate efficient code. inputs or results to other neighbors. Therefore, systolic arrays We implemented the approach on Intel GPUs. This is the can be viewed as “the combination of SIMD and the pipeline ar- first system that allows productive construction of systolic chitectures characteristics" [21], a fact that has been observed arrays on GPUs. We allow multiple projections, arbitrary pro- for a long time. jection directions and linear schedules, which can express Based on this fact, we can build a systolic array on a GPU most, if not all, systolic arrays in practice. Experiments with by mapping the PEs to the SIMD lanes of the GPU, and real- 1- and 2-D convolution on an Intel GEN9.5 GPU have demon- izing the data forwarding using shuffle instructions among strated the generality of the approach, and its productivity vector registers. This idea has been proposed as “software in expressing various systolic designs for finding the best systolic array" by Chen et al., and demonstrated on stencils candidate. Although our systolic arrays are purely software and convolution manually with competitive performance [3]. runningongenericSIMDhardware,comparedwiththeGPU’s Similar ideas can be found elsewhere. For examples, Ponde- specialized, hardware samplers that perform the same convo- mente, Luna and Alba used GPUs to build systolic arrays arXiv:2010.15884v1 [cs.PL] 29 Oct 2020 lutions, some of our best designs are up to 59% faster. Overall, for a generic search algorithm [1], Wang et al. implemented this approach holds promise for productive high-performance sequence alignment algorithms on GPUs in a systolic style computing on GPUs. without mentioning it [29]. All these works were done on Nvidia GPUs in the CUDA language. Keywords: Language, Compiler, Systolic array, GPU These state-of-art works, however, focus on specific work- loads, and the systolic arrays were built in high programming 1 Introduction skills. None of the works has pointed out a general, systematic All modern GPUs achieve performance via hardware multi- solution how to build on GPUs arbitrary systolic arrays for the threading and SIMD (single-instruction multiple-data), and numerous workloads that are known to benefit from systolic an efficient memory hierarchy [5]. The mainstream program- algorithms. And they have not provided a productive tool for minglanguagessuchasCUDAandOpenCLessentiallyexpose quickly building systolic arrays on GPUs, either. In this paper, we present a language and compiler to pro- August, 14, 2020 ductively build high-performance systolic arrays that run on Preprint. 1 August, 14, 2020 Hongbo Rong, Xiaochen Hao, Yun Liang, Lidong Xu, Hong H Jiang, and Pradeep Dubey GPUs. A programmer specifies a dataflow compute in uniform perspective of programming style, Susy for FPGAs is single- recurrence equations (UREs), and a projection of the compute thread SIMD, while our language for GPUs is a mix of SIMT onto a linear systolic array in a space-time transform. We allow and SIMD. From the perspective of hardware architectures, multiple projections, arbitrary projection directions and lin- FPGAs have on-chip memory but no hardware caches, have ear schedules. Our approach has the following characteristics: massive programmable logic resources and registers, while GPUs have shared memory, hardware caches, fixed execu- 1. Generality. tion units, and limited thread-private registers, and thus the UREs and space-time transform are the theoretical foun- compiler has to optimize very differently. dation of most systolic arrays we can see in the real world. They are rigorously formulated in mathematics and have been extensively studied. By enabling them, our language and compiler are able to cover the wide range of applications to which numerous systolic arrays apply. 2. Productivity. Our language has a higher abstraction level than the popular,SIMT-basedprogramminglanguageslikeCUDA and OpenCL. Both UREs and space-time transforms are succinct math: UREs are a functional notation of a compute, and space-time transforms are expressed by matrices. Our language separates concerns of programmers. For a compute, programmers write its functional notation (UREs) and its optimizations (space-time transforms, and other loop and data optimizations) separately. Our language is a specification language: programmers only specify optimizations, but leave their detailed im- plementation to a compiler; the compiler implements the optimizations, particularly, maps linear systolic ar- rays determined by the specified space-time transforms to the SIMD execution units and vector registers of GPUs. In this way, both productivity and performance are achieved in the same time. 3. Performance. A space-time transform neatly combines loop transfor- mations, data shuffling, and vector register allocation together: it can transform a loop nest in a single shot Figure 1. The overall flow. with the combined effect of several loop transforma- tions (like loop reordering, skewing and vectorization), Fig. 1 provides a high-level overview of our system. Pro- allocation of minimum number of vector registers, and grammers write a specification, which contains two parts: (1) shuffling of the data in the registers. a temporal definition, which is a functional definition of the Meanwhile, many other optimizations can be applied compute to perform, in the form of UREs, and (2) a spatial map- aswell.Theseoptimizationsincludetiling,multi-threading, ping, which is optimizations to map the compute efficiently building a memory hierarchy with shared memory and to a GPU. These optimizations transform loops (e.g. by loop registers, etc. The compiler composes the optimizations tiling, reordering, space-time transform, etc.), enable multi- together to generate efficient code. threading, and build a memory hierarchy. In more detail, the We prototyped a system for our approach on Intel GPUs [9]. iteration space of a dataflow compute is cut into groups of We leverage Susy [18], a system that enabled UREs and lim- software threads, and scheduled group by group to a GPU ited space-time transforms for FPGAs. Susy allows only a at runtime; every software thread is mapped to a hardware single projection, and the projection direction must follow thread called Execution Unit (EU) thread. For brevity, we will a loop dimension. In our system, we break the limitations to use the term thread to refer to a software thread, and EU thread allow multiple projections and arbitrary projection directions, for its corresponding hardware thread. and generate code for GPUs, which is essentially different Unlike a traditional thread, a thread here contains a linear from FPGAs, and necessitates substantial innovation. From the systolic array, as specified by a space-time transform as part 2 Systolic GPU August, 14, 2020 of the spatial mapping. The linear systolic array is realized by the SIMD function units and vector registers in a EU thread. More specifically, every lane of a SIMD function unit isaPE, and the PEs exchange data by shuffling the vector registers that contain the data. One may view a thread here as a wrap of threads in CUDA. This is the first system that allows productive construction of systolic arrays on GPUs, to the best of our knowledge. Were- markthatalthoughthecurrentsystemtargetsonlyIntelGPUs, it is general and should be applicable
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