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Design Methods for DSP Systems EURASIP Journal on Applied Signal Processing Design Methods for DSP Systems Guest Editors: Bernhard Wess, Shuvra S. Bhattacharyya, and Markus Rupp EURASIP Journal on Applied Signal Processing Design Methods for DSP Systems EURASIP Journal on Applied Signal Processing Design Methods for DSP Systems Guest Editors: Markus Rupp, Bernhard Wess, and Shuvra S. Bhattacharyya, Copyright © 2006 Hindawi Publishing Corporation. All rights reserved. This is a special issue published in volume 2006 of “EURASIP Journal on Applied Signal Processing.” All articles are open access articles distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Editor-in-Chief Ali H. Sayed, University of California, USA Associate Editors Kenneth Barner, USA Søren Holdt Jensen, Denmark Vitor H. Nascimento, Brazil Mauro Barni, Italy Mark Kahrs, USA Sven Nordholm , Australia Richard Barton, USA Thomas Kaiser, Germany Douglas O’Shaughnessy, Canada Ati Baskurt, France Moon Gi Kang, South Korea Montse Pardas, Spain Kostas Berberidis, Greece Matti Karjalainen, Finland Wilfried Philips, Belgium Jose C. Bermudez, Brazil Walter Kellermann, Germany Vincent Poor, USA Enis Cetin, Turkey Joerg Kliewer, USA Ioannis Psaromiligkos, Canada Jonathon Chambers, UK Lisimachos P. Kondi, USA Phillip Regalia, France Benoit Champagne, Canada Alex Kot, Singapore Markus Rupp, Austria Joe Chen, USA Vikram Krishnamurthy, Canada Bill Sandham, UK Liang-Gee Chen, Taiwan Tan Lee, Hong Kong Bulent Sankur, Turkey Huaiyu Dai, USA Geert Leus, The Netherlands Erchin Serpedin, USA Satya Dharanipragada, USA Bernard C. Levy, USA Dirk Slock, France Frank Ehlers, Italy Ta-Hsin Li, USA Yap-Peng Tan, Singapore Sharon Gannot, Israel Mark Liao, Taiwan Dimitrios Tzovaras, Greece Fulvio Gini, Italy Yuan-Pei Lin, Taiwan Hugo Van hamme, Belgium Irene Gu, Sweden Shoji Makino, Japan Bernhard Wess, Austria Peter Handel, Sweden Stephen Marshall, UK Douglas Williams, USA R. Heusdens, The Netherlands C. Mecklenbräuker, Austria Roger Woods, UK Ulrich Heute, Germany Gloria Menegaz, Italy Jar-Ferr Yang, Taiwan Arden Huang, USA Ricardo Merched, Brazil Abdelhak M. Zoubir, Germany Jiri Jan, Czech Republic Rafael Molina, Spain Sudharman K. Jayaweera, USA Marc Moonen, Belgium Contents Design Methods for DSP Systems, Markus Rupp, Bernhard Wess, and Shuvra S. Bhattacharyya Volume 2006 (2006), Article ID 47817, 3 pages Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems, Nacer-Eddine Zergainoh, Ludovic Tambour, Pascal Urard, and Ahmed Amine Jerraya Volume 2006 (2006), Article ID 28636, 11 pages Multiple-Clock-Cycle Architecture for the VLSI Design of a System for Time-Frequency Analysis, Veselin N. Ivanović, Radovan Stojanović, and LJubivša Stanković Volume 2006 (2006), Article ID 60613, 18 pages 3D-SoftChip: A Novel Architecture for Next-Generation Adaptive Computing Systems, Chul Kim, Alex Rassau, Stefan Lachowicz, Mike Myung-Ok Lee, and Kamran Eshraghian Volume 2006 (2006), Article ID 75032, 13 pages Highly Flexible Multimode Digital Signal Processing Systems Using Adaptable Components and Controllers, Vinu Vijay Kumar and John Lach Volume 2006 (2006), Article ID 79595, 9 pages Rapid VLIW Processor Customization for Signal Processing Applications Using Combinational Hardware Functions, Raymond R. Hoare, Alex K. Jones, Dara Kusic, Joshua Fazekas, John Foster, Shenchih Tung, and Michael McCloud Volume 2006 (2006), Article ID 46472, 23 pages Rapid Prototyping for Heterogeneous Multicomponent Systems: An MPEG-4 Stream over a UMTS Communication Link, M. Raulet, F. Urban, J. F. Nezan, C. Moy, O. Deforges, and Y. Sorel Volume 2006 (2006), Article ID 64369, 13 pages A Fully Automated Environment for Verification of Virtual Prototypes, P. Belanović, B. Knerr, M. Holzer, and M. Rupp Volume 2006 (2006), Article ID 32408, 12 pages FPGA-Based Reconfigurable Measurement Instruments with Functionality Defined by User, Guo-Ruey Tsai and Min-Chuan Lin Volume 2006 (2006), Article ID 84340, 14 pages FPGA Implementation of an MUD Based on Cascade Filters for a WCDMA System, Quoc-Thai Ho, Daniel Massicotte, and Adel-Omar Dahmane Volume 2006 (2006), Article ID 52919, 12 pages A New Pipelined Systolic Array-Based Architecture for Matrix Inversion in FPGAs with Kalman Filter Case Study, Abbas Bigdeli, Morteza Biglari-Abhari, Zoran Salcic, and Yat Tin Lai Volume 2006 (2006), Article ID 89186, 12 pages Floating-to-Fixed-Point Conversion for Digital Signal Processors, Daniel Menard, Daniel Chillet, and Olivier Sentieys Volume 2006 (2006), Article ID 96421, 19 pages Optimum Wordlength Search Using Sensitivity Information, Kyungtae Han and Brian L. Evans Volume 2006 (2006), Article ID 92849, 14 pages Hindawi Publishing Corporation EURASIP Journal on Applied Signal Processing Volume 2006, Article ID 47817, Pages 1–3 DOI 10.1155/ASP/2006/47817 Editorial Design Methods for DSP Systems Markus Rupp,1 Bernhard Wess,1 and Shuvra S. Bhattacharyya2 1 Institute of Communications and Radio Frequency Engineering, Vienna University of Technology, Gusshausstrasse 25/389, 1040 Vienna, Austria 2 Department of Electrical & Computer Engineering, University of Maryland, College Park, MD 20742, USA Received 8 August 2005; Accepted 8 August 2005 Copyright © 2006 Markus Rupp et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Industrial implementations of DSP systems today require ter transfer level architectures for VLSI signal processing sys- extreme complexity. Examples are wireless systems satisfy- tems from high-level representations as interconnections of ing standards like WLAN or 3GPP, video components, or intellectual property (IP) blocks. The development empha- multimedia players. At the same time, often harsh con- sizes extensive parameterization and component reuse to im- straints like low-power requirements burden the designer prove productivity and flexibility. Careful generation of con- even more. Conventional methods for ASIC design are not trol structures is also performed to manage delays and coor- sufficient any more to guarantee a fast conversion from ini- dinate parallel execution. Effectiveness of the tool is demon- tial concept to final product. In industry, the problem has strated on a number of high-throughput signal processing been addressed by the wording design crisis or design gap. applications. While this design gap exists in a complexity gap, that is, a In “Multiple-clock cycle architecture for the VLSI design of difference between existing, available, and demanded com- a system for time-frequency analysis,” Veselin N. Ivanovicet´ plexity, there is also a productivity gap, that is, the dif- al. present a streamlined architecture for time-frequency sig- ference between available complexity and how much we nal analysis. The architecture enables real-time analysis of a are able to efficiently convert into gate-level representa- number of important time-frequency distributions. By pro- tions. This special issue intends to present recent solutions viding for multiple-clock-cycle operation and resource shar- to such gaps addressing algorithmic design methods, al- ing across the design in an efficient manner, the architecture gorithms for floating-to-fixed-point conversion, automatic achieves these features with relatively low hardware complex- DSP coding strategies, architectural exploration methods, ity. Results are given based on implementation of the archi- hardware/software partitioning, as well as virtual and rapid tecture on field-programmable gate arrays, and a thorough prototyping. comparison is given against a single-cycle implementation We received 20 submissions from different fields and ar- architecture. eas of expertise from which finally only 12 were accepted for In “3D-SoftChip: a novel architecture for next-generation publication. These 12 papers can be categorised into four adaptive computing systems,” C. Kim et al. present an archi- groups: pure VLSI design methods, prototyping methods, tecture for real-time communication and signal processing experimental reports on FPGAs, and floating-to-fixed-point through vertical integration of a configurable array processor conversions. subsystem and a switch subsystem. The proposed integration Most activities in design methods are related to the final is achieved by means of an indium bump interconnection ar- product. VLSI design methods intend to deal with high com- ray to provide high interconnection bandwidth at relatively plexity in a rather short time. In this special issue, we present low levels of power dissipation. The paper motivates and de- five contributions allowing to design complex VLSI designs velops the design of the proposed system architecture, along in substantially lower time periods. with its 2D subsystems and hierarchical interconnection net- In “Macrocell builder: IP-block-based design environment work. Details on hardware/software codesign aspects of the for high-throughput VLSI dedicated digital signal process- proposed system are also discussed. ing systems”, N.-E. Zergainoh et al. present a design tool, In “Highly flexible multimode digital signal processing called DSP macrocell builder, that generates SystemC regis- systems using adaptable components and controllers”,V.V. 2 EURASIP Journal on Applied Signal Processing
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