DOCSLIB.ORG

Archhdl: a Novel Hardware RTL Modeling and High-Speed Simulation Environment

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Archhdl: a Novel Hardware RTL Modeling and High-Speed Simulation Environment View metadata, citation and similar papers at core.ac.uk brought to you by CORE provided by Tsukuba Repository ArchHDL: A Novel Hardware RTL Modeling and High-Speed Simulation Environment 著者 SATO Shimpei, KOBAYASHI Ryohei, KISE Kenji journal or IEICE transactions on information and systems publication title volume E101.D number 2 page range 344-353 year 2018-02 権利 (C) 2018 The Institute of Electronics, Information and Communication Engineers URL http://hdl.handle.net/2241/00152026 doi: 10.1587/transinf.2017RCP0012 IEICE TRANS. INF. & SYST., VOL.E101–D, NO.2 FEBRUARY 2018 344 PAPER Special Section on Reconfigurable Systems ArchHDL: A Novel Hardware RTL Modeling and High-Speed Simulation Environment Shimpei SATOya), Ryohei KOBAYASHIyyb), and Kenji KISEyc), Members SUMMARY LSIs are generally designed through four stages including Architectural design and logic design are also impor- architectural design, logic design, circuit design, and physical design. In tant for hardware FPGA implementation. Available hard- architectural design and logic design, designers describe their target hard- ware resources in FPGAs are increasing, and requirements ware in RTL. However, they generally use different languages for each phase. Typically a general purpose programming language such as C or to implement a large scale hardware are also increasing. So, C++ and a hardware description language such as Verilog HDL or VHDL the elapsed time of an RTL simulation for such large scale are used for architectural design and logic design, respectively. That is design is becoming very long even if using a fast RTL sim- time-consuming way for designing a hardware and more efficient design ulator. Therefore, CAD systems which realize high-speed environment is required. In this paper, we propose a new hardware mod- eling and high-speed simulation environment for architectural design and RTL simulation are strongly required. logic design. Our environment realizes writing and verifying hardware by In this paper, we propose ArchHDL that is a novel one language. The environment consists of (1) a new hardware descrip- hardware RTL modeling and high-speed simulation envi- tion language called ArchHDL, which enables to simulate hardware faster ronment. This environment comprises of (1) a hardware de- than Verilog HDL simulation, and (2) a source code translation tool from scription language called ArchHDL which enables to simu- ArchHDL code to Verilog HDL code. ArchHDL is a new language for hardware RTL modeling based on C++. The key features of this language late a hardware faster than Verilog HDL simulation and (2) a are that (1) designers describe a combinational circuit as a function and source code translation tool from ArchHDL to Verilog HDL. (2) the ArchHDL library realizes non-blocking assignment in C++. Using In this environment, designers implement their target hard- these features, designers are able to write a hardware transparently from ware with a provided ArchHDL library based on C++. The abstracted level description to RTL description in Verilog HDL-like style. Source codes in ArchHDL is converted to Verilog HDL codes by the trans- simulation is carried by executing an ArchHDL code which lation tool and they are used to synthesize for FPGAs or ASICs. As the implements a target hardware as a C++ program For the evaluation of our environment, we implemented a practical many-core pro- following hardware design flow, the source code written in cessor in ArchHDL and measured the simulation speed on an Intel CPU ArchHDL is converted to a Verilog HDL code by the trans- and an Intel Xeon Phi processor. The simulation speed for the Intel CPU lation tool. by ArchHDL achieves about 4.5 times faster than the simulation speed by Synopsys VCS. We also confirmed that the RTL simulation by ArchHDL In ArchHDL, designers write and verify a hardware is efficiently parallelized on the Intel Xeon Phi processor. We convert the using C++ language. Designers generally use a general- ArchHDL code to a Verilog HDL code and estimated the hardware utiliza- purpose programming language such as C or C++ to de- tion on an FPGA. To implement a 48-node many-core processor, 71% of scribe a hardware in the architectural design phase. In logic entire resources of a Virtex-7 FPGA are consumed. key words: hardware description language, RTL modeling, RTL simula- design phase, they use a hardware description language such tion as Verilog HDL or VHDL to describe a hardware in RTL. Designers typically have to describe their target hardware ff 1. Introduction twice by using di erent languages and it is time-consuming way to design a hardware. ArchHDL realizes transparent and efficient hardware design from the architectural design VLSI chips such as high performance processors and SoCs phase to the logic design phase by using one programming with many hardware elements are designed in the flow of (1) language. architectural design, (2) logic design, (3) circuit design, and Our environment realizes high-speed hardware RTL (4) physical design. In architectural design and logic design, simulation. Typical Verilog HDL simulator takes a long simulations in register transfer level (RTL) are indispensable time to simulate a hardware because it can simulate a de- ffi for e cient debugging and logical verification. tailed situation including some delays. Such detailed simu- lation is necessary for hardware design. However, require- Manuscript received May 2, 2017. Manuscript revised September 8, 2017. ment for high-speed logic level simulation in RTL is also Manuscript publicized November 17, 2017. thought to be high. The RTL simulation of a hardware writ- yThe authors are with Tokyo Institute of Technology, Tokyo, ten in ArchHDL is realized by executing the program com- 152–8550 Japan. piled with a typical C++ compiler. Then, it achieves high- yy The author is with University of Tsukuba, Tsukuba-shi, 305– speed simulation compared to Verilog HDL simulation. Ad- 8571 Japan. ditionally, the ArchHDL library supports parallel execution a) E-mail: [email protected] b) E-mail: [email protected] of the simulation. This realizes more high-speed simulation c) E-mail: [email protected] of a large scale hardware which uses many modules such as DOI: 10.1587/transinf.2017RCP0012 many core processors by parallel execution. Copyright ⃝c 2018 The Institute of Electronics, Information and Communication Engineers SATO et al.: ARCHHDL: A NOVEL HARDWARE RTL MODELING AND HIGH-SPEED SIMULATION ENVIRONMENT 345 This paper is based on our previous works [1]–[3], where we proposed ArchHDL and showed preliminary eval- uation results. In this paper, we show the following contri- butions: • Providing a detailed description of ArchHDL with its library implementation. • High-speed RTL simulation of a practical hardware Fig. 1 A block diagram of sample circuit used for explanation of hard- model by ArchHDL. ware description in ArchHDL. (Xorshift random value generator) • Efficiently parallelized RTL simulation on Intel Xeon Phi processor by ArchHDL. 2. A Novel Hardware RTL Modeling Environment 2.1 Concept of ArchHDL ArchHDL is a hardware description language based on C++. It provides a C++ library for hardware RTL mod- eling. The characteristics of ArchHDL are: 1. Verilog HDL-like coding style. 2. Description of a combinational circuit as a function us- ing lambda expression of C++11. 3. Supporting non-blocking assignment. 4. Supporting user-defined data types and object-oriented programming style. 5. Cycle based simulation (not event driven). Fig. 2 A description of Xorshift pseudo random value generator in Arch- HDL. 6. Parallel simulation using OpenMP without decreasing the simulation accuracy. 7. Simple library (only about 200 lines in total). Xorshift algorithm [4]. It employs four registers and gener- The ArchHDL library includes definitions of the Mod- ates random value by XOR and shift operations. Initializa- ule class, the reg class, the wire class, and functions for sim- tion mechanisms of register values and input of seed, which ulation. Using these classes and supported non-blocking as- are contained in the sample description we present later, are signment, hardware designers can write a hardware in Ver- omitted in this figure. ilog HDL-like style. More abstracted description such as Figure 2 is a sample description of Xorshift random functional level is allowed because a hardware written in value generator in ArchHDL. Descriptions about inclusion ArchHDL is just a C++ program. It realizes transparent de- of libraries are omitted. sign of hardware from abstracted level description to RTL The Xorshift class is declared as a subclass of the Mod- level description. ule class and it represents the hardware module. A hardware To describe a combinational circuit as a function, the module is declared as a subclass of the Module class which lambda expression which is newly added to the C++ stan- is defined in the ArchHDL library. Behavior of hardware dard library called C++11 is used. Non-blocking assign- modules is mainly described by using the reg class, the wire ment, which is generally supported in hardware descrip- class, the Assign function, and the Always function, which tion languages such as Verilog HDL or VHDL, is not sup- are also defined in the library. A class defined by inheriting ported in general purpose programming languages. Arch- the Module class corresponds to a module in Verilog HDL. HDL supports non-blocking assignment by the ArchHDL Five wires and Four registers are declared in the mod- library which realized by using C++ operation overload. ule. An instance of the wire class and the reg class can be re- The simulation of a hardware is carried by the execu- garded as a wire and reg in Verilog HDL respectively. These tion of the source code written in ArchHDL compiled with classes are implemented as template classes in the ArchHDL general C++ compilers. The simulation speed is faster than library.
Load more

Recommended publications
  • Co-Simulation Between Cλash and Traditional Hdls
    MASTER THESIS CO-SIMULATION BETWEEN CλASH AND TRADITIONAL HDLS Author: John Verheij Faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS) Computer Architecture for Embedded Systems (CAES) Exam committee: Dr. Ir. C.P.R. Baaij Dr. Ir. J. Kuper Dr. Ir. J.F. Broenink Ir. E. Molenkamp August 19, 2016 Abstract CλaSH is a functional hardware description language (HDL) developed at the CAES group of the University of Twente. CλaSH borrows both the syntax and semantics from the general-purpose functional programming language Haskell, meaning that circuit de- signers can define their circuits with regular Haskell syntax. CλaSH contains a compiler for compiling circuits to traditional hardware description languages, like VHDL, Verilog, and SystemVerilog. Currently, compiling to traditional HDLs is one-way, meaning that CλaSH has no simulation options with the traditional HDLs. Co-simulation could be used to simulate designs which are defined in multiple lan- guages. With co-simulation it should be possible to use CλaSH as a verification language (test-bench) for traditional HDLs. Furthermore, circuits defined in traditional HDLs, can be used and simulated within CλaSH. In this thesis, research is done on the co-simulation of CλaSH and traditional HDLs. Traditional hardware description languages are standardized and include an interface to communicate with foreign languages. This interface can be used to include foreign func- tions, or to make verification and co-simulation possible. Because CλaSH also has possibilities to communicate with foreign languages, through Haskell foreign function interface (FFI), it is possible to set up co-simulation. The Verilog Procedural Interface (VPI), as defined in the IEEE 1364 standard, is used to set-up the communication and to control a Verilog simulator.
    [Show full text]
  • An Open-Source Python-Based Hardware Generation, Simulation
    An Open-Source Python-Based Hardware Generation, Simulation, and Verification Framework Shunning Jiang Christopher Torng Christopher Batten School of Electrical and Computer Engineering, Cornell University, Ithaca, NY { sj634, clt67, cbatten }@cornell.edu pytest coverage.py hypothesis ABSTRACT Host Language HDL We present an overview of previously published features and work (Python) (Verilog) in progress for PyMTL, an open-source Python-based hardware generation, simulation, and verification framework that brings com- FL DUT pelling productivity benefits to hardware design and verification. CL DUT generate Verilog synth RTL DUT PyMTL provides a natural environment for multi-level modeling DUT' using method-based interfaces, features highly parametrized static Sim FPGA/ elaboration and analysis/transform passes, supports fast simulation cosim ASIC and property-based random testing in pure Python environment, Test Bench Sim and includes seamless SystemVerilog integration. Figure 1: PyMTL’s workflow – The designer iteratively refines the hardware within the host Python language, with the help from 1 INTRODUCTION pytest, coverage.py, and hypothesis. The same test bench is later There have been multiple generations of open-source hardware reused for co-simulating the generated Verilog. FL = functional generation frameworks that attempt to mitigate the increasing level; CL = cycle level; RTL = register-transfer level; DUT = design hardware design and verification complexity. These frameworks under test; DUT’ = generated DUT; Sim = simulation. use a high-level general-purpose programming language to ex- press a hardware-oriented declarative or procedural description level (RTL), along with verification and evaluation using Python- and explicitly generate a low-level HDL implementation. Our pre- based simulation and the same TB.
    [Show full text]
  • Intro to Programmable Logic and Fpgas
    CS 296-33: Intro to Programmable Logic and FPGAs ADEL EJJEH UNIVERSITY OF ILLINOIS URBANA-CHAMPAIGN © Adel Ejjeh, UIUC, 2015 2 Digital Logic • In CS 233: • Logic Gates • Build Logic Circuits • Sum of Products ?? F = (A’.B)+(B.C)+(A.C’) A B Black F Box C © Adel Ejjeh, UIUC, 2015 3 Programmable Logic Devices (PLDs) PLD PLA PAL CPLD FPGA (Programmable (Programmable (Complex PLD) (Field Prog. Logic Array) Array Logic) Gate Array) •2-level structure of •Enhanced PLAs •For large designs •Has a much larger # of AND-OR gates with reduced costs •Collection of logic blocks with programmable multiple PLDs with •Larger interconnection connections an interconnection networK structure •Largest manufacturers: Xilinx - Altera Slide taken from Prof. Chehab, American University of Beirut © Adel Ejjeh, UIUC, 2015 4 Combinational Programmable Logic Devices PLAs, CPLDs © Adel Ejjeh, UIUC, 2015 5 Programmable Logic Arrays (PLAs) • 2-level AND-OR device • Programmable connections • Used to generate SOP • Ex: 4x3 PLA Slide adapted from Prof. Chehab, American University of Beirut © Adel Ejjeh, UIUC, 2015 6 PLAs contd • O1 = I1.I2’ + I4.I3’ • O2 = I2.I3.I4’ + I4.I3’ • O3 = I1.I2’ + I2.I1’ Slide adapted from Prof. Chehab, American University of Beirut © Adel Ejjeh, UIUC, 2015 7 Programmable Array Logic (PALs) • More Versatile than PLAs • User Programmable AND array followed by fixed OR gates • Flip-flops/Buffers with feedback transforming output ports into I/O ports © Adel Ejjeh, UIUC, 2015 8 Complex PLDs (CPLD) • Programmable PLD blocks (PALs) I/O Block I/O I/O
    [Show full text]
  • A Pythonic Approach for Rapid Hardware Prototyping and Instrumentation
    A Pythonic Approach for Rapid Hardware Prototyping and Instrumentation John Clow, Georgios Tzimpragos, Deeksha Dangwal, Sammy Guo, Joseph McMahan and Timothy Sherwood University of California, Santa Barbara, CA, 93106 USA Email: fjclow, gtzimpragos, deeksha, sguo, jmcmahan, [email protected] Abstract—We introduce PyRTL, a Python embedded hardware To achieve these goals, PyRTL intentionally restricts users design language that helps concisely and precisely describe to a set of reasonable digital design practices. PyRTL’s small digital hardware structures. Rather than attempt to infer a and well-defined internal core structure makes it easy to add good design via HLS, PyRTL provides a wrapper over a well- defined “core” set of primitives in a way that empowers digital new functionality that works across every design, including hardware design teaching and research. The proposed system logic transforms, static analysis, and optimizations. Features takes advantage of the programming language features of Python such as elaboration-through-execution (e.g. introspection), de- to allow interesting design patterns to be expressed succinctly, and sign and simulation without leaving Python, and the option encourage the rapid generation of tooling and transforms over to export to, or import from, common HDLs (Verilog-in via a custom intermediate representation. We describe PyRTL as a language, its core semantics, the transform generation interface, Yosys [1] and BLIF-in, Verilog-out) are also supported. More and explore its application to several different design patterns and information about PyRTL’s high level flow can be found in analysis tools. Also, we demonstrate the integration of PyRTL- Figure 1. generated hardware overlays into Xilinx PYNQ platform.
    [Show full text]
  • Nanoelectronic Mixed-Signal System Design
    Nanoelectronic Mixed-Signal System Design Saraju P. Mohanty Saraju P. Mohanty University of North Texas, Denton. e-mail: [email protected] 1 Contents Nanoelectronic Mixed-Signal System Design ............................................... 1 Saraju P. Mohanty 1 Opportunities and Challenges of Nanoscale Technology and Systems ........................ 1 1 Introduction ..................................................................... 1 2 Mixed-Signal Circuits and Systems . .............................................. 3 2.1 Different Processors: Electrical to Mechanical ................................ 3 2.2 Analog Versus Digital Processors . .......................................... 4 2.3 Analog, Digital, Mixed-Signal Circuits and Systems . ........................ 4 2.4 Two Types of Mixed-Signal Systems . ..................................... 4 3 Nanoscale CMOS Circuit Technology . .............................................. 6 3.1 Developmental Trend . ................................................... 6 3.2 Nanoscale CMOS Alternative Device Options ................................ 6 3.3 Advantage and Disadvantages of Technology Scaling . ........................ 9 3.4 Challenges in Nanoscale Design . .......................................... 9 4 Power Consumption and Leakage Dissipation Issues in AMS-SoCs . ................... 10 4.1 Power Consumption in Various Components in AMS-SoCs . ................... 10 4.2 Power and Leakage Trend in Nanoscale Technology . ........................ 10 4.3 The Impact of Power Consumption
    [Show full text]
  • Review of FPD's Languages, Compilers, Interpreters and Tools
    ISSN 2394-7314 International Journal of Novel Research in Computer Science and Software Engineering Vol. 3, Issue 1, pp: (140-158), Month: January-April 2016, Available at: www.noveltyjournals.com Review of FPD'S Languages, Compilers, Interpreters and Tools 1Amr Rashed, 2Bedir Yousif, 3Ahmed Shaban Samra 1Higher studies Deanship, Taif university, Taif, Saudi Arabia 2Communication and Electronics Department, Faculty of engineering, Kafrelsheikh University, Egypt 3Communication and Electronics Department, Faculty of engineering, Mansoura University, Egypt Abstract: FPGAs have achieved quick acceptance, spread and growth over the past years because they can be applied to a variety of applications. Some of these applications includes: random logic, bioinformatics, video and image processing, device controllers, communication encoding, modulation, and filtering, limited size systems with RAM blocks, and many more. For example, for video and image processing application it is very difficult and time consuming to use traditional HDL languages, so it’s obligatory to search for other efficient, synthesis tools to implement your design. The question is what is the best comparable language or tool to implement desired application. Also this research is very helpful for language developers to know strength points, weakness points, ease of use and efficiency of each tool or language. This research faced many challenges one of them is that there is no complete reference of all FPGA languages and tools, also available references and guides are few and almost not good. Searching for a simple example to learn some of these tools or languages would be a time consuming. This paper represents a review study or guide of almost all PLD's languages, interpreters and tools that can be used for programming, simulating and synthesizing PLD's for analog, digital & mixed signals and systems supported with simple examples.
    [Show full text]
  • Myhdl Manual Release 0.11
    MyHDL manual Release 0.11 Jan Decaluwe April 10, 2020 Contents 1 Overview 1 2 Background information3 2.1 Prerequisites.......................................3 2.2 A small tutorial on generators.............................3 2.3 About decorators.....................................4 3 Introduction to MyHDL7 3.1 A basic MyHDL simulation...............................7 3.2 Signals and concurrency.................................8 3.3 Parameters, ports and hierarchy............................9 3.4 Terminology review................................... 11 3.5 Some remarks on MyHDL and Python........................ 12 3.6 Summary and perspective................................ 12 4 Hardware-oriented types 13 4.1 The intbv class..................................... 13 4.2 Bit indexing........................................ 14 4.3 Bit slicing......................................... 15 4.4 The modbv class..................................... 17 4.5 Unsigned and signed representation.......................... 18 5 Structural modeling 19 5.1 Introduction........................................ 19 5.2 Conditional instantiation................................ 19 5.3 Converting between lists of signals and bit vectors................. 21 5.4 Inferring the list of instances.............................. 22 6 RTL modeling 23 6.1 Introduction........................................ 23 6.2 Combinatorial logic................................... 23 6.3 Sequential logic...................................... 25 6.4 Finite State Machine modeling............................
    [Show full text]
  • Small Soft Core up Inventory ©2019 James Brakefield Opencore and Other Soft Core Processors Reverse-U16 A.T
    tool pip _uP_all_soft opencores or style / data inst repor com LUTs blk F tool MIPS clks/ KIPS ven src #src fltg max max byte adr # start last secondary web status author FPGA top file chai e note worthy comments doc SOC date LUT? # inst # folder prmary link clone size size ter ents ALUT mults ram max ver /inst inst /LUT dor code files pt Hav'd dat inst adrs mod reg year revis link n len Small soft core uP Inventory ©2019 James Brakefield Opencore and other soft core processors reverse-u16 https://github.com/programmerby/ReVerSE-U16stable A.T. Z80 8 8 cylcone-4 James Brakefield11224 4 60 ## 14.7 0.33 4.0 X Y vhdl 29 zxpoly Y yes N N 64K 64K Y 2015 SOC project using T80, HDMI generatorretro Z80 based on T80 by Daniel Wallner copyblaze https://opencores.org/project,copyblazestable Abdallah ElIbrahimi picoBlaze 8 18 kintex-7-3 James Brakefieldmissing block622 ROM6 217 ## 14.7 0.33 2.0 57.5 IX vhdl 16 cp_copyblazeY asm N 256 2K Y 2011 2016 wishbone extras sap https://opencores.org/project,sapstable Ahmed Shahein accum 8 8 kintex-7-3 James Brakefieldno LUT RAM48 or block6 RAM 200 ## 14.7 0.10 4.0 104.2 X vhdl 15 mp_struct N 16 16 Y 5 2012 2017 https://shirishkoirala.blogspot.com/2017/01/sap-1simple-as-possible-1-computer.htmlSimple as Possible Computer from Malvinohttps://www.youtube.com/watch?v=prpyEFxZCMw & Brown "Digital computer electronics" blue https://opencores.org/project,bluestable Al Williams accum 16 16 spartan-3-5 James Brakefieldremoved clock1025 constraint4 63 ## 14.7 0.67 1.0 41.1 X verilog 16 topbox web N 4K 4K N 16 2 2009
    [Show full text]
  • Towards Higher-Level Synthesis and Co-Design with Python
    Towards Higher-Level Synthesis and Co-design with Python Alexandre Quenon Vitor Ramos Gomes da Silva [email protected] [email protected] University of Mons University of Mons Mons, Belgium Mons, Belgium ABSTRACT In this paper, we promote the idea to go further in the concept of Several methods have arisen to fasten the hardware design process. high-level synthesis and co-design thanks to the Python program- Among them, the high-level synthesis (HLS), i.e., the use of a higher- ming language. We believe that making hardware and software level programming language than the usual Verilog or VHDL to designers work closer will fasten production and generate inno- create an implementation of a register transfer level (RTL). In this vation. We start by reviewing shortly the existing frameworks for paper, the direction towards even higher-level synthesis is promoted HLS, as well as higher-level HDLs, in section2. Then, in section3, with the use of Python as a high-level language/interface. Existing we focus on Python and propose strategies of hardware accelera- HLS frameworks and high-level hardware description languages tion to use this high-level language directly on an FPGA. Section4 are reviewed, then strategies to use Python code directly on the summarizes the main ideas and draws the conclusions. hardware are proposed. This brings the power of scientific high- level computation libraries of Python to the hardware design, which 2 A SHORT OVERVIEW OF HIGH-LEVEL we believe is the ultimate goal of HLS. SYNTHESIS FRAMEWORKS AND HARDWARE DESCRIPTION LANGUAGES KEYWORDS On the one hand, many high-level hardware description languages FPGA, framework, hardware description language (HDL), high- have been designed for more than twenty years.
    [Show full text]
  • Wesley New, FPGA Toolflows, Casper and Beyond
    FPGA Tool-flows: CASPER and Beyond Wesley New SKA-SA [email protected] Who am I? • SKA-SA • DBE Team - Digital Back End • Real-time data processing • Use FPGA based hardware • ROACH Board • CASPER Collaboration ! ! Aims • Provide and overview of FPGA technologies • Introduce the CASPER Collaboration • Examine the CASPER FPGA Design-flow • Introductions to the tutorials • Discuss the future of FPGA design-flows and how CASPER and SKA can take advantage of these ! ! Background: FPGAs • FPGA - Field Programmable Gate Array • Effectively a reconfigurable semiconductor • Consists of Logic Elements and Interconnects • Well suited to parallel DSP computing • Contain Hard Cores • Getting progressively more complex • Design for FPGAs using Hardware Description Languages (HDL) Verilog and VHDL • There is a move towards higher-level design • CPU, GPU, FPGA, ASIC ! ! ! FPGA: Logic and Interconnects FPGA Vendors • 2 Major players, Xilinx and Altera plus a few smaller ones • Each provide there own software for designing for their FPGAs • Xilinx - ISE/Vivado • Altera - Quartus • Both offer plug-ins for Simulink to take advantage of block diagram style design and simulation • Complexities of porting designs between vendors • IP specific to a vendor ! HDL (HW Description Lang) • 2 Major languages Verilog and VHDL • Verilog more of a C syntax • HDL use the event-driven methodology • Generally values of registers change on the edges of clocks ! ! CPU v GPU v FPGA v ASIC • Tradeoffs, tradeoffs, tradeoffs • ASICs, Long time to develop, hard to make changes, high NRE costs, run at a higher speed • FPGAs, Short development time, expensive per unit, bad at floating-point, highly reconfigurable • GPU, Easier to design for, good at floating-point, high power consumption • CPU, very general purpose, easy to develop for, lower performance ! ! FPGA vs ASIC Cost Per Unit HDL vs Traditions SW • HDL is very susceptible to bad coding • This can make designs use more power and resources • The way of thinking when writing in an HDL is very different to software.
    [Show full text]
  • A Scientist's Guide to Fpgas Ascientistsguidetofpgas
    A Scientist’s Guide to FPGAs iCSC 2019 Alexander Ruede (CERN/KIT-IPE) Content 1. Introduction 2. The Emergence of FPGAs 3. Digital Design 4. Anatomy of FPGAs 5. Classical Design Flow 6. CPU / GPU vs. FPGA 7. Pros & Cons 8. Applications 9. Examples 10. Getting Started A Scientist’s Guide to FPGAs – Alexander Ruede – iCSC 2019 2 1. Introduction FPGA: Field-Programmable Gate Array market • Growing applications of FPGAs popularity • Well established in HEP experiments • Finding the way into data centers • Can be substitution for: • ASICs (traditionally) • Processors (recently) A Scientist’s Guide to FPGAs – Alexander Ruede – iCSC 2019 3 2. The Emergence of FPGAs 1961: First IC-based 1959: Invention 1959: First Integrated Computer of the MOSFET Circuit (IC) 1963: CMOS 1965: Moore’s Law 1975: Programmable Logic Array (PLA) 1985: First FPGA (Xilinx XC2064) 2015: Intel 1983: EEPROM & acquires Altera 2016: 16nm Virtex FLASH Memory UltraScale+ Note: All dates are rather indicative than exact A Scientist’s Guide to FPGAs – Alexander Ruede – iCSC 2019 4 3. Digital Design Digital Logic Truth table of logical function • Digital information is processed and stored in binary form NAND • Boolean algebra and truth tables are logical gate used to express combinatorial logic circuits • Basic logical function (AND, OR, etc.) are abstracted in logical gates • Gates can efficiently be implemented in Transistor transistor circuits (e.g. CMOS) circuit • Every logical function can be implemented (CMOS) by using gates A Scientist’s Guide to FPGAs – Alexander Ruede – iCSC 2019 5 3. Digital Design Digital Building Blocks and Processes NAND NOR There are two kinds of processes with different building blocks: 1.
    [Show full text]
  • Digital Electronics 2: Introduction
    Digital Electronics 2: Introduction Martin Schoeberl Technical University of Denmark Embedded Systems Engineering February 4, 2021 1 / 68 Overview I Remote teaching and learning I Motivation and the digital abstraction I Course organization I Languages for digital hardware design I A first round of Chisel I Tools and tool setup I Lab: a hardware “Hello World” 2 / 68 Remote Learning I First: this is all new for the most of us I We need to be patient with each other I We should use Slack for quicker communication I Zoom for lecturing and lab: you are already there I Please have your camera on I Please mute your mic when not talking I Some nice features I You can raise your hand I You can ask questions with the mic or on chat I Everyone can share their screen or an individual window 3 / 68 Lab/Exercise Organization I Everyone at DTU can use the professional version of Zoom I http://dtudk.zoom.us/signin I You can also use Zoom for your group work I Zoom will also be used for the supervised lab I We will keep this Zoom meeting running with breakout rooms I Schedule a TA for help with Slack I You can also schedule a Zoom meeting with me at other times I This is a chance to learn how to collaborate remotely I This will be part of your future work as an engineer anyway I This experiment might change how we teach in the future 4 / 68 Lab Work I We will stick to the plan of a working Vending Machine I At the end it shall run in your FPGA board I I am a big fan of running stuff in real hardware I Demo your work to a TA via the camera I I know many
    [Show full text]