View metadata, citation and similar papers at core.ac.uk brought to you by CORE provided by Tsukuba Repository ArchHDL: A Novel Hardware RTL Modeling and High-Speed Simulation Environment 著者 SATO Shimpei, KOBAYASHI Ryohei, KISE Kenji journal or IEICE transactions on information and systems publication title volume E101.D number 2 page range 344-353 year 2018-02 権利 (C) 2018 The Institute of Electronics, Information and Communication Engineers URL http://hdl.handle.net/2241/00152026 doi: 10.1587/transinf.2017RCP0012 IEICE TRANS. INF. & SYST., VOL.E101–D, NO.2 FEBRUARY 2018 344 PAPER Special Section on Reconfigurable Systems ArchHDL: A Novel Hardware RTL Modeling and High-Speed Simulation Environment Shimpei SATOya), Ryohei KOBAYASHIyyb), and Kenji KISEyc), Members SUMMARY LSIs are generally designed through four stages including Architectural design and logic design are also impor- architectural design, logic design, circuit design, and physical design. In tant for hardware FPGA implementation. Available hard- architectural design and logic design, designers describe their target hard- ware resources in FPGAs are increasing, and requirements ware in RTL. However, they generally use different languages for each phase. Typically a general purpose programming language such as C or to implement a large scale hardware are also increasing. So, C++ and a hardware description language such as Verilog HDL or VHDL the elapsed time of an RTL simulation for such large scale are used for architectural design and logic design, respectively. That is design is becoming very long even if using a fast RTL sim- time-consuming way for designing a hardware and more efficient design ulator. Therefore, CAD systems which realize high-speed environment is required. In this paper, we propose a new hardware mod- eling and high-speed simulation environment for architectural design and RTL simulation are strongly required. logic design. Our environment realizes writing and verifying hardware by In this paper, we propose ArchHDL that is a novel one language. The environment consists of (1) a new hardware descrip- hardware RTL modeling and high-speed simulation envi- tion language called ArchHDL, which enables to simulate hardware faster ronment. This environment comprises of (1) a hardware de- than Verilog HDL simulation, and (2) a source code translation tool from scription language called ArchHDL which enables to simu- ArchHDL code to Verilog HDL code. ArchHDL is a new language for hardware RTL modeling based on C++. The key features of this language late a hardware faster than Verilog HDL simulation and (2) a are that (1) designers describe a combinational circuit as a function and source code translation tool from ArchHDL to Verilog HDL. (2) the ArchHDL library realizes non-blocking assignment in C++. Using In this environment, designers implement their target hard- these features, designers are able to write a hardware transparently from ware with a provided ArchHDL library based on C++. The abstracted level description to RTL description in Verilog HDL-like style. Source codes in ArchHDL is converted to Verilog HDL codes by the trans- simulation is carried by executing an ArchHDL code which lation tool and they are used to synthesize for FPGAs or ASICs. As the implements a target hardware as a C++ program For the evaluation of our environment, we implemented a practical many-core pro- following hardware design flow, the source code written in cessor in ArchHDL and measured the simulation speed on an Intel CPU ArchHDL is converted to a Verilog HDL code by the trans- and an Intel Xeon Phi processor. The simulation speed for the Intel CPU lation tool. by ArchHDL achieves about 4.5 times faster than the simulation speed by Synopsys VCS. We also confirmed that the RTL simulation by ArchHDL In ArchHDL, designers write and verify a hardware is efficiently parallelized on the Intel Xeon Phi processor. We convert the using C++ language. Designers generally use a general- ArchHDL code to a Verilog HDL code and estimated the hardware utiliza- purpose programming language such as C or C++ to de- tion on an FPGA. To implement a 48-node many-core processor, 71% of scribe a hardware in the architectural design phase. In logic entire resources of a Virtex-7 FPGA are consumed. key words: hardware description language, RTL modeling, RTL simula- design phase, they use a hardware description language such tion as Verilog HDL or VHDL to describe a hardware in RTL. Designers typically have to describe their target hardware ff 1. Introduction twice by using di erent languages and it is time-consuming way to design a hardware. ArchHDL realizes transparent and efficient hardware design from the architectural design VLSI chips such as high performance processors and SoCs phase to the logic design phase by using one programming with many hardware elements are designed in the flow of (1) language. architectural design, (2) logic design, (3) circuit design, and Our environment realizes high-speed hardware RTL (4) physical design. In architectural design and logic design, simulation. Typical Verilog HDL simulator takes a long simulations in register transfer level (RTL) are indispensable time to simulate a hardware because it can simulate a de- ffi for e cient debugging and logical verification. tailed situation including some delays. Such detailed simu- lation is necessary for hardware design. However, require- Manuscript received May 2, 2017. Manuscript revised September 8, 2017. ment for high-speed logic level simulation in RTL is also Manuscript publicized November 17, 2017. thought to be high. The RTL simulation of a hardware writ- yThe authors are with Tokyo Institute of Technology, Tokyo, ten in ArchHDL is realized by executing the program com- 152–8550 Japan. piled with a typical C++ compiler. Then, it achieves high- yy The author is with University of Tsukuba, Tsukuba-shi, 305– speed simulation compared to Verilog HDL simulation. Ad- 8571 Japan. ditionally, the ArchHDL library supports parallel execution a) E-mail: [email protected] b) E-mail: [email protected] of the simulation. This realizes more high-speed simulation c) E-mail: [email protected] of a large scale hardware which uses many modules such as DOI: 10.1587/transinf.2017RCP0012 many core processors by parallel execution. Copyright ⃝c 2018 The Institute of Electronics, Information and Communication Engineers SATO et al.: ARCHHDL: A NOVEL HARDWARE RTL MODELING AND HIGH-SPEED SIMULATION ENVIRONMENT 345 This paper is based on our previous works [1]–[3], where we proposed ArchHDL and showed preliminary eval- uation results. In this paper, we show the following contri- butions: • Providing a detailed description of ArchHDL with its library implementation. • High-speed RTL simulation of a practical hardware Fig. 1 A block diagram of sample circuit used for explanation of hard- model by ArchHDL. ware description in ArchHDL. (Xorshift random value generator) • Efficiently parallelized RTL simulation on Intel Xeon Phi processor by ArchHDL. 2. A Novel Hardware RTL Modeling Environment 2.1 Concept of ArchHDL ArchHDL is a hardware description language based on C++. It provides a C++ library for hardware RTL mod- eling. The characteristics of ArchHDL are: 1. Verilog HDL-like coding style. 2. Description of a combinational circuit as a function us- ing lambda expression of C++11. 3. Supporting non-blocking assignment. 4. Supporting user-defined data types and object-oriented programming style. 5. Cycle based simulation (not event driven). Fig. 2 A description of Xorshift pseudo random value generator in Arch- HDL. 6. Parallel simulation using OpenMP without decreasing the simulation accuracy. 7. Simple library (only about 200 lines in total). Xorshift algorithm [4]. It employs four registers and gener- The ArchHDL library includes definitions of the Mod- ates random value by XOR and shift operations. Initializa- ule class, the reg class, the wire class, and functions for sim- tion mechanisms of register values and input of seed, which ulation. Using these classes and supported non-blocking as- are contained in the sample description we present later, are signment, hardware designers can write a hardware in Ver- omitted in this figure. ilog HDL-like style. More abstracted description such as Figure 2 is a sample description of Xorshift random functional level is allowed because a hardware written in value generator in ArchHDL. Descriptions about inclusion ArchHDL is just a C++ program. It realizes transparent de- of libraries are omitted. sign of hardware from abstracted level description to RTL The Xorshift class is declared as a subclass of the Mod- level description. ule class and it represents the hardware module. A hardware To describe a combinational circuit as a function, the module is declared as a subclass of the Module class which lambda expression which is newly added to the C++ stan- is defined in the ArchHDL library. Behavior of hardware dard library called C++11 is used. Non-blocking assign- modules is mainly described by using the reg class, the wire ment, which is generally supported in hardware descrip- class, the Assign function, and the Always function, which tion languages such as Verilog HDL or VHDL, is not sup- are also defined in the library. A class defined by inheriting ported in general purpose programming languages. Arch- the Module class corresponds to a module in Verilog HDL. HDL supports non-blocking assignment by the ArchHDL Five wires and Four registers are declared in the mod- library which realized by using C++ operation overload. ule. An instance of the wire class and the reg class can be re- The simulation of a hardware is carried by the execu- garded as a wire and reg in Verilog HDL respectively. These tion of the source code written in ArchHDL compiled with classes are implemented as template classes in the ArchHDL general C++ compilers. The simulation speed is faster than library.