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ACSS Apr 1986.Pdf (898.3Kb Application/Pdf) The fA©®® University of Minnesota Twin Cities April 1986 ComPUting Reflections Seymour Cray's Machines (Part 1) Lawrence Liddiard Seymour Cray is known as the man the CDC 1604 (serial number 50) functional units, floating point who has been the chief architect of and CDC 160 computers, new in arithmetic with infinite and seven remarkable computers since 1962, the CDC 6600 (serial indefinite values, a sequential 1958. The seven machines are number 16), new in 1966, a slightly instruction stack, and it only cost the 1604, 160,6600, and 7600 used CRAY-1 (serial number 12) $7 million. In fact, the $7 million I systems of Control Data Corpora- acquired in 1981, and the CRAY-2 price tag seemed to be the right tion (CDC) and the CRAY-1, -2, (serial number3), new in 1985. price during 1966-1976 for a and -3 of Cray Research lncorpo- The CDC 1604 retired in 1968, the leading-edge computer, since it rated (CRI), and all of them, except CDC 6600 was replaced in 1974 by also was the approximate price for the 7600, were, are, or will be part its twin sister the CYBER 74, which the CDC 7600 and the CRA Y-1 . The CDC 7600 added the "00 of the computing resources used finally retired in 1983, and the l at the University of Minnesota. CRAY -1 will be put out to pasture in concepts of "pipe lined parallel 1986. arithmetic units" (the precursor of The first director of computing at vector units on the C RAY -1) and Minnesota, Dr. Marvin Stein, once The CDC 1604 made major the associative instruction stack. A told me about a conversation he advances over previous machines, minor aberration was introduced on had with a former Electrical such as the 48-bit word length that the CDC 7600 because it had both Engineering graduate of the gave floating point numbers a 10 to fast small and slower large core University in the late '50s. During the 616 exponent range, memories for single and eight-word 1 that visit, the graduate, Seymour compared to the 10 to the 76 loads/stores. Core memory was the Cray, offered the University a range on competing systems, and speed bottleneck in the design of chance to share in the develop- the current IEEE standard single the 7600 and represented 80 I ment of a new 48-bit word precision. In other respects the percent of the component cost. computer made with transistors. CDC 1604 combined elements of Lacking the necessary funds (a the earlier UNIVAC 11 03, besides Cray corrected this deviation from common University problem), using memory banking and the right path in the CRAY -1, which Dr. Stein turned down that offer, packing two instructions per word. used chips for memory that other and Mr. Cray went on to be the manufacturers had used only for architect of CDC computers. But the CDC 6600 was the first of high-speed register files. The Cray's major scientific computer CRAY-1 introduced "vector Not withstanding this early advances: It included a simpified registers" with corresponding ; rejection of Cray's work, the instruction set, register files, pipelined parallel vector functional University of Minnesota acquired parallel operation both with 1/0 units, returned to a uniformly fast processors and arithmetic Continued on page 50 I If April1986 49 i l r Continued from page 49 (3} "Hardwired control provides for divide instruction, a harder the fastest possible single-cycle process, did not have a /4 cycle memory, and extended operation. Microcode leads to corresponding lower command to the exponent range to 10 to the slower control paths and adds to produce the division remainder, 4960 while adding a post­ interpretive overhead." and thus a fairly long sequence of operation floating point error commands was needed to detection and recovery. (4} "Relatively few instructions and produce the answer for a double addressing modes facilitate a fast, precision divide. simple interpretation by the control Simplified Instruction Set engine." Seymour Gray was always looking for the fastest execution rates, and In the early 1980's the concept of (5} "Fixed instruction format with normal arithmetic rounding reduced instruction set computers consistent use eases the hard­ requires that the round bit be (RISC} as opposed to the then­ wired decoding of instructions, added after any normalization in an current complex (CISC} machines which again speeds control paths." additive or multiplicative operation began to be promoted within to correctly produce the rounded academia. The first VLSI chip (6} "More compile-time effort offers result. Since this can add several using that concept was called the an opportunity to explicitly move cycles to a command, the 6600 RISC I in a journal article by a group static run-time complexity into the and 7600 were designed to have at the University of California, compiler." the round bits added before the Berkeley. In that article, 1 the operation took place in the additive authors wrote: From that proposed definition of a (1/2 bit} and divide (1/3 bit} RISC, it does seem that Gray's operations. Since a post­ Since architects of new machines machines from the 6600 onward normalization down-shift of 1 bit build on the work of others, we could be considered RISC types. can occur, the rounding for those believe it is important to trace the That same reference shows that cases is sometimes only by 1/4 bit genealogy of RISG I. The the RISC I register file, organized or 1/6 bit respectively. CDC initially leading proponent of reduced as a series of overlapping registers delivered 6600s with the rounded instruction set computers for that enabled fast procedure calls, multiply adding a 1/2 bit before the floating-point data is [Seymour] was a large part of the performance post-normalization, which caused a Gray. For the last 15 years, he has improvement seen on that system. bit to be added in the lowest combined simple instruction sets Perhaps the GRAY -2 should have position for product results that with sophisticated pipelined organized its local memory to have shifted up the one-bit maximum. implementations to create the most similar procedure call speedups. This meant that integer products powerful floating-point engines in At ACSS we have always such as 1*1 received an answer the world. While Gray concentrates considered the CDC 6600 and 1/2** 47 too large. All of the 6600s on impressive floating-point rates CYBER 74 as the world's largest were corrected to round only by a at impressive costs, RISG I and fastest micro engines. 1/4 bit before the post­ concentrates on improved normalization, giving a resulting performance at lower cost for round of 1/2 or 1/4. Numerical integer programs written in HLLs analysts have included these Gray [Higher Level Languages]. Floating Point Arithmetic: arithmetic rounding anomalies in Rounding programming puzzles and articles Not all agree that RISC is the wave on how not to design rounded of the future,2 but some observers In the CDC 6600 and 7600, there arithmetic. propose "the following elements were hidden 96-bit registers used as a working definition of a RISC":3 in computing the full product, In our FORTRAN compilers (MNF addition, or subtraction results of and M77}, running a program with (1 } "Single-cycle operation two 48-bit mantissas of floating rounded arithmetic usually facilitates the rapid execution of point values. The instruction set produces more accurate answers simple functions that dominate a had separate commands to obtain and, combined with a run with computer's instruction stream and the upper or lower 48 bits of these unrounded arithmetic, quickly promotes a low interpretive results. Then double precision shows if loss of significant digits is overhead." arithmetic could be done, taking occurring at a cost penalty of only approximately four times longer two (i.e., often cheaper than (2} "Load/Store design follows than single precision with short converting to DOUBLE from a desire for single-cycle sequences of these upper and PRECISION or INTERVAL operation." lower precision commands. The arithmetic}. 50 April1986 Next month I will continue to Notes SIGMICRONewsletter, Vol.14, examine Seymour Gray's No. 4 (December 1983). machines, discussing some of the 1 David A. Patterson and Carlo other innovative ways Cray solved Sequin, "A VLSI RISC," IEEE 3Robert P. Colwell, Charles Y. floating point arnhmetic problems Computer, Vol.15, No.9 Hnchcock Ill, E. Douglas Jensen, and also examining some of the (September 1982). H. M. Brinkley Sprunt, and Charles interesting features of his machine P. Kollar, "Computers, Complexity, designs. 2William C. Hopkins, "HLLDA and Controversy," IEEE Computer, defines RISC: Thoughts on RISCs, Vol. 18, No.9 (September 1985). CISCs, and HLLDAs," ACM PrO!)rammjag Languages Programming Languages on the VAX 8600: An Overview Jim Miner and Janet Eberhart Wnh the advent of VAX 8600 services. This all adds up to a VAX Ada is a validated service, we are introducing some versatile and powerful environment implementation of the ANSI- and I new language processors and for developing and maintaining DOD-standard language. It is "' upgrading the existing ones as sophisticated applications. integrated into the VMS Common well. FORTRAN and Pascal are the Language Environment. All VMS perennial favorite languages on system services and utilities are our systems, and we have a new Ada® thus available to programs wrnten version of each. There is also a in VAX Ada. VAX Ada supports new version of COBOL and new Ada is a powerful, general-purpose VAX Record Management Ada, Common LISP, and OPSS language wnh integrated facilities Services (RMS).
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