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Computer Architecture Overview ICS332 — Operating Systems History Von Neumann Model Fetch-Decode-Execute Cycle Speeding Things Up Conclusion Computer Architecture Overview ICS332 | Operating Systems Henri Casanova ([email protected]) Spring 2018 Henri Casanova ([email protected]) Computer Architecture Overview Main sponsor: University of Pennsylvania / Ballistic Research Laboratory ($487k eq. 2016 $7M) Designers: Mauchly and Eckert First operators (i.e., programmers): The 6 \ENIAC Girls" (McNulty, Jennings, Snyder, Wescoff, Bilas, and Lichterman) History Von Neumann Model ENIAC Fetch-Decode-Execute Cycle Von Neumann Model Speeding Things Up Conclusion 1946 | ENIAC Electronic Numerical Integrator And Computer aka \Giant Brain" First electronic general-purpose computer Before that, \were humans, who could use non-programmable mechanical and later electrical computation tools Could be reprogrammed (Stored-Program Computer instead of Fixed-Program Computer) Henri Casanova ([email protected]) Computer Architecture Overview History Von Neumann Model ENIAC Fetch-Decode-Execute Cycle Von Neumann Model Speeding Things Up Conclusion 1946 | ENIAC Electronic Numerical Integrator And Computer aka \Giant Brain" First electronic general-purpose computer Before that, \were humans, who could use non-programmable mechanical and later electrical computation tools Could be reprogrammed (Stored-Program Computer instead of Fixed-Program Computer) Main sponsor: University of Pennsylvania / Ballistic Research Laboratory ($487k eq. 2016 $7M) Designers: Mauchly and Eckert First operators (i.e., programmers): The 6 \ENIAC Girls" (McNulty, Jennings, Snyder, Wescoff, Bilas, and Lichterman) Henri Casanova ([email protected]) Computer Architecture Overview History Von Neumann Model ENIAC Fetch-Decode-Execute Cycle Von Neumann Model Speeding Things Up Conclusion 1946 | ENIAC (Features) 1000x faster than (specialized) electro-mechanical equivalent 2400x times faster than (specialized) human being (30 seconds instead of 20 hours) 100 kHz / 5 kIPS (now: 4GHz / 5,000 MIPS) 1,000 bits of RAM (i.e., 0.12 KiB) 150 kW (now: 200W) 17,468 vacuum tubes (failure prone, power hungry) 8 × 3 × 100 ft; 27 metric tons (60,000 pounds) Henri Casanova ([email protected]) Computer Architecture Overview History Von Neumann Model ENIAC Fetch-Decode-Execute Cycle Von Neumann Model Speeding Things Up Conclusion 1946 | ENIAC (Pictures) Henri Casanova ([email protected]) Computer Architecture Overview History Von Neumann Model ENIAC Fetch-Decode-Execute Cycle Von Neumann Model Speeding Things Up Conclusion 1946 | ENIAC (Pictures) Henri Casanova ([email protected]) Computer Architecture Overview History Von Neumann Model ENIAC Fetch-Decode-Execute Cycle Von Neumann Model Speeding Things Up Conclusion 1946 | ENIAC (Pictures) Henri Casanova ([email protected]) Computer Architecture Overview This became the Von Neumann Architecture Model A Central Processing Unit performs operations and controls the sequence of operations A Memory Unit contains code and data Some kind of Input and Output mechanisms (I/O) History Von Neumann Model ENIAC Fetch-Decode-Execute Cycle Von Neumann Model Speeding Things Up Conclusion Von Neumann ENIAC design frozen in 1943; Eckert and Mauchly work on a new design: the EDVAC 1944: Von Neumann (1903-1957) joins Eckert and Mauchly, writes a memo formalizing their ideas Henri Casanova ([email protected]) Computer Architecture Overview History Von Neumann Model ENIAC Fetch-Decode-Execute Cycle Von Neumann Model Speeding Things Up Conclusion Von Neumann ENIAC design frozen in 1943; Eckert and Mauchly work on a new design: the EDVAC 1944: Von Neumann (1903-1957) joins Eckert and Mauchly, writes a memo formalizing their ideas This became the Von Neumann Architecture Model A Central Processing Unit performs operations and controls the sequence of operations A Memory Unit contains code and data Some kind of Input and Output mechanisms (I/O) Henri Casanova ([email protected]) Computer Architecture Overview Today a computer looks more CPU Disk Controller USB Controller Graphics Adapter like: Memory History Von Neumann Model Von Neumann Model Fetch-Decode-Execute Cycle Memory Unit Speeding Things Up Central Processing Unit Conclusion Von Neumann Model Amazingly it is still possible to CPU () Memory think of the computer this way at a m conceptual level (model from ∼70 years ago!) I/O Henri Casanova ([email protected]) Computer Architecture Overview CPU Disk Controller USB Controller Graphics Adapter Memory History Von Neumann Model Von Neumann Model Fetch-Decode-Execute Cycle Memory Unit Speeding Things Up Central Processing Unit Conclusion Von Neumann Model Amazingly it is still possible to CPU () Memory think of the computer this way at a m conceptual level (model from ∼70 years ago!) I/O Today a computer looks more like: Henri Casanova ([email protected]) Computer Architecture Overview History Von Neumann Model Von Neumann Model Fetch-Decode-Execute Cycle Memory Unit Speeding Things Up Central Processing Unit Conclusion Von Neumann Model Amazingly it is still possible to CPU () Memory think of the computer this way at a m conceptual level (model from ∼70 years ago!) I/O Today a computer looks more CPU Disk Controller USB Controller Graphics Adapter like: Memory Bus Memory Henri Casanova ([email protected]) Computer Architecture Overview History Von Neumann Model Von Neumann Model Fetch-Decode-Execute Cycle Memory Unit Speeding Things Up Central Processing Unit Conclusion Von Neumann Model: Origins 1847: Boolean algebra { Truth value (true / false), Boolean logic, Bit (binary digit) 1937: Shannon's MS Thesis { Any logical, numerical relationship can be built using Boolean algebra Therefore, any \information" can be represented in binary form, and therefore we can build computers that only understand binary Building computers this way is technologically convenient: 0 Volt: False (0) ∼5 Volt: True (1) Henri Casanova ([email protected]) Computer Architecture Overview History Von Neumann Model Von Neumann Model Fetch-Decode-Execute Cycle Memory Unit Speeding Things Up Central Processing Unit Conclusion The Von Neumann Architecture CPU () Memory m I/O Henri Casanova ([email protected]) Computer Architecture Overview History Von Neumann Model Von Neumann Model Fetch-Decode-Execute Cycle Memory Unit Speeding Things Up Central Processing Unit Conclusion Memory Unit Called Memory or RAM (Random Access Memory) for short I will say \memory" or \RAM" interchangeably The basic unit of memory is the byte (or octet, or octad, or octade) 1 Byte = 8 bits, e.g., \0110 1011" Henri Casanova ([email protected]) Computer Architecture Overview History Von Neumann Model Von Neumann Model Fetch-Decode-Execute Cycle Memory Unit Speeding Things Up Central Processing Unit Conclusion Memory Unit The memory contains numerical \information" / \data" / \content" Content 3 1 4 1 25 9 2 167 -5 ... Henri Casanova ([email protected]) Computer Architecture Overview History Von Neumann Model Von Neumann Model Fetch-Decode-Execute Cycle Memory Unit Speeding Things Up Central Processing Unit Conclusion Memory Unit The \data" are represented in memory in binary as bytes Content (Human) 0000 0011 3 0000 0001 1 0000 0100 4 0000 0001 1 0001 1001 25 0000 1001 9 0000 0010 2 1010 0111 167 1111 1011 -5 ... ... Henri Casanova ([email protected]) Computer Architecture Overview History Von Neumann Model Von Neumann Model Fetch-Decode-Execute Cycle Memory Unit Speeding Things Up Central Processing Unit Conclusion Memory Unit To be used, the data need to be located precisely in memory: addresses Address Content (Human) 0 0000 0011 3 1 0000 0001 1 2 0000 0100 4 3 0000 0001 1 4 0001 1001 25 5 0000 1001 9 6 0000 0010 2 7 1010 0111 167 8 1111 1011 -5 ... ... ... Henri Casanova ([email protected]) Computer Architecture Overview History Von Neumann Model Von Neumann Model Fetch-Decode-Execute Cycle Memory Unit Speeding Things Up Central Processing Unit Conclusion Memory Unit ... but because computers only understand binary, the addresses are binary too: Address Content (Human) 0000 0000 0000 0011 3 0000 0001 0000 0001 1 0000 0010 0000 0100 4 0000 0011 0000 0001 1 0000 0100 0001 1001 25 0000 0101 0000 1001 9 0000 0110 0000 0010 2 0000 0111 1010 0111 167 0000 1000 1111 1011 -5 ... ... ... Henri Casanova ([email protected]) Computer Architecture Overview The CPU has instructions like \Read the byte at address X and give me its value" and \Write this value into the byte at address Y" The Memory Unit (Bus + RAM) has the hardware to make these instructions happen History Von Neumann Model Von Neumann Model Fetch-Decode-Execute Cycle Memory Unit Speeding Things Up Central Processing Unit Conclusion Memory Unit Each byte in memory is labeled by a unique address We talk of a byte-addressable memory All addresses on a computer have the same number of bits (e.g., 16-bit addresses) Henri Casanova ([email protected]) Computer Architecture Overview History Von Neumann Model Von Neumann Model Fetch-Decode-Execute Cycle Memory Unit Speeding Things Up Central Processing Unit Conclusion Memory Unit Each byte in memory is labeled by a unique address We talk of a byte-addressable memory All addresses on a computer have the same number of bits (e.g., 16-bit addresses) The CPU has instructions like \Read the byte at address X and give me its value" and \Write this value into the byte at address Y" The Memory Unit (Bus + RAM) has the hardware to make these instructions happen Henri Casanova ([email protected]) Computer Architecture Overview At address 0000 0000 0000 0011 the content is 0000 0001 (The contents
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