International Journal of Scientific & Engineering Research, Volume 7, Issue 11, November-2016 1271 ISSN 2229-5518 Evaluation of CPU architecture by simulation technologies and benchmark computer systems Madiha Yousafa, Muhammad Harisb abCOMSATS Institute of Information Technology Park Road, Tarlai Kalan, Islamabad-45550, Pakistan
[email protected] Abstract— The processor architecture designers face major challenges to improve the processor’s performance. To measure the performance of the processor there are many parameter like performance of cache, TLB, IO operations, bus speed etc. Different companies launch series of processors with same base configuration and a little change of variations base on cache size, cache levels, share and separate cache and many other parameters like that. There are many simulators available to measure processor's performance theoretically with several parameters. We simulate some models of Intel Pentium 4 and UltraSPARC II processors and analyze the performance of the processors regarding cache and TLB. Keywords: ISTC (Instruction Simulator Translation Caches), DSTC (Data Simulator Translation Caches) —————————— —————————— 1 INTRODUCTION LSI design and developer companies like Intel, SUN, It stands for multimedia extensions and was developed by V AMD and IBM are also working in the field of processor- the Intel to increase the speed of multi media design. Before moving on we must first discuss that what operations. [6] is processor design and the factors on which it depends. Designing a computer processor in such a way that cycle time, In addition to above mentioned technologies, the architec- reliability, performance, chip area and many other issues are tures like P4 Netburst were very helpful to improve proces- resolved.