DOCSLIB.ORG

Multi-Platform Based Design Wallchart 2013

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text

Load more

MULTI-PLATFORM BASED DESIGN WALLCHART 2013 FOUNDATION PLATFORMS Foundation Platforms Product Markets Targeted Allwinner Technology A Series mobile, consumer Apple Ax consumer Applied Micro X-Gene networking Broadcom several networking, consumer Calxeda EnergyCore servers Cavium ECONA networking OCTEON networking PureVu video processing Conexant CX92125 computing CSR plc Quatro computing SIRF auto CSR8000 audio Freescale i.MX industrial, medical, auto, consumer QorIQ consumer, industrial, networking Intel Atom mobile Marvell ARMADA PX series consumer, mobile, networking, servers MediaTek MT series mobile, consumer Mindspeed Comcerto networking Nordic Semiconductor ANT sensors Nvidia Tegra mobile, auto, medical Qualcomm Snapdragon mobile Renesas Electronics R-Mobile mobile R-Home consumer R-Car auto Fuzhou Rockchip Electronics RK Series consumer, mobile Samsung Exynos mobile Sigma Designs several consumer Spreadtrum Communications Mocor platform mobile SC series mobile ST NovaThor mobile Texas Instruments OMAP, Sitara consumer, industrial, auto Hercules auto FUNCTIONAL PLATFORMS Functional Platforms Product Markets Targeted AMD Fusion servers ARM Cortex mobile, servers, industrial, networking, consumer, servers, medical Mali graphics Atmel maXTouch T industrial, mobile Evatronix 8051 Platform controllers Imagination - MIPS POWERVR graphics, consumer, mobile, networking Infineon TriCore auto, industrial Intel SoC mobile Core PC Nvidia Tesla graphics GeForce graphics ZiiLABS ZMS mobile PROGRAMMABLE PLATFORMS Programmable Platforms Product Markets Targeted Altera Cyclone III industrial Cypress Semiconductor PSoC industrial Xilinx Zynq auto, industrial Autodesk - US Cad APPLICATIONS PLATFORMS Applications Platforms Product Markets Targeted ARM TrustZone security Cadence DPUs mobile, computing Synopsys DesignWare SoundWave Audio consumer Subsystem Autodesk - US Cad www.garysmithEDA.com [email protected] [email protected] © 2013 Gary Smith EDA. All Rights Reserved. CAE WALLCHART 2013 RTL SIGN-OFF TOOLS RT LEVEL RTL Functional Verification RTL Design & Entry Cadence Synopsys AXIOM Aldec Aldec Ansys - Apache - Sequence Avery ARM - Obsidian Software Design Debug Blue Pearl Software ATA Synopsys - Springsoft - ACCELERATION & EMULATION Maia Atrenta Novas Software nSys Cadence Aldec Hardware Rapid Prototype Real Intent Concept Egineering ASIC Analytic Cadence - Quickturn Synopsys Synopsys - Springsoft Dolphin Integration Atrenta Mentor Dini Group YogaTech EMA - Forte - Axiom - Protometer Synopsys - EVE - Tharas Aldec (Alatek) Zocalo Chronology/Cynapps Concept Gidel Bluespec Excellicon Jasper Star Bridge Systems Cadence Formal Verification Expressive Systems - (Vizef) Mentor ChipIt Cadence Fractal NextOp Software Dynalith Systems Synopsys Hantro Real Intent Auspy HiTech Design Jasper HDL Works Severity1 Mentor - SpeedGate Impulse Mentor Interra Systems Vennsa Synopsys - Synplicity Pittsburgh Simulation Axiom Design Automation Jasper Veritools Flexras Polaris Design (@HDL) Jeda Reflex Calypto Levetate HW/SW Co-Verification S2C OneSpin Mentor Carbon Design Prover Technology Real Intent Mentor Sigasi Adveda Formal Analysis SoftJin Agilent EEsof EDA Mentor - 0-In Source III Aldec Atrenta Stelar Tools Cadence Cadence - Verplex SynaptiCAD Dolphin Integration Averant (HDAC) Tanner EDA Endeavor Intertech RTL ANALYSIS TOOLS Real Intent Time-Rover Foresight Systems Assertive Design TransEDA Synopsys - CoWare Avery Timing & Signal- Translogic TNI-Valiosys - Arexsys EMI Design Axiom Design Automation Integrity Design VeriEZ Ansys - Ansoft - (@HDL) - (IBM) Synopsys Verific Pacific Numerix IBM Power Design Ansys - Ansoft - Veritools Applied Simulation Jasper Synopsys Pacific Numerix Technology - Contec Willamette Jeda Atrenta Cadence - CadMOS Fujitsu NEC Ansys - Apache Atrenta Lorentz Solutions OneSpin ASC CLK Mentor - Flowmerics BullDAST Fujitsu Synopsys National Instruments - Calypto Applied Simulation Veritable Electronics Workbench Library Technologies Technology - Contec Premier EDA Solutions Ltd Mentor Ausdia Zuken - Incases TNI-Valiosys-TransEDA Averant Veritools Avertec Incentia Design Systems Mentor RTL DESIGN TOOLS Real Intent Mixed-Language Simulation Verilog Simulation Synopsys Fintronic Mentor Synopsys Cadence Cadence ALDEC ALDEC Logic Synthesis DESIGN FOR TEST TOOLS Dolphin Integration TransEDA Synopsys Fintronic Axiom Design Automation Cadence - Get2Chip Tachyon (Pragmetic C Software) (@HDL) - (IBM) Aldec DFT Tools Comit Dolphin Integration ALS Design Mentor DeFacTo Technologies VHDL Simulation Mentor - Innoveda Altium (Protel) - Synopsys Flynn Systems ALDEC Tachyon (Pragmetic C Software) Accolade (Metamore) Cadence Incentia Design Systems Adveda Simucad - Silvaco ATA Atrenta Intellitech ALS Design Tau Simulation Derivation Systems Dolphin - Genesys Intusoft Cadence Winterlogic FTL Systems SynTest Technologies iROC Technologies Dolphin Integration Veripool Incentia Design Systems Acugen Macraigor Systems Green Mountain Real Intent Oasys Alpine IK Tech Pacific Design Simucad - Silvaco ASC Teseda (Deft) Impulse Accelerated Technologies Mixed-Signal Simulation SynApps Asset Intertech - TI Mentor - Ikos Mentor Tiberon DA Winterlogic Astek Zuken MyCAD Synopsys Tiempo ATEEDA Symphony EDA Cadence Verific/Softjin Synopsys - Zycad Agilent EEsof EDA ALS Design Ansys - Ansoft Dolphin Integration FTL Systems Simucad - Silvaco uSysintegral Zuken MISCELLANEOUS GATE LEVEL Design Libraries Enterprise & CIS Tools RF Design & Simulationv Analog Design Gate Level Simulation Synopsys Zuken Agilent EEsof EDA Cadence ALDEC Ansys Dassault - Synchronicity Ansys - Ansoft National Instruments - AWR ALS Design Cadence IC Manage National Instruments - AWR Agilent - Accelicon Ansys - Ansoft Caesium PTC - Ohio Design Automation Cadence Ago Cadence Cast Oridus Synopsys Anadigm Capilano Computing Hantro Hyperformance Ago AnalogRails Intusoft Intusoft ClioSoft Berkeley Design Anasift Technology Mental Automation Levetate Design Systems Agilent Computer Simulation Technology Asygn Mentor Library Technologies ALS (CST) AVP National Instruments - Mentor Aprisa Helic Berkeley Design Elect Workbench SynaptiCAD Arena Solutions Interactive Products Infiniscale Simucad - Silvaco Tanner EDA Cadence - Orcad Mentor - ZeLand Software Lynguent Sophia Systems Zuken - Redac Design and Reuse OEA International Mephisto Design Automation Synopsys - Springsoft - Novas Mentor Silicon IP Optotek MunEDA Tanner EDA Missing Link Tools Simucad - Silvaco Nostral Zuken-Redac - Veda ARM OpeniT Synopsys Sonnet Software (KCC Ltd.) Orora Design Technologies Partminer Analog Simulation Imagination - MIPs Webb Labs Silicon Frontline Posedge Cadence CEVA Simucad - Silvaco Precience Gate Level / Synopsys Cadence - Tensilica Solido Design Automation Sapient Systems Transistor Level Design Ansys - Ansoft Rambus SynCira Satin Ansift National Instruments Sonics Synopsys SiCAD Cadence - Chip Estimate - Tanner YDC Translogic Giga Scale Zeni EDA Systems ALS Design Univa Concept Engineering Cybereda Xuropa Silicon Frontline Dolphin Integration YDC Solido Design Automation Intusoft Synopsys - Sandwork Design Legend Design Technology Tanner Mentor Number One Systems Tanner EDA Zuken www.garysmithEDA.com [email protected] [email protected] [email protected] © 2013 Gary Smith EDA. All Rights Reserved. CAD/CAM WALLCHART 2013 PCB PCB Design MCM - Hybrid PCB SPICE PCB CAM Mentor Ansys - Ansoft Cadence - Orcad - Microsim Mentor Zuken - Racal-Redac National Instruments Frontline (Orbotech & Mentor) Schematic Capture Infinite Graphics Cadence YDC Zuken - Redac Cadence Zuken - Redac Altium (Protel) Agilent Infinite Graphics Autodesk YDC Fujitsu ALS Design YDC Mentor Intercept Ansys - Ansoft Altium Adiva Zuken Applied Simulation Intercept Technology Ansys - Ansoft - Compact Software Altium (Protel) - Inovative CAD National Instruments - Technology - Contec YDC Applied Simulation Ansys - Ansoft Elect. Workbench Autodesk - US Cad National Instruments Technology - Contec Asset - Intertech JEDAT (Seiko BluWave) CAD Design Software Agilent - Eagleware - Elanix Beige Bag Software BQR YDC Cadence AcAe-Software CAD-Migos CAD Design Software ALS Design Coventor Aldec Intusoft Cadence Altium (Protel) - Accel HDL Works ALS Design Mentor Douglas Electronics Capilano Mentor Autodesk - US CAD Penzar Downstream Technologies Concept Engineering Tanner EDA AutoTRAX Simucad - Silvaco Frontline Design Automation Dolphin Integration Xyalis CAD Design Software Spectrum Software GraphiCode Elgris Technologies CADint Tanner EDA Intercept Technology Intercept - ESA Design Package Design Cad-Migos MasterCAM Mental Automation Mentor ConnectEDA PTC - Ohio Design Automation MyCAD Ansys - Apache Douglas Electronics Step Tools Number One Systems Cadence EMA - Design Advance Technomatix - Unicam PCB Libraries E-System Design IMSI T-Tech Phase Three Logic McDAD EDA Unisoft Preception Software Mental Automation Wise Software Solutions Simucad - Silvaco Novarm Software Tanner EDA Number One Systems Wire & Harness Yokogama Digital Computer (YDC) Penzar Mentor Ziegler Informatics Polar Instruments Zuken Precience (Element 14 - CADSoft) Altium Premier EDA Solutions Cadence Sophia Systems Spectrum Software Ziegler Informatics CAD/CAM Power Analysis & Optimization Extractors Asyncronous Design Physical Libraries Ansys - Apache Design Solutions Synopsys - Avant! CLK - Synchronous ARM - Artisan Cadence Design Automation Synopsys Timing Analysis Cadence Mentor Elastix Ansys - Apache Mentor Mentor Synopsys Fulcrum Aragio Ansys Ansys
Recommended publications
  • Multiprocessing in Mobile Platforms: the Marketing and the Reality

    Multiprocessing in Mobile Platforms: the Marketing and the Reality

    Multiprocessing in Mobile Platforms: the Marketing and the Reality Marco Cornero, Andreas Anyuru ST-Ericsson Introduction During the last few years the mobile platforms industry has aggressively introduced multiprocessing in response to the ever increasing performance demanded by the market. Given the highly competitive nature of the mobile industry, multiprocessing has been adopted as a marketing tool. This highly visible, differentiating feature is used to pass the oversimplified message that more processors mean better platforms and performance. The reality is much more complex, because several interdependent factors are at play in determining the efficiency of multiprocessing platforms (such as the effective impact on software performance, chip frequency, area and power consumption) with the number of processors impacting only partially the overall balance, and with contrasting effects linked to the underlying silicon technologies. In this article we illustrate and compare the main technological options available in multiprocessing for mobile platforms, highlighting the synergies between multiprocessing and the disruptive FD-SOI silicon technology used in the upcoming ST-Ericsson products. We will show that compared to personal computers (PCs), the performance of single-processors in mobile platforms is still growing and how, from a software performance perspective, it is more profitable today to focus on faster dual-core rather than slower quad-core processors. We will also demonstrate how FD-SOI benefits dual-core processors even more by providing higher frequency for the same power consumption, together with a wider range of energy efficient operating modes. All of this results in a simpler, cheaper and more effective solution than competing homogeneous and heterogeneous quad-processors.
  • FAN53525 3.0A, 2.4Mhz, Digitally Programmable Tinybuck® Regulator

    FAN53525 3.0A, 2.4Mhz, Digitally Programmable Tinybuck® Regulator

    FAN53525 — 3.0 A, 2.4 MHz, June 2014 FAN53525 3.0A, 2.4MHz, Digitally Programmable TinyBuck® Regulator Digitally Programmable TinyBuck Digitally Features Description . Fixed-Frequency Operation: 2.4 MHz The FAN53525 is a step-down switching voltage regulator that delivers a digitally programmable output from an input . Best-in-Class Load Transient voltage supply of 2.5 V to 5.5 V. The output voltage is 2 . Continuous Output Current Capability: 3.0 A programmed through an I C interface capable of operating up to 3.4 MHz. 2.5 V to 5.5 V Input Voltage Range Using a proprietary architecture with synchronous . Digitally Programmable Output Voltage: rectification, the FAN53525 is capable of delivering 3.0 A - 0.600 V to 1.39375 V in 6.25 mV Steps continuous at over 80% efficiency, maintaining that efficiency at load currents as low as 10 mA. The regulator operates at Programmable Slew Rate for Voltage Transitions . a nominal fixed frequency of 2.4 MHz, which reduces the . I2C-Compatible Interface Up to 3.4 Mbps value of the external components to 330 nH for the output inductor and as low as 20 µF for the output capacitor. PFM Mode for High Efficiency in Light Load . Additional output capacitance can be added to improve . Quiescent Current in PFM Mode: 50 µA (Typical) regulation during load transients without affecting stability, allowing inductance up to 1.2 µH to be used. Input Under-Voltage Lockout (UVLO) ® At moderate and light loads, Pulse Frequency Modulation Regulator Thermal Shutdown and Overload Protection . (PFM) is used to operate in Power-Save Mode with a typical .
  • Fax86: an Open-Source FPGA-Accelerated X86 Full-System Emulator

    Fax86: an Open-Source FPGA-Accelerated X86 Full-System Emulator

    FAx86: An Open-Source FPGA-Accelerated x86 Full-System Emulator by Elias El Ferezli A thesis submitted in conformity with the requirements for the degree of Master of Applied Science (M.A.Sc.) Graduate Department of Electrical and Computer Engineering University of Toronto Copyright c 2011 by Elias El Ferezli Abstract FAx86: An Open-Source FPGA-Accelerated x86 Full-System Emulator Elias El Ferezli Master of Applied Science (M.A.Sc.) Graduate Department of Electrical and Computer Engineering University of Toronto 2011 This thesis presents FAx86, a hardware/software full-system emulator of commodity computer systems using x86 processors. FAx86 is based upon the open-source IA-32 full-system simulator Bochs and is implemented over a single Virtex-5 FPGA. Our first prototype uses an embedded PowerPC to run the software portion of Bochs and off- loads the instruction decoding function to a low-cost hardware decoder since instruction decode was measured to be the most time consuming part of the software-only emulation. Instruction decoding for x86 architectures is non-trivial due to their variable length and instruction encoding format. The decoder requires only 3% of the total LUTs and 5% of the BRAMs of the FPGA's resources making the design feasible to replicate for many- core emulator implementations. FAx86 prototype boots Linux Debian version 2.6 and runs SPEC CPU 2006 benchmarks. FAx86 improves simulation performance over the default Bochs by 5 to 9% depending on the workload. ii Acknowledgements I would like to begin by thanking my supervisor, Professor Andreas Moshovos, for his patient guidance and continuous support throughout this work.
  • Global Network Investment Competition Fudan University Supreme Pole ‐ Allwinner Technology

    Global Network Investment Competition Fudan University Supreme Pole ‐ Allwinner Technology

    Global Network Investment Competition Fudan University Supreme Pole ‐ Allwinner Technology Date: 31.10.2017 Fan Jiang Jianbin Gu Qianrong Lu Shijie Dong Zheng Xu Chunhua Xu Allwinner Technology ‐‐ Sail Again We initiate coverage on Allwinner Technology with a strong BUY rating, target price is derived by DCF at CNY ¥ 35.91 , indicating Price CNY ¥ 27.60 30.1% upside potential. Price Target CNY ¥ 35.91 Upside Potential 30.1% Target Period 1 Year We recommend based on: 52 week Low CNY ¥ 23.4 Broad prospects of the AI. 52 week High CNY ¥ 54.02 Supporting of the industry policy. Average Volume CNY ¥ 190.28 M Allwinner has finished its transition. Market Cap CNY ¥ 96.08 B The rise of the various new P/E 64 products will put the margins back Price Performance in the black. 60 The current valuation, 64.x P/E, is 50 lower than its competitor such as 40 Ingenic which is trading at more 30 than 100 and Nationz which is 20 trading at 76.x P/E. 10 0 Overview for Allwinner Allwinner Technology, founded in 2007, is a leading fabless design company dedicated to smart application processor SoCs and smart analog ICs. Its product line includes multi‐core application processors for smart devices and smart power management ICs used worldwide. These two categories of products are applied to various types of intelligent terminals into 3 major business lines: Consumer Electronics: Robot, Smart Hardware Open Platform, Tablets, Video Theater Device, E‐Reader, Video Story Machine, Action Camera, VR Home Entertainment: OTT Box, Karaoke Machine, IPC monitoring Connected Automotive Applications: Dash Cams, Smart Rear‐view Mirror, In Car Entertainment THE PROSPECT OF AI AI(Artificial Intelligence) has a wider range of global concern and is entering its third golden period of development.
  • Ramp: Research Accelerator for Multiple Processors

    Ramp: Research Accelerator for Multiple Processors

    ..................................................................................................................................................................................................................................................... RAMP: RESEARCH ACCELERATOR FOR MULTIPLE PROCESSORS ..................................................................................................................................................................................................................................................... THE RAMP PROJECT’S GOAL IS TO ENABLE THE INTENSIVE, MULTIDISCIPLINARY INNOVATION John Wawrzynek THAT THE COMPUTING INDUSTRY WILL NEED TO TACKLE THE PROBLEMS OF PARALLEL David Patterson PROCESSING. RAMP ITSELF IS AN OPEN-SOURCE, COMMUNITY-DEVELOPED, FPGA-BASED University of California, EMULATOR OF PARALLEL ARCHITECTURES. ITS DESIGN FRAMEWORK LETS A LARGE, Berkeley COLLABORATIVE COMMUNITY DEVELOP AND CONTRIBUTE REUSABLE, COMPOSABLE DESIGN Mark Oskin MODULES. THREE COMPLETE DESIGNS—FOR TRANSACTIONAL MEMORY, DISTRIBUTED University of Washington SYSTEMS, AND DISTRIBUTED-SHARED MEMORY—DEMONSTRATE THE PLATFORM’S POTENTIAL. Shih-Lien Lu ...... In 2005, the computer hardware N Prototyping a new architecture in Intel industry took a historic change of direction: hardware takes approximately four The major microprocessor companies all an- years and many millions of dollars, nounced that their future products would even at only research quality. Christoforos Kozyrakis be single-chip multiprocessors, and that N Software
  • Computer Architectures an Overview

    Computer Architectures an Overview

    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
  • A13 Datasheet V1.01

    A13 Datasheet V1.01

    Allwinner Technology CO., Ltd. A13 A13 Datasheet V1.12 2012.3.29 A13 Datasheet v1.12 Copyright © 2011-2012 Allwinner Technology. All Rights Reserved. 2012-03-29 Allwinner Technology CO., Ltd. A13 Revision History Version Date Section/ Page Changes V1.00 2011.12.9 Initial version GPIOE[0]/[1]/[2] and GPIOG[0]/[1]/[2] V1.10 2011.12.30 Pin Description are changed for INPUT only. V1.11 2012.1.10 Pin Dimension Pin Dimension V1.12 2012.3.29 Audio Codec Revise some description A13 Datasheet v1.12 Copyright © 2011-2012 Allwinner Technology. All Rights Reserved. 1 2012-03-29 Allwinner Technology CO., Ltd. A13 Table of Contents Revision History ...................................................................................................................... 1 1. Introduction ..................................................................................................................... 5 2. Feature ............................................................................................................................. 5 3. Functional Block Diagram ................................................................................................ 9 4. Pin Assignment ............................................................................................................... 10 4.1. Pin Map ................................................................................................................... 10 4.2. Pin Dimension ........................................................................................................... 11

  • Android Benchmarks - Geekbench Browser 11/05/2015 6:27 Pm Geekbench Browser Geekbench 3 Geekbench 2 Benchmark Charts Search Geekbench 3 Results Sign up Log In

    Android Benchmarks - Geekbench Browser 11/05/2015 6:27 pm Geekbench Browser Geekbench 3 Geekbench 2 Benchmark Charts Search Geekbench 3 Results Sign Up Log In COMPARE Android Benchmarks Processor Benchmarks Mac Benchmarks iOS Benchmarks Welcome to Primate Labs' Android benchmark chart. The data on this chart is gathered from user-submitted Geekbench 3 results from the Geekbench Browser. Android Benchmarks Geekbench 3 scores are calibrated against a baseline score of 2500 (which is the score of an Intel Core i5-2520M @ 2.50 GHz). Higher scores are better, with double the score indicating double the performance. SHARE If you're curious how your computer compares, you can download Geekbench 3 and run it on your computer to find out your score. Tweet 0 This chart was last updated 30 minutes ago. 139 Like 891 Single Core Multi-Core Device Score HTC Nexus 9 1890 NVIDIA Tegra K1 Denver 2499 MHz (2 cores) Samsung Galaxy S6 edge 1306 Samsung Exynos 7420 1500 MHz (8 cores) Samsung Galaxy S6 1241 Samsung Exynos 7420 1500 MHz (8 cores) Samsung Galaxy Note 4 1164 Samsung Exynos 5433 1300 MHz (8 cores) NVIDIA SHIELD Tablet 1087 NVIDIA Tegra K1 2218 MHz (4 cores) Motorola DROID Turbo 1052 Qualcomm APQ8084 Snapdragon 805 2649 MHz (4 cores) Samsung Galaxy S5 Plus 1027 Qualcomm APQ8084 Snapdragon 805 2457 MHz (4 cores) Motorola Nexus 6 1016 Qualcomm APQ8084 Snapdragon 805 2649 MHz (4 cores) Samsung Galaxy Note 4 986 Qualcomm APQ8084 Snapdragon 805 2457 MHz (4 cores) Motorola Moto X (2014) 970 Qualcomm MSM8974AC Snapdragon 801 2457 MHz (4 cores) HTC One (M8x)
  • Taiwan Semiconductor Manufacturing

    Taiwan Semiconductor Manufacturing

    08 January 2015 Asia Pacific/Taiwan Equity Research Semiconductor Devices Taiwan Semiconductor Manufacturing (2330.TW / 2330 TT) Rating (from Outperform) NEUTRAL Price (08 Jan 15, NT$) 138.00 DOWNGRADE RATING Target price (NT$) 145.00¹ Upside/downside (%) 5.1 Mkt cap (NT$ bn) 3.58 (US$ 111,910 mn) Competition heats up in 2015 Enterprise value (NT$ mn) 3,463,889 ■ Competitive landscape a key focus for 2015. We downgrade TSMC to Number of shares (mn) 25,929.87 Free float (%) 87.3 NEUTRAL from Outperform with TP unchanged at NT$145, toning down our 52-week price range 141.5–100.5 positive view of the past five years. We see increasing customer ADTO - 6M (US$ mn) 148.6 concentration risks where further share gains are limited and may slip, *Stock ratings are relative to the coverage universe in each analyst's or each team's respective sector. moderating growth from mobile; rising competitors finally lifting their yields; ¹Target price is for 12 months. and valuation back in line with Taiwan tech and its historical average due to Research Analysts slowing YoY/sequential momentum after the likely strong 4Q14 results report. Randy Abrams, CFA ■ Customers more concentrated but now able to diversify. Qualcomm, 886 2 2715 6366 [email protected] Apple and Mediatek have supplied half of TSMC's growth in the past four Nickie Yue years and to boost TSMC’s growth 700 bp to 16%. Further share is capped 886 2 2715 6364 or might even slip as Apple brings Samsung/GF back in for iPhone, [email protected] Qualcomm relies more on Samsung/GF/UMC/SMIC, and further Mediatek gains are capped with TSMC's share up from 20% to 70% since 2007.
  • (12) Patent Application Publication (10) Pub. No.: US 2015/0254416 A1 Shih (43) Pub

    (12) Patent Application Publication (10) Pub. No.: US 2015/0254416 A1 Shih (43) Pub

    US 20150254416A1 (19) United States (12) Patent Application Publication (10) Pub. No.: US 2015/0254416 A1 Shih (43) Pub. Date: Sep. 10, 2015 (54) METHOD AND SYSTEM FOR PROVIDING (52) U.S. Cl. MEDICAL ADVICE CPC .......... G06F 19/3425 (2013.01); G06F 19/322 (2013.01) (71) Applicant: ClickMedix, Gaithersburg, MD (US) (72) Inventor: Ting-Chih Shih, Rockville, MD (US) (57) ABSTRACT (73) Assignee: CLICKMEDIX, Gaithersburg, MD A method and system for providing medical services wherein (US) a server establishes a wireless connection with a mobile device or computer of a user. The mobile device or computer (21) Appl. No.: 14/199,559 has already been provided with an application for the entry of (22) Filed: Mar. 6, 2014 user information. The server receives encrypted user infor mation from the mobile device or computer, decrypts the user Publication Classification information, and forwards the user information to experts selected on the basis of the user information. The server (51) Int. Cl. collects responses from the experts, and provides expert G06F 9/00 (2006.01) advice to the user of the mobile device or computer. NTERNET SERVICE SERVER PROVIDER 25 Patent Application Publication Sep. 10, 2015 Sheet 1 of 10 US 2015/0254416 A1 S. OO L gy2 O ch : 2 > S 2 v 9 --- ---m-m- Patent Application Publication Sep. 10, 2015 Sheet 2 of 10 US 2015/0254416 A1 ZI IZ| -----———————? |------ OT Patent Application Publication Sep. 10, 2015 Sheet 3 of 10 US 2015/0254416 A1 dXB:LHB Patent Application Publication Sep. 10, 2015 Sheet 4 of 10 US 2015/0254416 A1 ——— ?II || | | || | |NOIIVWHOHNI Å ||GO?I Nodisva HITV3HLNBILVd ______.ISOH______ ~~~~}dno89v10BTES!| S183dXBHO| |~\~~~~|||| †7·314 || | | || | ZO? A | } }} | }{ | l Patent Application Publication US 2015/0254416 A1 ?euauss)| Patent Application Publication Sep.
  • Allwinner V3 Is a High Performance FHD Camera Application Solution That Features

    Allwinner V3 Is a High Performance FHD Camera Application Solution That Features

    Smart Dual-Channel FHD Camera Solution Allwinner V3 is a high performance FHD camera application solution that features: Robust Video Engine, H.264 1080p@60fps or 2-CH 1080p@30fps encoding Allwinner V3 comes with a high-performance and low bit-rate video engine that is capable of single-channel H.264 1080p@60fps encoding, or dual-channel 1080p@30fps encoding, or front & rear 1080p@30fps encoding. It is also the world's first camera solution that supports recompilation of FHD MJPEG into H.264 format. An advanced ISP is integrated to provide higher image quality. ARM Cortex-A7 CPU, Advanced ADAS Algorithm Allwinner V3 packs an ARM Cortex-A7 core that runs up to 1.2GHz to deliver higher computing capability, enabling support for advanced ADAS (Advance Driver Assistant System) algorithm to provide more secure driving experience, including FCWS (Forward Collision Warning System), LDWS (Lane Departure Warning System) ,etc. WiFi or 3G/4G Supported, Android/iOS APKs WiFi or 3G/4G function can be available in V3 to enable interaction with mobile phones after installing corresponding Android/iOS applications. Linux OS or Allwinner's Camdroid OS Allwinner V3 runs on the Linux operating system or Allwinner's Camdroid OS, an Android-lite operation system that capable of running on Nor Flash. Lower Power Consumption Allwinner V3 runs is highly power efficient due to its leading fabrication process and optimized processor architecture design. High System Integration Allwinner V3 integrates a wide range of connectivity and interfaces, including MIPI & parallel CSI controllers, RGB/ LVDS LCD controller, audio codec, EMAC + PHY, etc.
  • Exploiting Broadcast Information in Cellular Networks

    Exploiting Broadcast Information in Cellular Networks

    Let Me Answer That For You: Exploiting Broadcast Information in Cellular Networks Nico Golde, Kévin Redon, and Jean-Pierre Seifert, Technische Universität Berlin and Deutsche Telekom Innovation Laboratories This paper is included in the Proceedings of the 22nd USENIX Security Symposium. August 14–16, 2013 • Washington, D.C., USA ISBN 978-1-931971-03-4 Open access to the Proceedings of the 22nd USENIX Security Symposium is sponsored by USENIX Let Me Answer That For You: Exploiting Broadcast Information in Cellular Networks Nico Golde, K´evin Redon, Jean-Pierre Seifert Technische Universitat¨ Berlin and Deutsche Telekom Innovation Laboratories {nico, kredon, jpseifert}@sec.t-labs.tu-berlin.de Abstract comBB [20, 25, 45]. These open source projects consti- tute the long sought and yet publicly available counter- Mobile telecommunication has become an important part parts of the previously closed radio stacks. Although all of our daily lives. Yet, industry standards such as GSM of them are still constrained to 2G network handling, re- often exclude scenarios with active attackers. Devices cent research provides open source software to tamper participating in communication are seen as trusted and with certain 3G base stations [24]. Needless to say that non-malicious. By implementing our own baseband those projects initiated a whole new class of so far uncon- firmware based on OsmocomBB, we violate this trust sidered and practical security investigations within the and are able to evaluate the impact of a rogue device with cellular communication research, [28, 30, 34]. regard to the usage of broadcast information. Through our analysis we show two new attacks based on the pag- Despite the recent roll-out of 4G networks, GSM re- ing procedure used in cellular networks.