Evaluation of CPU Architecture by Simulation Technologies And
Total Page:16
File Type:pdf, Size:1020Kb
Load more
Recommended publications
-
Fax86: an Open-Source FPGA-Accelerated X86 Full-System Emulator
FAx86: An Open-Source FPGA-Accelerated x86 Full-System Emulator by Elias El Ferezli A thesis submitted in conformity with the requirements for the degree of Master of Applied Science (M.A.Sc.) Graduate Department of Electrical and Computer Engineering University of Toronto Copyright c 2011 by Elias El Ferezli Abstract FAx86: An Open-Source FPGA-Accelerated x86 Full-System Emulator Elias El Ferezli Master of Applied Science (M.A.Sc.) Graduate Department of Electrical and Computer Engineering University of Toronto 2011 This thesis presents FAx86, a hardware/software full-system emulator of commodity computer systems using x86 processors. FAx86 is based upon the open-source IA-32 full-system simulator Bochs and is implemented over a single Virtex-5 FPGA. Our first prototype uses an embedded PowerPC to run the software portion of Bochs and off- loads the instruction decoding function to a low-cost hardware decoder since instruction decode was measured to be the most time consuming part of the software-only emulation. Instruction decoding for x86 architectures is non-trivial due to their variable length and instruction encoding format. The decoder requires only 3% of the total LUTs and 5% of the BRAMs of the FPGA's resources making the design feasible to replicate for many- core emulator implementations. FAx86 prototype boots Linux Debian version 2.6 and runs SPEC CPU 2006 benchmarks. FAx86 improves simulation performance over the default Bochs by 5 to 9% depending on the workload. ii Acknowledgements I would like to begin by thanking my supervisor, Professor Andreas Moshovos, for his patient guidance and continuous support throughout this work. -
The Interactive Performance of SLIM: a Stateless, Thin-Client Architecture ✽ ✽ ✝ Brian K
17th ACM Symposium on Operating Systems Principles (SOSP’99) Published as Operating Systems Review, 34(5):32–47, December 1999 The interactive performance of SLIM: a stateless, thin-client architecture ✽ ✽ ✝ Brian K. Schmidt , Monica S. Lam , J. Duane Northcutt ✽ Computer Science Department, Stanford University {bks, lam}@cs.stanford.edu ✝ Sun Microsystems Laboratories [email protected] Abstract 1 Introduction Taking the concept of thin clients to the limit, this paper Since the mid 1980’s, the computing environments of proposes that desktop machines should just be simple, many institutions have moved from large mainframe, stateless I/O devices (display, keyboard, mouse, etc.) that time-sharing systems to distributed networks of desktop access a shared pool of computational resources over a machines. This trend was motivated by the need to provide dedicated interconnection fabric — much in the same way everyone with a bit-mapped display, and it was made as a building’s telephone services are accessed by a possible by the widespread availability of collection of handset devices. The stateless desktop design high-performance workstations. However, the desktop provides a useful mobility model in which users can computing model is not without its problems, many of transparently resume their work on any desktop console. which were raised by the original UNIX designers[14]: This paper examines the fundamental premise in this “Because each workstation has private data, each system design that modern, off-the-shelf interconnection must be administered separately; maintenance is technology can support the quality-of-service required by difficult to centralize. The machines are replaced today’s graphical and multimedia applications. -
Intermediate X86 Part 2
Intermediate x86 Part 2 Xeno Kovah – 2010 xkovah at gmail All materials are licensed under a Creative Commons “Share Alike” license. • http://creativecommons.org/licenses/by-sa/3.0/ 2 Paging • Previously we discussed how segmentation translates a logical address (segment selector + offset) into a 32 bit linear address. • When paging is disabled, linear addresses map 1:1 to physical addresses. • When paging is enabled, a linear address must be translated to determine the physical address it corresponds to. • It’s called “paging” because physical memory is divided into fixed size chunks called pages. • The analogy is to books in a library. When you need to find some information first you go to the library where you look up the relevant book, then you select the book and look up a specific page, from there you maybe look for a specific specific sentence …or “word”? ;) • The internets ruined the analogy! 3 Notes and Terminology • All of the figures or references to the manual in this section refer to the Nov 2008 manual (available in the class materials). This is because I think the manuals <= 2008 organized and presented much clearer than >= 2009 manuals. • When I refer to a “frame” it means “a page- sized chunk of physical memory” • When paging is enabled, a “linear address” is the same thing as a “virtual memory ” “ ” address or virtual address 4 The terrifying truth revealed! And now you knowAHHHHHHHH!!!…the rest of the story.(Nah, Good it’s not so bad day. :)) 5 Virtual Memory • When paging is enabled, the 32 bit linear address space can be mapped to a physical address space less than 32 bits. -
Sun Ultratm 2 Workstation Just the Facts
Sun UltraTM 2 Workstation Just the Facts Copyrights 1999 Sun Microsystems, Inc. All Rights Reserved. Sun, Sun Microsystems, the Sun Logo, Ultra, SunFastEthernet, Sun Enterprise, TurboGX, TurboGXplus, Solaris, VIS, SunATM, SunCD, XIL, XGL, Java, Java 3D, JDK, S24, OpenWindows, Sun StorEdge, SunISDN, SunSwift, SunTRI/S, SunHSI/S, SunFastEthernet, SunFDDI, SunPC, NFS, SunVideo, SunButtons SunDials, UltraServer, IPX, IPC, SLC, ELC, Sun-3, Sun386i, SunSpectrum, SunSpectrum Platinum, SunSpectrum Gold, SunSpectrum Silver, SunSpectrum Bronze, SunVIP, SunSolve, and SunSolve EarlyNotifier are trademarks, registered trademarks, or service marks of Sun Microsystems, Inc. in the United States and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. OpenGL is a registered trademark of Silicon Graphics, Inc. UNIX is a registered trademark in the United States and other countries, exclusively licensed through X/Open Company, Ltd. Display PostScript and PostScript are trademarks of Adobe Systems, Incorporated. DLT is claimed as a trademark of Quantum Corporation in the United States and other countries. Just the Facts May 1999 Sun Ultra 2 Workstation Figure 1. The Sun UltraTM 2 workstation Sun Ultra 2 Workstation Scalable Computing Power for the Desktop Sun UltraTM 2 workstations are designed for the technical users who require high performance and multiprocessing (MP) capability. The Sun UltraTM 2 desktop series combines the power of multiprocessing with high-bandwidth networking, high-performance graphics, and exceptional application performance in a compact desktop package. Users of MP-ready and multithreaded applications will benefit greatly from the performance of the Sun Ultra 2 dual-processor capability. -
Multiprocessing Contents
Multiprocessing Contents 1 Multiprocessing 1 1.1 Pre-history .............................................. 1 1.2 Key topics ............................................... 1 1.2.1 Processor symmetry ...................................... 1 1.2.2 Instruction and data streams ................................. 1 1.2.3 Processor coupling ...................................... 2 1.2.4 Multiprocessor Communication Architecture ......................... 2 1.3 Flynn’s taxonomy ........................................... 2 1.3.1 SISD multiprocessing ..................................... 2 1.3.2 SIMD multiprocessing .................................... 2 1.3.3 MISD multiprocessing .................................... 3 1.3.4 MIMD multiprocessing .................................... 3 1.4 See also ................................................ 3 1.5 References ............................................... 3 2 Computer multitasking 5 2.1 Multiprogramming .......................................... 5 2.2 Cooperative multitasking ....................................... 6 2.3 Preemptive multitasking ....................................... 6 2.4 Real time ............................................... 7 2.5 Multithreading ............................................ 7 2.6 Memory protection .......................................... 7 2.7 Memory swapping .......................................... 7 2.8 Programming ............................................. 7 2.9 See also ................................................ 8 2.10 References ............................................. -
Sun Enterprisetm 220R Server Just the Facts
Sun EnterpriseTM 220R Server Just the Facts Copyrights 1998, 1999 Sun Microsystems, Inc. All Rights Reserved. Sun, Sun Microsystems, the Sun logo, Sun Enterprise, Ultra, UltraComputing, Sun Enterprise Ultra, Starfire, Solaris, Solstice, Sun Enterprise SyMON, Sun WebServer, IPX, NFS, VIS, Sun StorEdge, OpenBoot, Solaris Web Start Wizards, Solstice AdminSuite, Solaris Management Console, Sun Enterprise Authentication Mechanism, SunScreen, Solstice DiskSuite, Solstice Backup, Sun StorEdge LibMON, Solstice Site Manager, Solstice Domain Manager, Solaris Resource Manager, ShowMe How, Solstice Enterprise Manager, Solstice Enterprise Agents, ShowMe TV, Java, SunLink, Solstice SunNet Manager, SunScreen EFS, Solstice Cooperative Consoles, Solstice TMNscript, Solstice TMNscript Runtime, SunCD, SunVTS, SunSpectrum, SunSwift, SunFastEthernet, SunFDDI, SunTRI/P, SunHSI/P, PGX, PGX32, SunATM, SunSpectrum Platinum, SunSpectrum Gold, SunSpectrum Silver, SunSpectrum Bronze, SunStart, SunVIP, SunSolve, and SunSolve EarlyNotifier are trademarks, registered trademarks, or service marks of Sun Microsystems, Inc. in the United States and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. UNIX is a registered trademark in the United States and in other countries, exclusively licensed through X/Open Company, Ltd. Just the Facts November 1999 Positioning Figure 1. Sun EnterpriseTM 220R System Exceptional Processing Power in a Compact Footprint The Sun EnterpriseTM 220R server is the latest member of Sun’s powerful line of servers for enterprise network computing based on the UltraSPARCTM processor technology. This next-generation workgroup server brings multiprocessing power, UltraSCSI disks, and the industry-standard peripheral component interconnect (PCI) I/O bus to a highly modular, rack-optimized 4RU (rack unit) design. -
X86 Memory Protection and Translation
2/5/20 COMP 790: OS Implementation COMP 790: OS Implementation Logical Diagram Binary Memory x86 Memory Protection and Threads Formats Allocators Translation User System Calls Kernel Don Porter RCU File System Networking Sync Memory Device CPU Today’s Management Drivers Scheduler Lecture Hardware Interrupts Disk Net Consistency 1 Today’s Lecture: Focus on Hardware ABI 2 1 2 COMP 790: OS Implementation COMP 790: OS Implementation Lecture Goal Undergrad Review • Understand the hardware tools available on a • What is: modern x86 processor for manipulating and – Virtual memory? protecting memory – Segmentation? • Lab 2: You will program this hardware – Paging? • Apologies: Material can be a bit dry, but important – Plus, slides will be good reference • But, cool tech tricks: – How does thread-local storage (TLS) work? – An actual (and tough) Microsoft interview question 3 4 3 4 COMP 790: OS Implementation COMP 790: OS Implementation Memory Mapping Two System Goals 1) Provide an abstraction of contiguous, isolated virtual Process 1 Process 2 memory to a program Virtual Memory Virtual Memory 2) Prevent illegal operations // Program expects (*x) – Prevent access to other application or OS memory 0x1000 Only one physical 0x1000 address 0x1000!! // to always be at – Detect failures early (e.g., segfault on address 0) // address 0x1000 – More recently, prevent exploits that try to execute int *x = 0x1000; program data 0x1000 Physical Memory 5 6 5 6 1 2/5/20 COMP 790: OS Implementation COMP 790: OS Implementation Outline x86 Processor Modes • x86 -
Ultrasparctm II Microprocessor
UltraSPARCTM II Microprocessor High-Performance, Highly-Scalable, Multiprocess- The UltraSPARC II processor microarchitecture is designed ing, 64-bit SPARC™ V9 RISC Microprocessor to provide up to 4-way glueless multiprocessing support and supports up to 64-way systems. The processor sup- ports multiple L2 cache speeds and sizes to enable high- performance multiprocessing systems. Balanced overall system performance requires optimal performance along three critical levels: memory band- width, media processing, and raw compute performance. A highly-scalable, high-performance system interconnect ensures a bottleneck-free computing environment result- ing in high memory bandwidth. VIS™ (Visual Instruction Set) multimedia extensions boost the performance of graphics-intensive multimedia applications, and thus reduce overall system costs by eliminating the need for a special-purpose media processor. And the UltraSPARC II delivers superior raw compute performance by using the Placeholder for illustration or photo most innovative RISC microprocessor architecture and state-of-the-art process technology. The UltraSPARC II processor not only helps the system designer by implementing industry-standard testing and instrumentation interfaces, it also uses Error Checking & Correction (ECC) and parity to increase system reliability. With high performance, high scalability, and high reliabil- ity, the UltraSPARC II is the processor of choice for today’s workstations and servers. FEATURES • Full 64-bit implementation of SPARC V9 architecture • 100% binary compatibility with previous versions of SPARC systems The state-of-the-art UltraSPARC™ II processor is the second • Built-in MP support (glueless 4-way and up to 64-way) generation in the UltraSPARC s-series microprocessor fam- • High-performance UPA system interconnect ily. -
S U N U Ltra™ 60 Workstation
S UN ULTRA™ 60 WORKSTATION THE NEXT LEVEL IN MULTIPROCESSING WORKSTATIONS. .................... .................... It’s the perfect combination of raw multiprocessing performance and sophisticated next-generation technologies—a high-powered, flexible system that’s ready for today’s compute-intensive challenges. And for whatever’s next. The Sun Ultra™ 60 workstation accommodates two powerful, 450-MHz UltraSPARC™-II modules, with horsepower to drive demanding applications. And the combination of fast UltraSCSI disk, 66-MHz PCI technology, and the 120-MHz, 1.9 GB/sec., crossbar-switch UPA interconnect delivers exceptionally fast processing and throughput. • Graphics are no less advanced, with Creator3D and Elite3D able to handle applications like geotechnical, simulation, seismic analysis, and medical imaging. Plus, dual-head and 24-inch monitor support means more visible display area—and more productivity. The Sun Ultra 60 workstation. HIGHLIGHTS •Up to two 450-MHz or 360-MHz • Modular design and 120-MHz,1.9 GB/sec. • Two Creator3D or Elite3D m3 graphics • Supports previous-generation memory, UltraSPARC-II modules and 4-MB cache UPA interconnect allows easy upgrade cards, or one Elite3D m6 card, with disk, and graphics cards, protecting for exceptional application performance. to next-generation processors, graphics one Creator3D 0r one Elite m3 provide hardware investments. • 100% binary compatible with entire cards, and peripherals. outstanding performance for • Dual-bus 66-MHz PCI technology, product line—which protects your • Rigorous testing ensures a robust, well- demanding graphics applications. 10-/100-BaseT Ethernet, and UltraSCSI investment. engineered system and years of uptime. disk provide the industry’s best I/O and networking capabilities. .................... SUN ULTRA 60 SPECIFICATIONS PROCESSOR OPTIONS MONITOR OPTIONS 24-in. -
Operating Systems & Virtualisation Security Knowledge Area
Operating Systems & Virtualisation Security Knowledge Area Issue 1.0 Herbert Bos Vrije Universiteit Amsterdam EDITOR Andrew Martin Oxford University REVIEWERS Chris Dalton Hewlett Packard David Lie University of Toronto Gernot Heiser University of New South Wales Mathias Payer École Polytechnique Fédérale de Lausanne The Cyber Security Body Of Knowledge www.cybok.org COPYRIGHT © Crown Copyright, The National Cyber Security Centre 2019. This information is licensed under the Open Government Licence v3.0. To view this licence, visit: http://www.nationalarchives.gov.uk/doc/open-government-licence/ When you use this information under the Open Government Licence, you should include the following attribution: CyBOK © Crown Copyright, The National Cyber Security Centre 2018, li- censed under the Open Government Licence: http://www.nationalarchives.gov.uk/doc/open- government-licence/. The CyBOK project would like to understand how the CyBOK is being used and its uptake. The project would like organisations using, or intending to use, CyBOK for the purposes of education, training, course development, professional development etc. to contact it at con- [email protected] to let the project know how they are using CyBOK. Issue 1.0 is a stable public release of the Operating Systems & Virtualisation Security Knowl- edge Area. However, it should be noted that a fully-collated CyBOK document which includes all of the Knowledge Areas is anticipated to be released by the end of July 2019. This will likely include updated page layout and formatting of the individual Knowledge Areas KA Operating Systems & Virtualisation Security j October 2019 Page 1 The Cyber Security Body Of Knowledge www.cybok.org INTRODUCTION In this Knowledge Area, we introduce the principles, primitives and practices for ensuring se- curity at the operating system and hypervisor levels. -
Sun Blade 1000 and 2000 Workstations
Sun BladeTM 1000 and 2000 Workstations Just the Facts Copyrights 2002 Sun Microsystems, Inc. All Rights Reserved. Sun, Sun Microsystems, the Sun logo, Sun Blade, PGX, Solaris, Ultra, Sun Enterprise, Starfire, SunPCi, Forte, VIS, XGL, XIL, Java, Java 3D, SunVideo, SunVideo Plus, Sun StorEdge, SunMicrophone, SunVTS, Solstice, Solstice AdminTools, Solstice Enterprise Agents, ShowMe, ShowMe How, ShowMe TV, Sun Workstation, StarOffice, iPlanet, Solaris Resource Manager, Java 2D, OpenWindows, SunCD, Sun Quad FastEthernet, SunFDDI, SunATM, SunCamera, SunForum, PGX32, SunSpectrum, SunSpectrum Platinum, SunSpectrum Gold, SunSpectrum Silver, SunSpectrum Bronze, SunSolve, SunSolve EarlyNotifier, and SunClient are trademarks, registered trademarks, or service marks of Sun Microsystems, Inc. in the United States and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. UNIX is a registered trademark in the United States and in other countries, exclusively licensed through X/Open Company, Ltd. FireWire is a registered trademark of Apple Computer, Inc., used under license. OpenGL is a trademark of Silicon Graphics, Inc., which may be registered in certain jurisdictions. Netscape is a trademark of Netscape Communications Corporation. PostScript and Display PostScript are trademarks of Adobe Systems, Inc., which may be registered in -
Chapter 3 Protected-Mode Memory Management
CHAPTER 3 PROTECTED-MODE MEMORY MANAGEMENT This chapter describes the Intel 64 and IA-32 architecture’s protected-mode memory management facilities, including the physical memory requirements, segmentation mechanism, and paging mechanism. See also: Chapter 5, “Protection” (for a description of the processor’s protection mechanism) and Chapter 20, “8086 Emulation” (for a description of memory addressing protection in real-address and virtual-8086 modes). 3.1 MEMORY MANAGEMENT OVERVIEW The memory management facilities of the IA-32 architecture are divided into two parts: segmentation and paging. Segmentation provides a mechanism of isolating individual code, data, and stack modules so that multiple programs (or tasks) can run on the same processor without interfering with one another. Paging provides a mech- anism for implementing a conventional demand-paged, virtual-memory system where sections of a program’s execution environment are mapped into physical memory as needed. Paging can also be used to provide isolation between multiple tasks. When operating in protected mode, some form of segmentation must be used. There is no mode bit to disable segmentation. The use of paging, however, is optional. These two mechanisms (segmentation and paging) can be configured to support simple single-program (or single- task) systems, multitasking systems, or multiple-processor systems that used shared memory. As shown in Figure 3-1, segmentation provides a mechanism for dividing the processor’s addressable memory space (called the linear address space) into smaller protected address spaces called segments. Segments can be used to hold the code, data, and stack for a program or to hold system data structures (such as a TSS or LDT).