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Xilinx DS577 XPS 16550 UART (V3.00A), Data Sheet

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Xilinx DS577 XPS 16550 UART (V3.00A), Data Sheet 0 XPS 16550 UART (v3.00a) DS577 September 16, 2009 00 Product Specification Introduction LogiCORE™ Facts This document provides the specification for the XPS Core Specifics 16550 UART (Universal Asynchronous Virtex-4®, Virtex-4Q, Virtex-4QV, Receiver/Transmitter) Intellectual Property (IP). Virtex-5, Virtex-5FX, Virtex-6, Virtex-6CX, Spartan-3 AN, The XPS 16550 UART described in this document has Spartan®-3E, Automotive Supported Device Spartan-3E, Spartan-3, Automotive been incorporating features described in National Family Spartan-3, Spartan-3A, Automotive . Semiconductor PC16550D UART with FIFOs data sheet Spartan-3A, Spartan-3A DSP, The National Semiconductor PC16550D data sheet is Automotive Spartan-3A DSP, Spartan-6 referenced throughout this document and should be used as the authoritative specification. Differences Version of Core xps_uart16550 v3.00a between the National Semiconductor PC16550D and Resources Used the XPS 16550 UART are highlighted in Specification Min Max Exceptions section. Slices Refer to the Table 17, Table 18 and LUTs Features Table 19, Table 20, Table 21 FFs • Connects as a 32-bit Slave on PLB V4.6 bus of 32, 64 Block RAMs N/A and 128 bits data width Special Features N/A • Hardware and software register compatible with all standard 16450 and 16550 UARTs Provided with Core • Implements all standard serial interface protocols Documentation Product Specification − 5, 6, 7 or 8 bits per character Design File Formats VHDL − Odd, Even or no parity detection and Constraints File N/A generation Verification N/A − 1, 1.5 or 2 stop bit detection and generation Instantiation Template N/A − Internal baud rate generator and separate Reference Designs & receiver clock input N/A Application notes − Modem control functions Design Tool Requirements − Prioritized transmit, receive, line status and Xilinx Implementation modem control interrupts ISE® 11.3 or later Tools − False start bit detection and recover Mentor Graphics ModelSim v6.4b − Verification Line break detection and generation or later − Internal loop back diagnostic functionality Mentor Graphics ModelSim v6.4b Simulation − 16 byte transmit and receive FIFOs or later Synthesis XST 11.3 or later Support Provided by Xilinx, Inc. © 2006-2009 Xilinx, Inc., XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. DS577 September 16, 2009 www.xilinx.com 1 Product Specification XPS 16550 UART (v3.00a) Functional Description The XPS 16550 UART implements the hardware and software functionality of the ubiquitous National Semiconductor 16550 UART, that works in both 16450 and 16550 UART modes. For complete details please refer the National Semiconductor data sheet. The XPS 16550 UART performs parallel to serial conversion on characters received from the CPU and serial to parallel conversion on characters received from a modem or microprocessor peripheral. The XPS 16550 UART is capable of transmitting and receiving 8, 7, 6, or 5 bit characters, with 2, 1.5 or 1 stop bits and odd, even or no parity. The XPS 16550 UART can transmit and receive independently. The device can be configured and it’s status monitored via the internal register set. The XPS 16550 UART is capable of signaling receiver, transmitter and modem control interrupts. These interrupts can be masked, are prioritized and can be identified by reading an internal register. The device contains a 16 bit, programmable, baud rate generator and independent 16 byte transmit and receive FIFOs. The FIFOs can be enabled or disabled through software control. The top-level block diagram for the XPS 16550 UART is shown in Figure 1. Figure Top x-ref 1 Serial PLB PLB IPIC UART Interface IPIC_IF Interface Interface Module Interface UART16550 Modem Interface DS577_01_020609 Figure 1: XPS 16550 UART Top-level Block Diagram The top level modules of the XPS 16550 UART are: • PLB Interface Module • IPIC_IF • UART16550 The detailed block diagram for the XPS 16550 UART is shown in Figure 2. 2 www.xilinx.com DS577 September 16, 2009 Product Specification XPS 16550 UART (v3.00a) Figure Top x-ref 2 IP2INTC_Irpt Freeze UART16550 rxrdyN Bus2IP_Clk rclk Receiver Bus2IP_Reset RBR FIFO1 sin THR FIFO1 sout le wr 2 u FCR Transmitter txrdyN rd LCR PLB IPIC_IF LSR ce Mod a IP2Bus_Ack IER baudoutN IP2Bus_Error IIR MCR PLB Interf Bus2IP_Data[24:31] MSR IP2Bus_IntrEvent SCR nd Control a xin IP2Bus_Data[24:31] DLL Baud xout DLM Generator ctsn Decode dcdn dsrn Modem rin Logic dtrn rtsn out1N out2N ddis Note: 1. 16450 UART mode does not support the FCR. 2. 16450 UART mode does not support the FIFOs. DS577_02_020609 Figure 2: XPS 16550 UART Detailed Block Diagram PLB Interface Module PLB Interface Module provides bidirectional interface between UART 16550 module and the PLB. The base element of the PLB Interface Module is slave attachment, which provides the basic functionality of PLB slave operation. IPIC_IF IPIC_IF module incorporates logic to acknowledge the write and read transactions initiated by the plbv46 slave single module to write into the UART 16550 module registers and read from UART 16550 module registers. UART 16550 UART 16550 provides all the core features for transmission, reception of data and modem features of UART. The UART 16550 module of XPS 16550 UART can be configured for 16450 or 16550 mode of operation. This is accomplished by the usage of generic C_IS_A_16550. DS577 September 16, 2009 www.xilinx.com 3 Product Specification XPS 16550 UART (v3.00a) If C_IS_A_16550 set to one, the UART 16550 module has FIFOs instantiated to support 16550 mode of operation. When C_IS_A_16550 is set to zero, the UART 16550 module works without FIFOs in 16450 mode. In 16550 mode, the FIFOs can be enabled by configuring FCR register. XPS 16550 UART I/O Signals The XPS 16550 UART I/O signals are listed and described in Table 1. Table 1: XPS 16550 UART I/O Signals Initial Port Signal Name Interface I/O State Description System Signals Freezes UART for software P1 Freeze System I - debug (active high) Device interrupt output to microprocessor interrupt input P2 IP2INTC_Irpt System O 0 or system interrupt controller (active high) P3 SPLB_Clk System I - PLB clock P4 SPLB_Rst System I - PLB reset (active high) PLB Master Interface Signals P5 PLB_ABus[0 : C_SPLB_AWIDTH-1] PLB I - PLB address bus PLB primary address valid P6 PLB_PAValid PLB I - indicator PLB_masterID[0 : P7 PLB I - PLB current master identifier C_SPLB_MID_WIDTH - 1] P8 PLB_RNW PLB I - PLB read not write P9 PLB_BE[0 : [C_SPLB_DWIDTH/8] - 1] PLB I - PLB byte enables P10 PLB_size[0 : 3] PLB I - PLB transfer size P11 PLB_type[0 : 2] PLB I - PLB transfer type P12 PLB_wrDBus[0 : C_SPLB_DWIDTH - 1] PLB I - PLB write data bus Unused PLB Master Interface Signals P13 PLB_UABus[0 : 31] PLB I - PLB upper address bits P14 PLB_SAValid PLB I - PLB secondary address valid PLB secondary to primary read P15 PLB_rdPrim PLB I - request indicator PLB secondary to primary write P16 PLB_wrPrim PLB I - request indicator P17 PLB_abort PLB I - PLB abort bus request P18 PLB_busLock PLB I - PLB bus lock P19 PLB_MSize[0 : 1] PLB I - PLB data bus width indicator P20 PLB_TAttribute[0 : 15] PLB I - PLB transfer attribute P21 PLB_lockerr PLB I - PLB lock error P22 PLB_wrBurst PLB I - PLB burst write transfer P23 PLB_rdBurst PLB I - PLB burst read transfer P24 PLB_wrPendReq PLB I - PLB pending bus write request 4 www.xilinx.com DS577 September 16, 2009 Product Specification XPS 16550 UART (v3.00a) Table 1: XPS 16550 UART I/O Signals (Contd) Initial Port Signal Name Interface I/O Description State P25 PLB_rdPendReq PLB I - PLB pending bus read request PLB pending read request P26 PLB_rdPendPri[0 : 1] PLB I - priority PLB pending write request P27 PLB_wrPendPri[0 : 1] PLB I - priority P28 PLB_reqPri[0 : 1] PLB I - PLB current request priority PLB Slave Interface Signals P29 Sl_addrAck PLB O 0 Slave address acknowledge P30 Sl_SSize[0 : 1] PLB O 0 Slave data bus size P31 Sl_wait PLB O 0 Slave wait indicator P32 Sl_rearbitrate PLB O 0 Slave rearbitrate bus indicator P33 Sl_wrDack PLB O 0 Slave write data acknowledge Slave write transfer complete P34 Sl_wrComp PLB O 0 indicator P35 Sl_rdBus[0 : C_SPLB_DWIDTH-1] PLB O 0 Slave read data bus P36 Sl_rdDack PLB O 0 Slave read data acknowledge Slave read transfer complete P37 Sl_rdComp PLB O 0 indicator Sl_MBusy[0 : P38 PLB O 0 Slave busy indicator C_SPLB_NUM_MASTERS - 1] Sl_MWrErr[0 : P39 PLB O 0 Slave write error indicator C_SPLB_NUM_MASTERS - 1] Sl_MRdErr[0 : P40 PLB O 0 Slave read error indicator C_SPLB_NUM_MASTERS - 1] Unused PLB Slave Interface Signals Slave terminate write burst P41 Sl_wrBTerm PLB O 0 transfer P42 Sl_rdWdAddr[0 : 3] PLB O 0 Slave read word address Slave terminate read burst P43 Sl_rdBTerm PLB O 0 transfer Sl_MIRQ[0 : P44 PLB O 0 Master interrupt request C_SPLB_NUM_MASTERS - 1] UART Signals 16 x clock signal from the P45 baudoutN Serial O 1 transmitter section of the UART Receiver 16x clock (Optional, may be driven externally under P46 rclk Serial I - control of the C_HAS_EXTERNAL_RCLK parameter) P47 sin Serial I - Serial data input P48 sout Serial O 1 Serial data output DS577 September 16, 2009 www.xilinx.com 5 Product Specification XPS 16550 UART (v3.00a) Table 1: XPS 16550 UART I/O Signals (Contd) Initial Port Signal Name Interface I/O Description State Baud rate generator reference clock (Optional, may be driven P49 xin Serial I - externally under control of the C_HAS_EXTERNAL_XIN parameter) If C_HAS_EXTERNAL_XIN = 0, xout will be 0, if C_HAS_EXTERNAL_XIN = 1 P50 xout Serial O - xout can be used as Baud rate generator reference feedback clock Clear to send (active low). When low, this indicates that P51 ctsN Modem I - the MODEM or data set is ready to exchange data.
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