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Xr ST16C654/654D 2.97V to 5.5V QUAD UART with 64-BYTE FIFO AUGUST 2005 REV

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Xr ST16C654/654D 2.97V to 5.5V QUAD UART with 64-BYTE FIFO AUGUST 2005 REV xr ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO AUGUST 2005 REV. 5.0.2 GENERAL DESCRIPTION FEATURES Pin-to-pin compatible with ST16C454, ST16C554 The ST16C654/654D1 (654) is an enhanced quad • Universal Asynchronous Receiver and Transmitter and TI’s TL16C554AFN and TL16C754BFN (UART) each with 64 bytes of transmit and receive • Intel or Motorola Data Bus Interface select FIFOs, transmit and receive FIFO trigger levels, • Four independent UART channels automatic hardware and software flow control, and ■ Register Set Compatible to 16C550 data rates of up to 1.5 Mbps. Each UART has a set ■ of registers that provide the user with operating status Data rates of up to 1.5 Mbps and control, receiver error indications, and modem ■ 64 Byte Transmit FIFO serial interface controls. Selectable interrupt polarity ■ 64 Byte Receive FIFO with error tags provides flexibility to meet design requirements. An ■ 4 Selectable TX and RX FIFO Trigger Levels internal loopback capability allows onboard ■ Automatic Hardware (RTS/CTS) Flow Control diagnostics. The 654 is available in 64 pin LQFP, 68 ■ Automatic Software (Xon/Xoff) Flow Control pin PLCC and 100 pin QFP packages. The 64 pin ■ package only offers the 16 mode interface, but the 68 Progammable Xon/Xoff characters and 100 pin packages offer an additional 68 mode ■ Wireless Infrared (IrDA 1.0) Encoder/Decoder interface which allows easy integration with Motorola ■ Full modem interface processors. The ST16C654CQ64 (64 pin) offers • 2.97V to 5.5V supply operation three state interrupt output while the Sleep Mode (200 uA typical) ST16C654DCQ64 provides continuous interrupt • output. The 100 pin package provides additional • Crystal oscillator or external clock input FIFO status outputs (TXRDY# and RXRDY# A-D), APPLICATIONS separate infrared transmit data outputs (IRTX A-D) and channel C external clock input (CHCCLK). The • Portable Appliances ST16C654/654D is compatible with the industry • Telecommunication Network Routers standard ST16C454 and ST16C654/554D. • Ethernet Network Routers NOTE: 1 Covered by U.S. Patent #5,649,122. • Cellular Data Devices • Factory Automation and Process Controls FIGURE 1. ST16C654 BLOCK DIAGRAM 2.97V to 5.5V VCC A2:A0 GND D7:D0 UART Channel A IOR# UART 64 Byte TX FIFO IOW# TXA, RXA, IRTXA, DTRA#, Regs IR DSRA#, RTSA#, CTSA#, CSA# TX & RX ENDEC CDA#, RIA# CSB# BRG 64 Byte RX FIFO CSC# CSD# UART Channel B TXB, RXB, IRTXB, DTRB#, DSRB#, RTSB#, CTSB#, INTA (same as Channel A) Data Bus CDB#, RIB# INTB Interface INTC UART Channel C TXC, RXC, IRTXC, DTRC#, INTD (same as Channel A) DSRC#, RTSC#, CTSC#, CHCCLK CDC#, RIC# TXRDY# A-D UART Channel D TXD, RXD, IRTXD, DTRD#, RXRDY# A-D (same as Channel A) DSRD#, RTSD#, CTSD#, Reset CDD#, RID# 16/68# INTSEL Crystal Osc/Buffer XTAL1 CLKSEL XTAL2 654 BLK Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com 2.97V TO5.5VQUAD UART WITH 64-BYTE FIFO ST16C654/654D F IGURE RXRDYD# RXRDYD# RXRDYA# RXRDYA# TXRDYD# TXRDYD# INTSEL INTSEL CDD# CDD# CDA# CDA# RID# RID# RIA# RIA# 2. P GND GND VCC RXD VCC RXD RXA RXA D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 100 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 IN O N.C. 1 80 N.C. N.C. 1 80 N.C. UT N.C. 2 79 N.C. N.C. 2 79 N.C. A N.C. 3 N.C. 3 78 N.C. 78 N.C. SSIGNMENT N.C. 4 77 N.C. N.C. 4 77 N.C. TXRDYA# 5 76 FSRS# TXRDYA# 5 76 FSRS# IRTXA 6 75 IRTXD IRTXA 6 75 IRTXD DSRA# 7 DSRA# 7 74 DSRD# 74 DSRD# F CTSA# 8 73 CTSD# CTSA# 8 73 CTSD# OR DTRA# 9 72 DTRD# DTRA# 9 72 DTRD# 100- VCC 10 71 GND VCC 10 71 GND Connect 16/68# pintoGND 16/68# Connect PIN RTSA# 11 70 RTSD# RTSA# 11 pintoVCC 16/68# Connect 70 RTSD# IRQ# 12 69 N.C. INTA 12 69 INTD P QFP CSA# 13 Mode Motorola 68 N.C. CSA# 13 68 CSD# 100-pin QFP 100-pin QFP ST16C654 ST16C654 Intel Mode Intel TXA 14 67 TXD TXA 14 67 TXD ACKAGES R/W# 15 66 N.C. IOW# 15 66 IOR# 2 TXB 16 65 TXC TXB 16 65 TXC A3 17 64 A4 CSB# 17 64 CSC# N.C. 18 63 N.C. INTB 18 63 INTC I N RTSB# 19 62 RTSC# RTSB# 19 62 RTSC# 16 GND 20 61 VCC GND 20 61 VCC AND DTRB# 21 60 DTRC# DTRB# 21 60 DTRC# CTSB# 22 59 CTSC# CTSB# 22 59 CTSC# 68M DSRB# 23 58 DSRC# DSRB# 23 58 DSRC# IRTXB 24 57 IRTXC IRTXB 24 57 IRTXC ODE TXRDYB# 25 56 TXRDYC# TXRDYB# 25 56 TXRDYC# N.C. 26 55 N.C. N.C. 26 55 N.C. N.C. 27 54 N.C. N.C. 27 54 N.C. N.C. 28 53 N.C. N.C. 28 53 N.C. N.C. 29 52 N.C. N.C. 29 52 N.C. xr N.C. 30 51 N.C. N.C. 30 51 N.C. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CDC# CDC# REV. 5.0.2 CLKSEL CLKSEL RXRDYB# CDB# RIB# RXB 16/68# XTAL1 XTAL2 CHCCLK RESET RXRDY# TXRDY# GND RXC RIC# RXRDYC# RXRDYB# CDB# RIB# RXB 16/68# XTAL1 XTAL2 CHCCLK RESET RXRDY# TXRDY# GND RXC RIC# RXRDYC# A2 A1 A0 A2 A1 A0 xr ST16C654/654D REV. 5.0.2 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO FIGURE 3. PIN OUT ASSIGNMENT FOR PLCC PACKAGES IN 16 AND 68 MODE AND LQFP PACKAGES GND D7 D6 D5 D4 D3 D2 D1 D0 INTSEL VCC RXD GND D7 D6 D5 D4 D3 D2 D1 D0 VCC RXD CDA# RIA# RXA RID# CDD# CDA# RIA# RXA GND RID# CDD# 9 8 7 6 5 4 3 2 1 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 63 68 67 66 65 64 63 62 63 DSRA# 10 60 DSRD# DSRA# 10 60 DSRD# CTSA# 11 59 CTSD# CTSA# 11 59 CTSD# DTRA# 12 58 DTRD# DTRA# 12 58 DTRD# VCC 13 57 GND VCC 13 57 GND RTSA# 14 56 RTSD# RTSA# 14 56 RTSD# INTA 15 55 INTD IRQ# 15 55 N.C. CSA# 16 ST16C654 54 CSD# CS# 16 ST16C654 54 N.C. TXA 17 68-pin PLCC 53 TXD TXA 17 68-pin PLCC 53 TXD IOW# 18 Intel Mode 52 IOR# R/W# 18 Motorola Mode 52 N.C. TXB 19 (16/68# pin connected to VCC) 51 TXC TXB 19 (16/68# pin connected to GND) 51 TXC CSB# 20 50 CSC# A3 20 50 A4 INTB 21 49 INTC N.C. 21 49 N.C. RTSB# 22 48 RTSC# RTSB# 22 48 RTSC# GND 23 47 VCC GND 23 47 VCC DTRB# 24 46 DTRC# DTRB# 24 46 DTRC# CTSB# 25 45 CTSC# CTSB# 25 45 CTSC# DSRB# 26 44 DSRC# DSRB# 26 44 DSRC# 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 A2 A1 A0 A2 A1 A0 RXB RXB RXC RXC GND GND RIB# RIB# RIC# RIC# CDB# CDB# CDC# CDC# 16/68# 16/68# XTAL1 XTAL2 XTAL1 XTAL2 RESET RESET CLKSEL CLKSEL TXRDY# TXRDY# RXRDY# RXRDY# RXA D2 RXD D7 D1 VCC D6 D5 D4 D0 D3 GND RID# CDD# CDA# RIA# 64 60 56 54 52 51 62 61 59 57 55 50 58 49 53 63 DSRA# 1 48 DSRD# CTSA# 2 47 CTSD# DTRA# 3 46 DTRD# VCC 4 45 GND RTSA# 5 44 RTSD# INTA 6 ST16C654 43 INTD CSA# 7 ST16C654D 42 CSD# TXA 8 64-pin TQFP 41 TXD IOR# IOW# 9 Intel Mode Only 40 TXB 10 39 TXC CSB# 11 38 CSC# INTB 12 37 INTC RTSB# 13 36 RTSC# GND 14 35 VCC DTRB# 15 34 DTRC# CTSB# 16 33 CTSC# 31 21 29 30 23 26 22 32 25 27 28 20 24 17 18 19 A0 A1 A2 RIB# RXC RXB RIC# GND CDB# CDC# XTAL1 XTAL2 DSRB# DSRC# RESET CLKSEL ORDERING INFORMATION OPERATING OPERATING DEVICE DEVICE PART NUMBER PACKAGE TEMPERATURE PART NUMBER PACKAGE TEMPERATURE STATUS STATUS RANGE RANGE ST16C654CJ68 68-Lead PLCC 0°C to +70°C Active ST16C654DCQ64 64-Lead LQFP 0°C to +70°C Active ST16C654IJ68 68-Lead PLCC -40°C to +85°C Active ST16C654DIQ64 64-Lead LQFP -40°C to +85°C Active ST16C654CQ64 64-Lead LQFP 0°C to +70°C Active ST16C654CQ100 100-Lead QFP 0°C to +70°C Active ST16C654IQ64 64-Lead LQFP -40°C to +85°C Active ST16C654IQ100 100-Lead QFP -40°C to +85°C Active 3 ST16C654/654D xr 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.2 PIN DESCRIPTIONS Pin Description 64-LQFP 68-PLCC 100-QFP NAME TYPE DESCRIPTION PIN # PIN# PIN # DATA BUS INTERFACE A2 22 32 37 I Address data lines [2:0].
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