RS232/422/485 Serial Communications
Total Page:16
File Type:pdf, Size:1020Kb
Load more
Recommended publications
-
DAN189 EXAR UARTS in GPS APPLICATIONS March 2007 EXAR UARTS in GPS APPLICATIONS
DAN189 EXAR UARTS IN GPS APPLICATIONS March 2007 EXAR UARTS IN GPS APPLICATIONS 1.0 INTRODUCTION This application note describes where an Exar UART can be used in a Global Positioning System (GPS) application. GPS has traditionally been used in military applications such as marine navigation, aircraft navigation, and weapon’s guidance. However, GPS applications have recently expanded to industrial and consumer applications such as vehicle navigation systems, fleet management, and personal navigation. In these applications, the Exar UART can be used in the GPS receiver and in the GPS application. FIGURE 1. GPS APPLICATION EXAMPLES GPS Applications Marine Navigation System Aircraft Navigation System Vehicle Navigation System Fleet Management System Personal Navigation System GPS Receiver TX RX UART RX TX UART 1.1 GPS Receiver A GPS receiver typically includes the following: • RF block for receiving the GPS data and converting it to digital data • Microprocessor for processing the data • ROM to store the firmware for processing the data • RAM used by the microprocessor for data processing • UART to send data to the GPS application The figure below shows a block diagram of a GPS receiver. FIGURE 2. GPS RECEIVER BLOCK DIAGRAM ROM RAM RF Block TX Microprocessor UART RX 1 DAN189 EXAR UARTS IN GPS APPLICATIONS The figure below shows a block diagram of an automobile GPS navigation system: FIGURE 3. AUTOMOBILE GPS NAVIGATION SYSTEM EXAMPLE Keypad ROM RAM Radio CD RX GPS UART Microprocessor DVD TX LCD The UART that has been used in the GPS receiver or in the GPS application has typically been an industry standard 16550 UART or a UART that is available on the microprocessor. -
MC88(I)Terminal Users Guide
MC 88(i)T User Guide MC88(i)Terminal Users Guide Title: MC88(i)T User Guide Version: 0.0.0.2 Status: Preliminary Date: November 14, 2012 Doc: MC88(i)T_UG_EN_Rel. 0.2 Author: Wacker Copyright: MC Technologies GmbH, Hannover / Germany MC88(i)Term_UG_en_141112.doc Page 1 of 22 MC 88(i)T User Guide 1.1 Contents 1.1 Contents ......................................................................................................................................... 2 1.2 Figures ........................................................................................................................................... 3 1.3 Tables ............................................................................................................................................ 3 1.4 Revision history .............................................................................................................................. 3 1.5 Legal information ........................................................................................................................... 3 1.5.1 Definitions ................................................................................................................................ 3 1.5.2 Disclaimers .............................................................................................................................. 4 1.6 Terms and abbreviations ............................................................................................................... 4 1.7 Related documents ....................................................................................................................... -
Telecommunications Handbook: Connecting to NEWTON
DOCUMENT RESUME ED 375 804 IR 016 847 AUTHOR Baker, Christopher; And Others TITLE Telecommunications Handbook: Connecting to NEWTON. Version 1.4. INSTITUTION Argonne National Lab., IL. Div of Educational. Programs. SPONS AGENCY Department of Energy, Washington, D.C. PUB DATE Mar 94 CONTRACT W-31-109-Eng-38 NOTE 26p.; For an earlier version of this handbook, see ED 366 323. PUB TYPE Guides Non-Classroom Use (055) Reports Descriptive (141) EDRS PRICE MF01/PCO2 Plus Postage. DESCRIPTORS Computer Uses in Education; *Electronic Mail; Elementary Secondary Education; Information Dissemination; *Information Networks; *Online Systems; *Science Education; Scientists; Teachers; *Telecommunications IDENTIFIERS *Argonne National Laboratory IL; *Newton Bulletin Board System ABSTRACT This handbook was written for use with the Argonne National Laboratory's electronic bulletin board system (BBS) called NEWTON, which is designed to create an electronic network that will link scientists, teachers, and students with the many diversified resources of the Argonne National Laboratory. The link to Argonne will include such resources as scientists, research programs, and educational programs (workshops, conferences, and instructional materials), and serve as a forum for sharing knowledge, new ideas, and teaching materials. Through the BBS, students will be able to interact with fellow students throughout the nation, and/the BBS will help to build a teacher support group that will work with established teacher-alliance networks and worldwide research networks, including Internet. This manual begins with the mission statement which identifies objectives, primary users, materials, and services of NEWTON. The introduction then examines telecommunications and education and the NEWTON BBS. Additional sections contain information on accessing NEWTON; equipment needed to login to NEWTON; the setup of the equipment; the login procedure; and a list of NEWTON's features including system, personal, and group features. -
Ds430 Opb 16550 Uart
0 OPB 16550 UART (v1.00d) DS430 December 2, 2005 0 0 Product Specification Introduction LogiCORE™ Facts This document provides the specification for the OPB Core Specifics 16550 UART (Universal Asynchronous QPro™-R Virtex™-II, QPro Receiver/Transmitter) Intellectual Property (IP). Virtex-II, Spartan™-II, Spartan-IIE, Supported Device Spartan-3, Spartan-3E, Virtex, The OPB 16550 UART described in this document has Family Virtex-II, Virtex-II Pro, Virtex-4, been designed incorporating features described in Virtex-E National Semiconductor PC16550D UART with FIFOs data Version of Core opb_uart16550 v1.00d sheet (June,1995),Discontinued (http://www.national.com/pf/PC/PC16550D.html). Resources Used The National Semiconductor PC16550D data sheet is Min Max referenced throughout this document and should be Slices 283 417 used as the authoritative specification. Differences LUTs 328 545 between the National Semiconductor implementation and the OPB 16550 UART Point Design implementation FFs 275 338 are highlighted and explained in Specification Block RAMs Exceptions. Provided with Core Features Documentation Product Specification • Hardware and software register compatible with all Design File Formats VHDL standard 16450 and 16550 UARTs Constraints File N/A • Implements all standard serial interface protocols Verification N/A - 5, 6, 7, or 8 bits per character Instantiation Template N/A - Odd, Even, or no parity detection and generation Reference Designs None - 1, 1.5, or 2 stop bit detection and generation Design Tool Requirements - Internal baud rate generator and separate receiver Xilinx Implementation ISE 6.1i or later clock input Tools - Modem control functions Verification ModelSim SE/EE 5.8e or later Simulation IPModelSim SE/EE 5.8e or later - False start bit detection and recovery - Prioritized transmit, receive, line status, and Synthesis XST modem control interrupts Support - Line break detection and generation Support provided by Xilinx, Inc. -
Serial Communication Buses
Computer Architecture 10 Serial Communication Buses Made wi th OpenOffi ce.org 1 Serial Communication SendingSending datadata oneone bitbit atat oneone time,time, sequentiallysequentially SerialSerial vsvs parallelparallel communicationcommunication cable cost (or PCB space), synchronization, distance ! speed ? ImprovedImproved serialserial communicationcommunication technologytechnology allowsallows forfor transfertransfer atat higherhigher speedsspeeds andand isis dominatingdominating thethe modernmodern digitaldigital technology:technology: RS232, RS-485, I2C, SPI, 1-Wire, USB, FireWire, Ethernet, Fibre Channel, MIDI, Serial Attached SCSI, Serial ATA, PCI Express, etc. Made wi th OpenOffi ce.org 2 RS232, EIA232 TheThe ElectronicElectronic IndustriesIndustries AllianceAlliance (EIA)(EIA) standardstandard RS-232-CRS-232-C (1969)(1969) definition of physical layer (electrical signal characteristics: voltage levels, signaling rate, timing, short-circuit behavior, cable length, etc.) 25 or (more often) 9-pin connector serial transmission (bit-by-bit) asynchronous operation (no clock signal) truly bi-directional transfer (full-duplex) only limited power can be supplied to another device numerous handshake lines (seldom used) many protocols use RS232 (e.g. Modbus) Made wi th OpenOffi ce.org 3 Voltage Levels RS-232RS-232 standardstandard convertconvert TTL/CMOS-levelTTL/CMOS-level signalssignals intointo bipolarbipolar voltagevoltage levelslevels toto improveimprove noisenoise immunityimmunity andand supportsupport longlong cablecable lengthslengths TTL/CMOS → RS232: 0V = logic zero → +3V…+12V (SPACE) +5V (+3.3V) = logic one → −3V…−12V (MARK) Some equipment ignores the negative level and accepts a zero voltage level as the "OFF" state The "dead area" between +3V and -3V may vary, many receivers are sensitive to differentials of 1V or less Made wi th OpenOffi ce.org 4 Data frame CompleteComplete one-byteone-byte frameframe consistsconsists of:of: start-bit (SPACE), data bits (7, 8), stop-bits (MARK) e.g. -
SCR1 SDK. Altera Arria-V Starter Kit Edition. Quick Start Guide
SCR1 SDK. Altera Arria-V Starter Kit Edition. Quick Start Guide © Syntacore, [email protected] Version 1.4, 2019-04-08 Table of Contents Revision History . 2 1. Setup equipment. 3 1.1. Prerequisites . 3 2. SDK HW assembly . 4 2.1. Connecting serial console . 4 2.2. Pins assignment. 4 3. Arria-V HW image update . 6 4. Booting the new FPGA image . 8 5. Resetting the board: . 9 6. UART connection settings . 9 7. Using UART terminal . 10 7.1. Load binary images to the Memory address . 10 7.2. Example: Dhrystone run from TCM memory . 12 7.3. Using OpenOCD. 13 7.3.1. Installing OpenOCD . 13 7.3.2. Starting the OpenOCD server. 13 7.3.3. Downloading and running an image using OpenOCD. 14 8. Building SDK FPGA-project for the Arria V GX SDK. 16 8.1. General structure of the SDK project. 16 8.2. Additional requirements for compilation . 16 8.3. Building SDK FPGA project. 17 8.3.1. FPGA firmware generation (sof-format) . 17 8.3.2. Converting FPGA-image to the board flash memory image (flash-format) . 17 8.3.3. SDK-specific pins assignment in FPGA-project . 19 8.4. SCR1 SDK FPGA-project functional description . 20 8.4.1. Common project structure . 20 8.4.2. Qsys SoC module structure. 20 8.4.3. Description of the blocks used in the SDK project . 21 8.4.3.1. SCR1-core. 21 8.4.3.2. AXI bridge . 21 8.4.3.3. Opencores UART 16550 IP . 21 8.4.4. -
TS 102 511 V1.1.1 (2007-08) Technical Specification
ETSI TS 102 511 V1.1.1 (2007-08) Technical Specification Human Factors (HF); AT Commands for Assistive Mobile Device Interfaces 2 ETSI TS 102 511 V1.1.1 (2007-08) Reference DTS/HF-00091 Keywords GSM, HF, ICT, interface, MMI, mobile, service, telephony, terminal, UMTS, user ETSI 650 Route des Lucioles F-06921 Sophia Antipolis Cedex - FRANCE Tel.: +33 4 92 94 42 00 Fax: +33 4 93 65 47 16 Siret N° 348 623 562 00017 - NAF 742 C Association à but non lucratif enregistrée à la Sous-Préfecture de Grasse (06) N° 7803/88 Important notice Individual copies of the present document can be downloaded from: http://www.etsi.org The present document may be made available in more than one electronic version or in print. In any case of existing or perceived difference in contents between such versions, the reference version is the Portable Document Format (PDF). In case of dispute, the reference shall be the printing on ETSI printers of the PDF version kept on a specific network drive within ETSI Secretariat. Users of the present document should be aware that the document may be subject to revision or change of status. Information on the current status of this and other ETSI documents is available at http://portal.etsi.org/tb/status/status.asp If you find errors in the present document, please send your comment to one of the following services: http://portal.etsi.org/chaircor/ETSI_support.asp Copyright Notification No part may be reproduced except as authorized by written permission. The copyright and the foregoing restriction extend to reproduction in all media. -
Low-Profile PCI Cards: a New Approach to Inner Space • Lavalanche Winners! • Distributor Profile Lava I/O News
April 2002 Vol.4 No.4 Inside this issue: • Low-profile PCI cards: A New Approach to Inner Space • Lavalanche Winners! • Distributor profile Lava I/O News Low-Profile PCI Cards: A New Approach to Inner Space Most of us remember our first impression on looking inside the chassis of a desktop or tower computer: is that all there is? Apart from the motherboard, power supply, drives and cables, a few cards, and dust bunnies, things were pretty empty in there. And while we knew that air had to circulate inside the case, the empty spaces inside still seemed a bit large. Notebook computers came along and really confirmed the impression that the inside of typical computers had enough extra space for a game of baseball. sets standards for the PCI bus generally. As well as defining a maximum height for Low-profile PCI cards follow the “PCI Local cards designated as “low-profile”, the low-pro- The reason for all the empty space is historical: Bus Specification, Revision 2.2” or later, but file PCI specification also outlines two low-pro- the original PC's expansion cards were loaded in addition adopt the form factor require- file PCI card lengths —short (called “MD1”) with lots of separate and large components. ments of the new "PCI Engineering Change and long (“MD2”).An MD1 low-profile card has They were rather tall, and needed to be so. Notice —Low Profile PCI Card". Designed as a a maximum length of 4.72" (119.91 mm). An However, as integrated circuit technology collaborative effort by the PCI Special Interest MD2 card is longer than an MD1 card, but not advanced, expansion boards got smaller and Group and companies including IBM and longer than 6.6" (167.64 mm). -
Z182 Com Port Appnote
HIGH PERFORMANCE PC COMMUNICATION Zilog PORT USING THE Z182 MICROCONTROLLER HIGH PERFORMANCE PC COMMUNICATION PORT USING THE Z182 o meet the demands of high speed communications on the Information Superhighway, Zilog's Z182-based PC Communication Port "COMPORT.S™" software code provides the user with increased data buffering capabilities for faster communication between PCs T and modems. INTRODUCTION With the advent of the Information Superhighway, users will handle heavy traffic at only a sustained rate of 57.6 Kbps. be able to access information quickly and easily by means This factor, combined with limited CPU bandwidth (due to of PC/Modem communications. However, user-friendly complex operating systems), means users cannot take full operating systems, capable of processing large amounts advantage of the high throughput that today’s modems of data, become so performance intensive that data com- can accommodate. munication becomes a bottleneck. Although there have been many advances in modem and PC design, a satis- PC Week's labs (July 1992) analyzed the serial card factory solution to the PC/modem communication bottle- bottleneck issue and their tests showed that a standard neck has not been found. serial card could not reliably sustain data transfer over 19.2 Kbps. However, when using a 16550 UART loaded The PC/Modem communication bottleneck is caused by serial card, the user could expect 57.6 Kbps of reliable, the PC standard serial cards used to connect to the sustained data transfer. This is great for V.32bis, but what modems. Conventional serial cards were designed to about V.FAST and beyond? Serial Port Limitations If you look at a PC Standard Serial Card, you will find a 8250 quickly to interrupts in a multi-tasking system? The answer or 16450 UART as well as RS-232 line drivers. -
XR20M1170 Data Sheet
XR20M1170 I2C/SPI UART WITH 64-BYTE FIFO JUNE 2019 REV. 1.1.2 GENERAL DESCRIPTION FEATURES 1.62 to 3.6 Volt operation The XR20M11701 is a high performance universal asynchronous receiver and transmitter (UART) with Selectable I2C/SPI interface 64 byte TX and RX FIFOs and a selectable I2C/SPI SPI clock frequency up to slave interface. The XR20M1170 operates from 1.62 to 3.63 volts. The enhanced features in the 18MHz at 3.3V XR20M1170 include a programmable fractional baud 16MHz at 2.5V rate generator, an 8X and 4X sampling rate that 8MHz at 1.8V allows for a maximum baud rate of 16Mbps at 3.3V. The standard features include 16 selectable TX and Full-featured UART RX FIFO trigger levels, automatic hardware (RTS/ Data rate of up to 16Mbps at 3.3V CTS) and software (Xon/Xoff) flow control, and a Data rate of up to 12.5Mbps at 2.5V complete modem interface. Onboard registers provide the user with operational status and data Data rate of up to 8Mbps at 1.8V error flags. An internal loopback capability allows Fractional baud rate generator system diagnostics. The XR20M1170 is available in Transmit and receive FIFOs of 64 bytes the 24-pin QFN, 16-pin QFN, 24-pin TSSOP and 16- 16 selectable TX and RX FIFO trigger levels pin TSSOP packages. Automatic hardware (RTS/CTS) flow control NOTE: 1 Covered by U.S. Patent #5,649,122 Automatic software (Xon/Xoff) flow control APPLICATIONS Halt and resume transmission control Portable appliances Automatic RS-485 half-duplex direction control output via RTS# Battery-operated devices Wireless Infrared (IrDA 1.0 and 1.1) encoder/ Cellular data devices decoder Factory automation and process controls Automatic sleep mode (< 15uA at 3.3V) General purpose I/Os Full modem interface Crystal oscillator (up to 24MHz) or external clock (up to 64MHz) input 24-QFN, 16-QFN, 24-TSSOP, 16-TSSOP packages FIGURE 1. -
Microprocessors and Microcontrollers (EE-231) Main Objectives
Microprocessors and Microcontrollers (EE-231) Main Objectives • 16550 Communication Device • ADC and DAC interfacing 16550 Programmable Communications Interface • National Semiconductor Corp’s PC16550D is a programmable communications interface designed to connect to virtually any type of serial interface. • 16550 is a universal asynchronous receiver/transmitter (UART) fully compatible with Intel microprocessors. • 16550 operates at 0–1.5 M baud. – baud rate is bps (bits transferred per second) including start, stop, data, and parity • 16550 also includes a programmable baud rate generator and separate FIFOs for input and output data to ease the load on the microprocessor. • Each FIFO contains 16 bytes of storage. • The most common communications interface found in the PC and many modems. Asynchronous Serial Data • Asynchronous serial data are transmitted and received without a clock and in frames as shown in figure. – each frame contains a start bit, seven data bits, parity, and one stop bit • Most Internet services use 10 bits, but normally do not use parity. • instead, eight data bits are transferred, replacing parity with a data bit 16550 Functional Description • The device is available as a 40-pin DIP (dual in-line package) or as a 44-pin PLCC (plastic leadless chip carrier). • Two completely separate sections are responsible for data communications. – the receiver and the transmitter • Because each sections is independent, 16550 is able to function in simplex, half-duplex, or full-duplex modes. The pin-out of the 16550 UART. 16550 Functional Description • A major feature of the 16550 is its internal receiver and transmitter FIFO (first-in, first-out) memories. • Because each is 16 bytes deep, the UART requires attention from the processor only after receiving 16 bytes of data. -
Using C-Kermit 2Nd Edition
<< Previous file Chapter 1 Introduction An ever-increasing amount of communication is electronic and digital: computers talking to computers Ð directly, over the telephone system, through networks. When you want two computers to communicate, it is usually for one of two reasons: to interact directly with another computer or to transfer data between the two computers. Kermit software gives you both these capabilities, and a lot more too. C-Kermit is a communications software program written in the C language. It is available for many different kinds of computers and operating systems, including literally hundreds of UNIX varieties (HP-UX, AIX, Solaris, IRIX, SCO, Linux, ...), Digital Equipment Corporation (Open)VMS, Microsoft Windows NT and 95, IBM OS/2, Stratus VOS, Data General AOS/VS, Microware OS-9, the Apple Macintosh, the Commodore Amiga, and the Atari ST. On all these platforms, C-Kermit's services include: • Connection establishment. This means making dialup modem connections or (in most cases) network connections, including TCP/IP Telnet or Rlogin, X.25, LAT, NET- BIOS, or other types of networks. For dialup connections, C-Kermit supports a wide range of modems and an extremely sophisticated yet easy-to-use dialing directory. And C-Kermit accepts incoming connections from other computers too. • Terminal sessions. An interactive terminal connection can be made to another com- puter via modem or network. The Windows 95, Windows NT, and OS/2 versions of C-Kermit also emulate specific types of terminals, such as the Digital Equipment Cor- poration VT320, the Wyse 60, or the ANSI terminal types used for accessing BBSs or PC UNIX consoles, with lots of extras such as scrollback, key mapping, printer con- trol, colors, and mouse shortcuts.