Retargetable Compilers and Tools for Embedded Processors in Industrial Applications Cl
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Retargetable compilers and tools for embedded processors in industrial applications Cl. B. Liem To cite this version: Cl. B. Liem. Retargetable compilers and tools for embedded processors in industrial applications. Micro and nanotechnologies/Microelectronics. Institut National Polytechnique de Grenoble - INPG, 1997. English. tel-00010762 HAL Id: tel-00010762 https://tel.archives-ouvertes.fr/tel-00010762 Submitted on 26 Oct 2005 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. THESE présentée par LIEM, Clifford Benjamin B. Sc., M. Eng. pour obtenir le grade de DOCTEUR de l’INSTITUT NATIONAL POLYTECHNIQUE DE GRENOBLE (arrêté ministériel du 30 Mars 1992) spécialité: Microélectronique Compilateurs Multicibles et Outils pour les Processeurs Embarqués dans le cadre d’Applications Industrielles Date de soutenance: 18 juillet, 1997 Composition du Jury: Messieurs Bernard COURTOIS : Président Rolf ERNST : Rapporteur Patrice QUINTON : Rapporteur Pierre PAULIN : Examinateur Ahmed JERRAYA : Directeur Thèse préparée au sein du Laboratoire TIMA-INPG 46, avenue Félix Viallet, 38031 Grenoble, FRANCE THESIS presented by LIEM, Clifford Benjamin B. Sc., M. Eng. to obtain the title of DOCTOR of the NATIONAL POLYTECHNICAL INSTITUTE OF GRENOBLE specialty: Microelectronics Retargetable Compilers and Tools for Embedded Processors in Industrial Applications Defence Date: July 18, 1997 Composition of the Jury: Misters Bernard COURTOIS : President Rolf ERNST : Report Examiner Patrice QUINTON : Report Examiner Pierre PAULIN : Examiner Ahmed JERRAYA : Director This thesis was prepared at the TIMA Laboratory, INPG 46, avenue Félix Viallet, 38031 Grenoble, FRANCE iii Abstract Embedded core processors are becoming a vital part of today’s system-on-a-chip in the growing areas of telecommunications, multimedia and consumer electronics. This is mainly in response to a need to track evolving standards with the flexibility of embedded software. Consequently, maintaining the high product performance and low product cost requires a careful design of the processor tuned to the appli- cation domain. With the increased presence of instruction-set processors, retargetable software compilation techniques are critical, not only for improving engineering productiv- ity, but to allow designers to explore the architectural possibilities for the applica- tion domain. The contributions of this thesis are primarily in the following three categories: • methods and experiences using a retargetable compiler methodology for embed- ded processors in industry. • an augmentation of the knowledge necessary for compiling abstract source code for DSP architectures. • a set of tools which allow the designer to explore an instruction-set architecture for a set of compiled code in the light of redesigning the processor for an evolu- tion or reuse of the architecture. The manuscript begins with an overview of the techniques of modern retargeta- ble compilers and shows the application of practical techniques to embedded instruction-set processors. The methods are highlighted with examples from indus- try processors used in products for multimedia, telecommunications, and consumer electronics. An emphasis is given to the methodology and experience gained in applying two different retargetable compiler approaches in industrial settings. Many pragmatic areas such as language support, source code abstraction levels, validation strategies, and source-level debugging are also discussed. In addition, new compiler techniques are presented which support address gen- eration for DSP architectures. The contribution is an address calculation transfor- mation based on an architectural model. This model allows the programmer to iv write his algorithm on a more abstract level which encourages portability of code. Furthermore, the architectural model allows the designer to explore different con- figurations of the hardware for better running of the algorithm. As a natural complement to the compiler techniques which have been pre- sented, new utilities for the design of embedded processors are described. As the lifetime of an embedded processor is rich with architectural variations and design reuse, these aids provide ways of analyzing the match between application code and the instruction-set. Two tools allow the designer to obtain both static and dynamic feedback on the fit of the processor in the application domain. These tools allow the designer to explore the architecture space as well as the algorithm execu- tion. The material contained in this thesis has been accepted to be published in the form of a book by Kluwer Academic Publishers. v Acknowledgments A great number of people have contributed to the work contained in this book and I would like to thank each one of them for their help and support. To Pierre Paulin, thank-you for nearly six years of productive and interesting cooperation. In addi- tion to being a role model for my technical career, you’ve also been a supporting friend, always looking out for my best interests. To Ahmed Jerraya, thanks for the open welcome into your team. You’ve motivated me in more ways than I could describe. I would like to thank the examiners (i.e. rapporteurs): Prof. Rolf Ernst and Prof. Patrice Quinton for having accepted and efficiently reviewed this work. Fur- thermore, I thank Bernard Courtois for his presence as president of the jury. To Marco Cornero, thank-you for your diligent corrections to this text, not to mention your technical contributions to the projects. You’ve been a pleasure to work with both professionally and personally. To François Naçabal, thanks for your support through my time in France both as a friend and colleague. To the rest of the Embedded Systems Team at SGS-Thomson: Miguel Santana, Etienne Lant- reibecq, Frank Ghenaissa, Michel Favre, Frédéric Rocheteau, and Thierry Lepley, thank-you for many positive discussions both in groups and one-on-one. To the TIMA Laboratory and particularly the Systems Level Synthesis group, thank-you for making my stay enjoyable and productive. I especially thank (in no particular order) Maher Rahmouni, Imed Moussa, Gilberto Marchioro, Jean-Marc Daveau, Carlos Valderrama, Jean Fréhel, Julia Dushina, Wander Cesario, Richard Pistorius, Hong Ding, Tarek Ben-Ismail, Mohamed Romdhani, Mohamed Abid, M. Ben Mohammed, Polen Kission, and Ricardo de Oliveira Duarte for many tech- nical and personal discussions. Furthermore, I thank Phillippe Guillaume for his careful corrections of the French summary of this writing. And to the rest of the TIMA/CMP Laboratory headed faithfully by Bernard Courtois, I thank you for a comfortable working environment with such a qualified staff. I give particular thanks to Isabelle Essalhiene-Schauner, Corinne Durand-Viel, Chantal Benis and Patricia Chassat. vi To the IVT design team of SGS-Thomson in particular Michel Harrand, Olivier Deygas, José Sanches, and Elisabeth Berrebi, thanks for the many fulfilling coop- erations. To the MMDSP design team at Thomson Consumer Electronic Compo- nents, I thank Laurent Bergher, Jean-Marc Gentit, Xavier Figari, and Jean Lopez for giving me the opportunity to know and work with you. Finally, to the DPG Video design team of SGS-Thomson: Richard Chesson, Giovanni Martinelli, and Min Xue, thanks for the openness in using my prototype design tools. I would like to thank Central R&D of SGS-Thomson Microelectronics includ- ing Jo Borel, Yves Duflos and Jean-Pierre Moreau for the support of this project. I would also like to thank Bell-Northern Research/Nortel including Dave Agnew and Terry Thomas for their support of this project. I especially thank Donna Ger- vais for her tireless help throughout this co-operation. I would also like to thank my former colleagues at Nortel for their technical contributions which sparked the beginnings of much of this work: Trevor May, Shailesh Sutarwala, Francis Lan- glois, and Chris Donawa. And to my wife Christine Sauvé-Liem, your love and support was the final link that gave me the motivation to complete this work. Thanks for always being by my side. I also give you a special thanks for help in the design of the book cover. You have a wonderfully creative gift. Finally, I thank You, my Lord and Saviour, Jesus Christ, for your unending love and grace all the days of my life. vii Table of Contents Abstract . iii Acknowledgments . .v Table of Contents . vii List of Figures . xi List of Tables . xv 0 Présentation Générale en Français . .0-1 Résumé . .0-1 0.1 Introduction . .0-2 0.2 Techniques de compilation pour les processeurs embarqués . .0-3 0.2.1 Le processus de compilation traditionnel . .0-3 0.2.2 Le concept de compilation multicibles . .0-5 0.2.3 Techniques dédiées aux processeurs spécialisés . .0-6 0.3 Deux approches de compilation récentes . .0-7 0.3.1 Résumé des concepts . .0-7 0.3.2 CodeSyn: un compilateur fondé sur un modèle . .0-8 0.3.3 FlexCC: un compilateur basé sur des règles . .0-8 0.3.4 Discussion . .0-9 0.4 Aspects pratiques pour la conception de compilateurs . 0-10 0.4.1 Support du langage source . 0-10 0.4.2 Les différents niveaux d’abstraction du codage . 0-10 0.4.3 Les stratégies de validation . 0-12 0.4.4 Le débogage . 0-12 0.5 Transformations pour les unités de calcul d’adresses . 0-13 0.5.1 Les unités de calcul d’adresses pour les architectures de traitement de signal . 0-13 0.5.2 Techniques de génération d’adresses traditionnels . 0-14 0.5.3 Une transformation pour le calcul d’adresses postérieur . 0-14 0.6 Expériences industrielles liées aux méthodes de compilation .