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INF 5460 • When a is used in an , oscillator, filter, Electronic noise – sensor, etc. it will also be a need for passive elements like Estimates and countermeasures resistors, capacitors and coils to provide biasing so that the transistor has the correct working point. These passive elements will influence on the noise. In the following we will Lecture 13 (Mot 10) look at some architectures and how they affect the equivalent Amplifier Architectures input noise.

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Miller capacitance Transistor configurations: Before we look at the transistor configurations we need a fast  There are mainly three alternatives for placing a FET/BJT in an repetition of the Miller effect. architecture: CS/CE has both voltage and FET BJT • When a capacitor is connected between a signal line and a current amplification resulting stable potential the signal line will experience a capacitance in the highest gain. But it has CS: CE: according to the standard formula (C=A/t). also the highest input Common Common • If the potential on the other side are in phase a smaller capacitance (due to the Miller Source Emitter effect) capacitance will be experienced. If the signal is exactly equal CD/CC has a high current the capacitance will "disappear". gain but a voltage gain close CD: CC: • If the signal is in opposite phase the experienced capacitance to one. It has a low input Common Common capacitance (from the Miller will be larger. If it is in opposite phase and exactly equal the Drain Collector effect) resulting in a high capacitance will be double. input impedance. It also has low output impedance. CG: CB: CG/CB is used to achieve Common Common low input impedance and high Gate Base output impedance. 3 4

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10-2 The voltage gain Kt: The schematic shows a transistor that is biased for low noise operation   R  Z || R  between 10Hz and 10kHz.  L  i D  Kt     The noise values are as follows:  Zi  Z S  Zi || RD  10Hz 10kHz Kt is the voltage gain from Vs to Vo. The first parenthesis is the voltage En 2nV 2nV gain within the transistor ( is ICE/IBE) while the second parenthesis is the In 2pA 0.3pA network in front of the base. R0 1000 6700 Z  r  r   1Z NF@R0 1.8dB 0.3dB i x  E The noise schematic shows a hybrid- The input resistance Zi includes the resistance you can see through the model together with passive bias base towards emitter. R  R || r || R elements. L C 0 i2 The load resistance consists of the collector bias resistance, the transistor Note that when VEE and VCC are stable internal resistance and the input resistance of the next stage: Ri2.

DC-sources that are merged together Z E  RE ||  jX E with ground during noise analysis. The emitter impedance consists of a real part and an imaginary part (a 5 resistance and a capacitance in parallel). 6

ZS  RS  jX C We will then have the following expression for the equivalent input noise: 2 The source impedance is a resistance in series with a capacitor.  R  R  2 2 2  S D  2 2 2 2 Eni  Ens  En    In RS  jX C   I D RS  RD  If we assume ignorable loss in biasing, 2 coupling and feedback we can simplify E 2  E   E   C  the expression for Kt to: 2   1 RECE   K't 

RL In the expression, we recognise the first line (say from section. 7.3). Kt   Last term is also known. The second last term, however, need some Z S  rx  r  Z E comments. The voltage over RE will not be EE for higher frequencies, If Zs ≪ r and ZE ≪ re the expression is simplified to: because CE will "attempt to short-circuit" this. We choose to model the R L thermal noise in RE as a current noise of size IE=EE/RE. The noise Kt    gm RL re current over RE and CE will be: 2 2 2 If we simplify and ignore the external load we have: 2 2 EE RE EE E'E  I E CE || RE   2  2 K't  Kt for RL  RC RE jRECE 1 1 RECE 

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Choice of capacitance values Back to the expression for Eni: 2  R  R  CC is a high pass filter together with the resistances at the transistor gate E 2  E 2  E 2  S D   I 2 R  jX 2  I 2 R2 ni ns n   n  S C  D S (I.e. bias resistance in parallel with the transistor input resistance).  RD  2 With regard to noise, 1/(CC) should be much less than RS at the lowest E 2  E   E   C  relevant frequency. This is because these are added and determines the 1 R C 2  K'   E E   t  contribution of In: In(RS+j/(CC)). Obviously the last term should be tried From the expression we find that to have low noise: made small (<1/100) relative to RS. NB! Hence due to noise CC must not  RD should be large relative to RS. be used intentionally for filter functions!  CC should be large.

 Rs should be small. CE should short-circuit the emitter AC-wise to ground. The impedance of  RE should be small if CE is not large CE should be small relative to the internal resistance in the emitter: re.  CE should be large. Basically noise in RE has the same weight as the noise in the source

 Kt should be large. (gain=1), however CE will reduce the contribution from RE.

If the AC-coupling is not needed, we can remove RD and CC. 2 CE (Common Emitter) has the greatest power amplification. Thus noise from EtE 2 stages following the amplifier can probably be ignored. 2 2 2  ES 1 RECE 9 10

Common-emitter with one voltage supply

• Here a point A is established supplying a stable DC The equivalent input noise can potential for the base. The be expressed as: 2 point A is AC-wise short  R  R  E 2  E 2  E 2  S D   I 2 R  jX 2 ni ns n   n  S C  circuited to ground through  RD  B 2 2 2 2 2 C .  E A EB 2  RS EE  EC      ED      2 2 2 2  K'  1 RACB  1 RBCB   RD 1 RE CE   t  In addition to the known terms, we have now a new term in square 10Hz 10kHz parenthesis due to the base bias network. The parenthesis is En 4.5nV 4.5nV weighted with the RS/RD ratio. In 0.3pA 0.1pA R0 10k 45k The DC-voltage at the base is determined by the relationship NF@R0 0.68dB 0.35dB between RA and RB as follows: R V Kt 280 B CC VA  Ri 780 RA  RB 11 12

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Noise in cascaded stages We have previously studied the noise figure for cascaded . We will now look at the equivalent input noise: The contributing noise from the resistors RA and RB should be relatively small. A good starting point is to choose CB so large that the noise in the relevant frequency range satisfies the inequality:

2 2 2 EtA EtB EtD  2 2 2  2 2 2 1  RACB 1  RBCB The expression for equivalent input noise can be expressed as follows 2 2 2 2 2 2 2 2 2 2 2 En2  In2ro1 En3  In3ro2 Eni  Ens  En1  In1RS  2  2 2   Kt1 Kt1Kt2 Here ro1 is the output resistance of stage 1. Similarly for ro2, ro3 etc. Kti is as earlier the voltage gain.

As previously if the gain is large enough in the first stage, noise from 13 subsequent stages can be ignored. 14

Common-source --- common-emitter couple • CS provides high input impedance and high voltage gain. There are three methods one can use for noise analysis of more • The example uses a complex systems such as cascaded network: JFET but the • Manual network analysis (hand calculations), considerations does • use a simulator (like LTspice), or also apply to • measure the system after realisation. .

Trick for simulation (and measurement): If you are unsure of the impact of noise from a source - simulate with this source only and inspect the simulation results at the 10Hz 10kHz output. En 8nV 4nV In 7fA 7fA R0 1.1M 570k NF@R0 0.03dB 0.015dB 15 16

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To reduce the En1-noise contribution from the FET we may consider The voltage amplification for the increasing ID1. But this requires a smaller RD1 which means less total CS-stage is: g m1RL1 gain. Kt1   1 g m1Z S1 RL1 and ZS1 are given by: The expression for the equivalent input noise for this circuit is: 2 R  R || r || R  R  R  E 2 R 2 L1 D1 d i2 E 2  E 2  E 2  G1 S   I 2 R  jX 2  G1 S ni ns n1  R  n1 S C1 R 2 and  G1  G1 Z  R ||  jX 2 2 S1 S1 S1 ES1 1 2 2 2 2 EC 2   ED1  En2  I n2 RD1  1 R C 2 K 2 K 2 The total voltage gain is: S1 S1 t1 tc G1 S g m1RL1RC 2 • R must be large compared to R K tc  • CC1 must be large compared to RS 1 g m1Z S1 rx2  r 2  • CS1 must be sufficient large When r2 ≫ RD1 and RC2 ≫ ro2 • Kt1 should be large and we have that: g m1RD1RC 2 K tc  • Ktc should be large. re2 17 18

Common-collector --- Common-emitter CC-CE has only a little larger En than a pure CE stage but can offer Equivalent input noise is: 2 2 higher input resistance E 2  I R   E  E 2 E 2  E 2  E 2  I 2 R 2  n2   n2 E1    E1   C2 and lower input ni ns n1 n1 S 2     2 capacitance. Kt1  K't1   K't1  Ktc K’t1 is the gain in the first CC stage with RE1 as load.

1RE1 RE1 First stage has a gain of approx. 1. The total gain is: K't1   RS  rx1  r 1 re1  RS 1 1  2 RL1 RC 2 K tc   • In CC and CD should the emitter/source resistance be large. RS  rx1  r 1  1 RL1 rx2  r 2   2 Z E 2  Where RL1  RE1 || rx2  r 2   2 Z E 2 

The expression for Ktc can be simplified when 1RL1 ≫ (RS+rx1+r1) and r2 ≫ rx2+2ZE2: RC 2 Ktc   re2 19 20

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Common-Emitter --- Common-Base CE-CB has low input capacitance and high output impedance. Due to the low input resistance of the second stage the voltage gain of the first The total power gain can be expressed as:  R  R stage will be low. This reduces the high frequency feedback (Miller K   1 L1 2 C2  tc r  r  R   Z  r  r  Z  effect) through C as discussed before. The input capacitance is thus x1  1 S 1 E1  2 x2 B2   R R much less than for a regular CE step.  1 2 L1 C2 rx1  r1  RS  1Z E1 r 2  rx2  ZB2  Where rx2  r1  Z B2 RL1  RC1 ||  re2  2 When RS=0 and RC1 ≫ r/2 we can simplify Ktc to: RC2 Ktc   re1 The equivalent input noise is: 1 E2  E2  E2  I 2 R2  E2  E2  I 2 R  Z 2 Q1 provides power amplification but not voltage gain (i.e. Q1 provides a ni ns n1 n1 S 2  C1 n2 n2 L1 B2  Kt1 current gain.) Q2 provides a large voltage gain. 2 2 2 EA2 EB2 EC 2 RC1 is used to provide extra collector current to Q2 when there is a need  2 2  2 2  2 Kt11 CB2RA2   Kt11 CB2RB2   Ktc for large gain-bandwidth. 21 22

Integrated BJT cascade amplifier Here Q1 acts as a CE-stage and Q2 as a CB- stage. Q3 is load. The total voltage gain is:

ro3 K tc   re1 The equivalent input noise is: CC-CE CE-CB CE-3pow CE-2pow CS-CE 2 2 2 2 2 2 1 2 2 2 Eo3 10Hz 10kHz 10Hz 10kHz 10Hz 10kHz 10Hz 10kHz 10Hz 10kHz Eni  Ens  En1  I n1RS  2 En2  I n2 re2  Z B2   2 Kt1 K tc En 2nV 2nV 4.5nV 4.5nV 8nV 4nV 6nV 5.8nV 1.6nV 1.4nV Here is Kt1=re2/re1. Since the collector currents In 2pA 0.3pA 0.3pA 0.1pA 7fA 7fA 0.3pA 0.1pA 20pA 1.5pA are equal is Kt1=1. ZB2 is the impedance to R0 1k 6.7k 10k 45k 1.1M 570k 20k 58k 80 930 VBB2 (should be low). Since Re2 also is small NF@R0 1.8dB 0.3dB 0.68dB 0.35dB 0.9dB 0.3dB 7dB 1dB the contribution from In2 should also be ignorable.

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Differential amplifiers – two sources The two input signals V1 and V2 The noise voltage from Q3 is: can be defined relative to a Eo3  En3Kt3 common value (common-mode) The gain in Q3 is: ro2 VC, and a difference value VD. Kt3   Ktc re3 V V V  1 2 V  V V With these simplifications and assuming all are equal C 2 and D 1 2 the expression for the equivalent input noise is reduced to: We will then have: 2 2 2 2 2 3 2 V Eni  Ens  En1  In1RS  En2  En3 D VD V1 VC  V2 VC  2 2 2 2 2 and 2  Ens  3En  In1RS The figure shows the noise schematic. The equivalent input noise is:

2 2 2 2 2 2 2 2 2 Eni  Ens1  Ens2  En1  En2  In1RS1  In2RS 2

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Differential connection – one source Noise model for the We assume that the positive and negative input has the Example of differential stage: same noise characteristics and adds together the En and In- a) values for the amplifier. Voltage gain of differential signal:

2 2 2 2 Vo2 Vo1  2RC EnT  En1  En2  2En1 K   dm 1 R Vs2 Vs1 S  RE  2 2 2 gm  2 2 2  RS  2  RS  I n1 2 I nT RS  I n1   I n2    RS  2   2  2 Here is gm=1/re for each of the transistors. When we add together with the noise from the source Assuming identical transistors and RC1=RC2=RC, RE1=RE2=RE and resistance, we obtain the equivalent input noise: RS1=RS2=RS. I 2 R2 2 2 2 n1 S For the typical cases where RE=0 and RS ≪ r we can simplify Eni  Ens  2En1  2 Kdm to:  2RC K dm  re 27 28

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b) V  V  R Gain for the common voltage signal: K  o2 o1  C Eni: cm V  V 1 R 2 2 2 2 2 2 2 2 2 s2 s1  R  S  2R Eni  ES1  ES 2  En1  En2  In1RS1  In2RS 2 g E  EE m E 2  E 2 E 2  E 2  E 2  E 2  E 2  C1 C 2  EE VEE VCC When REE is large we get:  R E1 E2 2 2 C Kdm Kdc Kcm  c) 2REE Differential voltage gain between outputs with common input signal: Here is EVEE and EVCC noise on the voltage supplies.  R 1   R 1   S 2   S1  RC1   RE2   RC2    RE1  Vo2 Vo1   2 gm2   1 gm1  Kdc   2V  R 1 R 1  S  S 2 S1  2REE    RE 2    RE1   2 gm2 1 gm1 

Ideally if the inputs were completely symmetrical Kdc should be 0. When this is not the case one can reduce Kdc say by increasing REE.

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Integrated BJT differential amplifier It can be relatively large variation in process parameters for integrated The figure shows the integrated version of the differential amplifier circuits from production to production. However between the elements we studied previously. on the same circuit the variation can be made very small. This is Equivalent input noise: exploited by using design strategies based more on the symmetry E 2  E 2  E 2  E 2  E 2  I 2 R 2  I 2 R 2 between the elements than on their actual values. ni s1 s2 n1 n2 n1 s1 n2 s2 2 2 2 In integrated circuits the common-mode noise rejection is improved. On 2 2 En5  EVEE  EVCC  En3  En4  2 the other hand, integrated circuits require compromises that may give Kdc more noise than when optimizing a process for a single isolated Since common-mode rejection is component. Examples of these compromises are: high and all active circuits have • long diffusion insulations, approximately the same geometry • active loads, and and noise mechanisms, Eni will be reduced to: • power sources. 2 2 2 2 2 Eni  2ES  4En  2In RS

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Parallel amplifier stages What when several amplifiers are placed in parallel? Schematically, we can draw noise sources as in the figure. En We have: E'n  and I'n  I n N N A new optimal source resistance can be defined as: E'n Ro R'o   I'n N

Gain is given by: A'v  NAv

A significant contribution to the En -noise in a BJT is the base resistance rx. The base resistance can be reduced by placing the base contacts all the way around the emitter and the closest possible on the emitter. In FETs it is determined by the channel resistances, and by gm. Low resistance and high gm can be achieved by having a large W/L ratio. By parallelising both the C’ and the Miller effect is increased. 33

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