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Miller Capacitance Transistor Configurations

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Miller Capacitance Transistor Configurations 15.11.2016 INF 5460 • When a transistor is used in an amplifier, oscillator, filter, Electronic noise – sensor, etc. it will also be a need for passive elements like Estimates and countermeasures resistors, capacitors and coils to provide biasing so that the transistor has the correct working point. These passive elements will influence on the noise. In the following we will Lecture 13 (Mot 10) look at some architectures and how they affect the equivalent Amplifier Architectures input noise. 2 Miller capacitance Transistor configurations: Before we look at the transistor configurations we need a fast There are mainly three alternatives for placing a FET/BJT in an repetition of the Miller effect. architecture: CS/CE has both voltage and FET BJT • When a capacitor is connected between a signal line and a current amplification resulting stable potential the signal line will experience a capacitance in the highest gain. But it has CS: CE: according to the standard formula (C=A/t). also the highest input Common Common • If the potential on the other side are in phase a smaller capacitance (due to the Miller Source Emitter effect) capacitance will be experienced. If the signal is exactly equal CD/CC has a high current the capacitance will "disappear". gain but a voltage gain close CD: CC: • If the signal is in opposite phase the experienced capacitance to one. It has a low input Common Common capacitance (from the Miller will be larger. If it is in opposite phase and exactly equal the Drain Collector effect) resulting in a high capacitance will be double. input impedance. It also has low output impedance. CG: CB: CG/CB is used to achieve Common Common low input impedance and high Gate Base output impedance. 3 4 1 15.11.2016 10-2 Common Emitter The voltage gain Kt: The schematic shows a transistor that is biased for low noise operation R Z || R between 10Hz and 10kHz. L i D Kt The noise values are as follows: Zi Z S Zi || RD 10Hz 10kHz Kt is the voltage gain from Vs to Vo. The first parenthesis is the voltage En 2nV 2nV gain within the transistor ( is ICE/IBE) while the second parenthesis is the In 2pA 0.3pA network in front of the base. R0 1000 6700 Z r r 1Z NF@R0 1.8dB 0.3dB i x E The noise schematic shows a hybrid- The input resistance Zi includes the resistance you can see through the model together with passive bias base towards emitter. R R || r || R elements. L C 0 i2 The load resistance consists of the collector bias resistance, the transistor Note that when VEE and VCC are stable internal resistance and the input resistance of the next stage: Ri2. DC-sources that are merged together Z E RE || jX E with ground during noise analysis. The emitter impedance consists of a real part and an imaginary part (a 5 resistance and a capacitance in parallel). 6 ZS RS jX C We will then have the following expression for the equivalent input noise: 2 The source impedance is a resistance in series with a capacitor. R R 2 2 2 S D 2 2 2 2 Eni Ens En In RS jX C I D RS RD If we assume ignorable loss in biasing, 2 coupling and feedback we can simplify E 2 E E C the expression for Kt to: 2 1 RECE K't RL In the expression, we recognise the first line (say from section. 7.3). Kt Last term is also known. The second last term, however, need some Z S rx r Z E comments. The voltage over RE will not be EE for higher frequencies, If Zs ≪ r and ZE ≪ re the expression is simplified to: because CE will "attempt to short-circuit" this. We choose to model the R L thermal noise in RE as a current noise of size IE=EE/RE. The noise Kt gm RL re current over RE and CE will be: 2 2 2 If we simplify and ignore the external load we have: 2 2 EE RE EE E'E I E CE || RE 2 2 K't Kt for RL RC RE jRECE 1 1 RECE 7 8 2 15.11.2016 Choice of capacitance values Back to the expression for Eni: 2 R R CC is a high pass filter together with the resistances at the transistor gate E 2 E 2 E 2 S D I 2 R jX 2 I 2 R2 ni ns n n S C D S (I.e. bias resistance in parallel with the transistor input resistance). RD 2 With regard to noise, 1/(CC) should be much less than RS at the lowest E 2 E E C relevant frequency. This is because these are added and determines the 1 R C 2 K' E E t contribution of In: In(RS+j/(CC)). Obviously the last term should be tried From the expression we find that to have low noise: made small (<1/100) relative to RS. NB! Hence due to noise CC must not RD should be large relative to RS. be used intentionally for filter functions! CC should be large. Rs should be small. CE should short-circuit the emitter AC-wise to ground. The impedance of RE should be small if CE is not large CE should be small relative to the internal resistance in the emitter: re. CE should be large. Basically noise in RE has the same weight as the noise in the source Kt should be large. (gain=1), however CE will reduce the contribution from RE. If the AC-coupling is not needed, we can remove RD and CC. 2 CE (Common Emitter) has the greatest power amplification. Thus noise from EtE 2 stages following the amplifier can probably be ignored. 2 2 2 ES 1 RECE 9 10 Common-emitter with one voltage supply • Here a point A is established supplying a stable DC The equivalent input noise can potential for the base. The be expressed as: 2 point A is AC-wise short R R E 2 E 2 E 2 S D I 2 R jX 2 ni ns n n S C circuited to ground through RD B 2 2 2 2 2 C . E A EB 2 RS EE EC ED 2 2 2 2 K' 1 RACB 1 RBCB RD 1 RE CE t In addition to the known terms, we have now a new term in square 10Hz 10kHz parenthesis due to the base bias network. The parenthesis is En 4.5nV 4.5nV weighted with the RS/RD ratio. In 0.3pA 0.1pA R0 10k 45k The DC-voltage at the base is determined by the relationship NF@R0 0.68dB 0.35dB between RA and RB as follows: R V Kt 280 B CC VA Ri 780 RA RB 11 12 3 15.11.2016 Noise in cascaded stages We have previously studied the noise figure for cascaded amplifiers. We will now look at the equivalent input noise: The contributing noise from the resistors RA and RB should be relatively small. A good starting point is to choose CB so large that the noise in the relevant frequency range satisfies the inequality: 2 2 2 EtA EtB EtD 2 2 2 2 2 2 1 RACB 1 RBCB The expression for equivalent input noise can be expressed as follows 2 2 2 2 2 2 2 2 2 2 2 En2 In2ro1 En3 In3ro2 Eni Ens En1 In1RS 2 2 2 Kt1 Kt1Kt2 Here ro1 is the output resistance of stage 1. Similarly for ro2, ro3 etc. Kti is as earlier the voltage gain. As previously if the gain is large enough in the first stage, noise from 13 subsequent stages can be ignored. 14 Common-source --- common-emitter couple • CS provides high input impedance and high voltage gain. There are three methods one can use for noise analysis of more • The example uses a complex systems such as cascaded network: JFET but the • Manual network analysis (hand calculations), considerations does • use a simulator (like LTspice), or also apply to • measure the system after realisation. MOSFETs. Trick for simulation (and measurement): If you are unsure of the impact of noise from a source - simulate with this source only and inspect the simulation results at the 10Hz 10kHz output. En 8nV 4nV In 7fA 7fA R0 1.1M 570k NF@R0 0.03dB 0.015dB 15 16 4 15.11.2016 To reduce the En1-noise contribution from the FET we may consider The voltage amplification for the increasing ID1. But this requires a smaller RD1 which means less total CS-stage is: g m1RL1 gain. Kt1 1 g m1Z S1 RL1 and ZS1 are given by: The expression for the equivalent input noise for this circuit is: 2 R R || r || R R R E 2 R 2 L1 D1 d i2 E 2 E 2 E 2 G1 S I 2 R jX 2 G1 S ni ns n1 R n1 S C1 R 2 and G1 G1 Z R || jX 2 2 S1 S1 S1 ES1 1 2 2 2 2 EC 2 ED1 En2 I n2 RD1 1 R C 2 K 2 K 2 The total voltage gain is: S1 S1 t1 tc G1 S g m1RL1RC 2 • R must be large compared to R K tc • CC1 must be large compared to RS 1 g m1Z S1 rx2 r 2 • CS1 must be sufficient large When r2 ≫ RD1 and RC2 ≫ ro2 • Kt1 should be large and we have that: g m1RD1RC 2 K tc • Ktc should be large.
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