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Edoxde Box -102 USOO8338260B2 (12) United States Patent (10) Patent No.: US 8,338,260 B2 Cheng et al. (45) Date of Patent: Dec. 25, 2012 (54) RAISED SOURCE/DRAINSTRUCTURE FOR 7,479,431 B2 1/2009 Hattendorf et al. ENHANCED STRAN COUPLING FROM 2005/0048732 A1* 3, 2005 Park et al. ..................... 438,305 2008. O157224 A1 7/2008 Fischer et al. STRESS LNER 2008, 0217686 A1 9/2008 Majumdar et al. 2009/0026504 A1 1/2009 Okuda et al. .................. 257/255 (75) Inventors: Kangguo Cheng, Guilderland, NY (US); 2009/003.9426 A1 2/2009 Cartier et al. ................. 257,344 Bruce Doris, Brewster, NY (US); Ali 2009,0261363 A1 10, 2009 Chen et al. Khakifirooz. Schenectady, NY (US); OTHER PUBLICATIONS Pranita Kulkarni, Slingerlands, NY (US); Ghavam Shahidi, Pound Ridge, Cheng, K., et al. “Fully Depleted Extremely Thin SOI Technology NY (US) Fabricated by a Novel Integration Scheme Featuring Implant-Free, Zero-Silicon-Loss, and Faceted Raised Source/Drain.” 2009 Symp. (73) Assignee: International Business Machines On VLSI Tech., Jun. 16-18, 2009, pp. 212-213. Corporation, Armonk, NY (US) Cheng, K., et al., “Extremely Thin SOI (ETSOI) CMOS with Record s s LowVariability for Low Power System-on-Chip Applications.” 2009 - r IEEE Int. Elec Dev Meeting, Dec. 7-9, 2009. (*) Notice: Subject to any disclaimer, the term of this Waite, A., et al., “Electrical Stressing of Submicrometre MOSFETs patent is extended or adjusted under 35 with Raised Source/Drain Structures Realised by Selective Epitaxial U.S.C. 154(b) by 255 days. Growth of Silicon Using Silane Only.” Electronics Letters, vol. 30. Issue 17, Aug. 18, 1994, pp. 1455-1456. (21) Appl. No.: 12/760,250 * cited by examiner (22) Filed: Apr. 14, 2010 Primary Examiner — Wensing Kuo (65) Prior Publication Data (74) Attorney, Agent, or Firm — Jose Gutman: Thomas US 2011 FO2S4O90 A1 Oct. 20, 2011 Grzesik; Fleit Gibbons Gutman Bongini & Bianco PL (51) Int. Cl. (57) ABSTRACT HOIL 2/336 (2006.01) A transistor is provided that includes a buried oxide layer (52) U.S. Cl. ................................ 438/300; 257/E21.409 above a substrate. A silicon layer is above the buried oxide (58) Field of Classification Search .................. 438/151, layer. A gate stack is on the silicon layer, the gate stack 438/197,300 including a high-koxide layer on the silicon layer and a metal See application file for complete search history. gate on the high-koxide layer. A nitride liner is adjacent to the gate stack. An oxide liner is adjacent to the nitride liner. A set (56)56 References Cited Olfacetedff draised ra1Sed SOurcefdra1nfolrain regionsreg1OnS havinghav1ng a part 1ncludinincluding a portion of the silicon layer. The set of faceted raised source/ U.S. PATENT DOCUMENTS drain regions also include a first faceted side portion and a 7,009,258 B2 3, 2006 Park et al. second faceted side portion. 7,053,400 B2 5, 2006 Sun et al. 7,138,320 B2 11/2006 Van Bentum et al. 6 Claims, 5 Drawing Sheets 222 3526 328 22O 84-O T 84-O /SILICIDEN POLY /SLICIDEN X S44. 218 || DOPED RSD N CY DOPED RSD -1O4 EDOXDE BOX N \ \ \ 4. ^ ^ / ^ ^ ^ ^ M / ^ / / -102 ^ / ^ U.S. Patent Dec. 25, 2012 Sheet 1 of 5 US 8,338,260 B2 PAD NITRIDE BREDOXDE BOX) SSUBSTRATE FG. 1 J-224 --222 J-22O POLY 218 O S 7 ST 214 WELL al BURIED OXIDE (BOX) SSUESTRATE FG, 2 U.S. Patent Dec. 25, 2012 Sheet 2 of 5 US 8,338,260 B2 / / FG. 3 224, 326 3523 BREDOXDE BOX FG, 4. U.S. Patent Dec. 25, 2012 Sheet 3 of 5 US 8,338,260 B2 224, 326 328 \ \xi \, BREDOXDE BOX) SSESTRATE r102 F.G. 5 224, 326 328 POLY || | - (633 y-532 218 / LLL LIN RSD S. 14 will 216 \, BURIED OXIDE (BOX) Y. X Y. Y. Y. X SSESTRATE r102 FIG. (3 U.S. Patent Dec. 25, 2012 Sheet 4 of 5 US 8,338,260 B2 222 326 3523 FIG. 7 222 326 3523 STI ) 52O WELL ( STI raio FG, 8, U.S. Patent Dec. 25, 2012 Sheet 5 of 5 US 8,338,260 B2 222 326 523 S- T 34-O -T 20 aao POLY M-944 /SILICIDEN 218 N /SILICIDEN DOPEDRSD Numa / DOPEDRSD ^ /f Ezona SC 1^ / st ^ . 31 (6 BREDOXDE (BOX) rO SSESTRATE 102 FG. 9 222 326 3528, F.G. 1C) (PRIOR ART) US 8,338,260 B2 1. 2 RAISED SOURCEADRAN STRUCTURE FOR the separate views, and which together with the detailed ENHANCED STRAN COUPLING FROM description below are incorporated in and form part of the STRESS LNER specification, serve to further illustrate various embodiments and to explain various principles and advantages all in accor FIELD OF THE INVENTION dance with the present invention, in which: The present invention generally relates to the field of semi FIGS. 1 to 9 are cross-sectional views of a process for conductors, and more particularly relates to extremely-thin forming an extremely-thin silicon-on-insulator transistor silicon-on-insulator field-effect transistors. with faceted raised source? drains according to an embodi ment of the present invention; and BACKGROUND OF THE INVENTION 10 FIG. 10 is a cross-sectional view of a conventional Field Effect Transistor with conventional raised source/drains. Complementary Metal Oxide Semiconductor (“CMOS) Field Effect Transistors (“FETs) are employed in almost DETAILED DESCRIPTION every electronic circuit application, such as signal processing, computing, and wireless communications. One known type 15 As required, detailed embodiments of the present invention ofFET is an Extremely Thin Silicon-On-Insulator (“ETSOI) FET. One problem experienced with ETSOI FETs is the are disclosed herein; however, it is to be understood that the effectiveness of the nitride stress liner. In ETSOI designs with disclosed embodiments are merely exemplary of the inven a raised-source and drain (RSD) design the effectiveness of tion, which can be embodied in various forms. Therefore, the nitride liner is diminished. This is because the RSD prox specific structural and functional details disclosed herein are imity of the stress liner to the Si interface is reduced. not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in SUMMARY OF THE INVENTION the art to variously employ the present invention in virtually any appropriately detailed structure. Further, the terms and In one embodiment, a transistoris disclosed. The transistor comprises a buried oxide layer above a Substrate. A silicon 25 phrases used herein are not intended to be limiting; but rather, layer is above the buried oxide layer. A gate stack is on the to provide an understandable description of the invention. silicon layer, the gate stack including a high-koxide layer on The terms 'a' or “an', as used herein, are defined as one as the silicon layer and a metal gate on the high-koxide layer. A or more than one. The term plurality, as used herein, is defined nitride liner is adjacent to the gate stack. An oxide liner is as two as or more than two. Plural and singular terms are the adjacent to the nitride liner. A set of faceted raised source/ 30 same unless expressly stated otherwise. The term another, as drain regions comprising a part comprising a portion of the used herein, is defined as at least a second or more. The terms silicon layer. The set of faceted raised source/drain regions including and/or having, as used herein, are defined as com also comprise a first faceted side portion and a second faceted prising (i.e., open language). The term coupled, as used side portion. herein, is defined as connected, although not necessarily In another embodiment, an integrated circuit comprising at 35 directly, and not necessarily mechanically. The terms pro least one transistor is disclosed. The transistor comprises a gram, Software application, and the like as used herein, are buried oxide layer above a substrate. A silicon layer is above defined as a sequence of instructions designed for execution the buried oxide layer. A gate stack is on the silicon layer, the on a computer system. A program, computer program, or gate stack including a high-k oxide layer on the silicon layer Software application may include a Subroutine, a function, a and a metal gate on the high-k oxide layer. A nitride liner is 40 procedure, an object method, an object implementation, an adjacent to the gate stack. An oxide liner is adjacent to the executable application, an applet, a servlet, a source code, an nitride liner. A set of faceted raised source/drain regions com object code, a shared library/dynamic load library and/or prising a part comprising a portion of the silicon layer. The set other sequence of instructions designed for execution on a of faceted raised source/drain regions also comprise a first computer system. faceted side portion and a second faceted side portion. In yet another embodiment, a method for fabricating a 45 FIGS. 1 to 9 illustrate a process for forming an extremely transistor is disclosed. The method comprises forming a gate thin silicon-on-insulator transistor according to an embodi stack on a silicon layer that is above a buried oxide layer. The ment of the present invention. The process begins with an SOI gate stack comprises a high-koxide layer on the silicon layer wafer that is formed by a silicon substrate 102, a buried oxide and a metal gate on the high-koxide layer. A first nitride layer layer (“BOX) 104, and an SOI layer 106. It should be noted is formed on the silicon layer and the gate stack.
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