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UNIVERSITY of CALIFORNIA Los Angeles Design, Evaluation and Co UNIVERSITY OF CALIFORNIA Los Angeles Design, Evaluation and Co-optimization of Emerging Devices and Circuits A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy in Electrical Engineering by Shaodi Wang 2017 c Copyright by Shaodi Wang 2017 ABSTRACT OF THE DISSERTATION Design, Evaluation and Co-optimization of Emerging Devices and Circuits by Shaodi Wang Doctor of Philosophy in Electrical Engineering University of California, Los Angeles, 2017 Professor Puneet Gupta, Chair The continued push for traditional Silicon technology scaling faces the main chal- lenge of non-scaling power density. Exploring alternative power-efficient technologies is essential for sustaining technology development. Many emerging technologies have been proposed as potential replacement for Silicon technology. However, these emerging tech- nologies need rigorous evaluation in the contexts of circuits and systems to identify their value prior to commercial investment. We have developed evaluation frameworks cover- ing emerging Boolean logic devices, memory devices, memory systems, and integration technologies. The evaluation metrics are in terms of delay, power, and reliability. Ac- cording to the evaluation results, the development of emerging Boolean logic devices is still far from being able to replace Silicon technology, but magnetic random access mem- ory (MRAM) is a promising memory technology showing benefits in performance and energy-efficiency. As a specific example, we co-optimize MRAM with application circuits and systems. Optimized MRAM write and read design can significantly improve the system perfor- mance. We have proposed magnetic tunnel junction (MTJ) based process and tem- perature variation monitor, which enables variation-aware MRAM write and read op- timization. We have also proposed utilizing negative differential resistance (NDR) to enable fast and energy-efficient write and zero-disturbance read for resistive memories including MRAM. In addition, we also design and adapt MRAM technology into low- power stochastic computing system to improve energy-efficiency. To further improve ii the stochastic computing system, a promising VC-MTJ based true random stochastic bitstream generator is proposed and utilized. iii The dissertation of Shaodi Wang is approved. Yuan Xie Subramanian S. Iyer Kang L. Wang Puneet Gupta, Committee Chair University of California, Los Angeles 2017 iv I dedicate my PhD dissertation to my wife, my parents, my advisor, and my labmates. v Table of Contents 1 Introduction :::::::::::::::::::::::::::::::::::: 1 1.1 Emerging Technology Introduction . .2 1.1.1 Emerging Boolean Logic Devices . .2 1.1.2 Emerging Memories . .3 1.1.3 Voltage-control Magnetic Tunnel Junction (VC-MTJ) . .4 1.1.4 Emerging Integration Technologies . .5 1.1.5 Emerging Memory System Reliability . .7 1.2 Emerging Technologies Evaluation . .7 1.3 Design for Efficient MRAM Write and Read . .8 1.3.1 Optimized MRAM Write and Read Enabled by MTJ-based Varia- tion Monitor . .9 1.3.2 Negative Differential Resistance-assisted NVM Write and Read . .9 1.4 Stochastic Non-volatile Computing using MTJ . 11 2 PROCEED: A Pareto Optimization-based Circuit-level Evaluator for Emerging Devices :::::::::::::::::::::::::::::::::: 13 2.1 Chapter Introduction . 13 2.2 Overview of PROCEED Framework . 15 2.2.1 Canonical Circuit Construction . 16 2.2.2 Delay and Power Modeling . 18 2.2.3 Area Modeling . 18 2.2.4 Process Variation and Voltage Drop . 20 2.2.5 Interconnect Load . 20 2.2.6 Pareto-Based Optimization . 20 2.2.7 Power Management Modeling . 21 vi 2.2.8 Activity Factor . 22 2.2.9 Multiple Vdd and Vt .......................... 23 2.2.10 Heterogeneous Integration . 23 2.3 Pareto Optimization . 24 2.4 Experiment Results . 28 2.4.1 Framework Evaluation . 29 2.4.2 Impact of Multiple Vdd, Vt, and Gate Sizing . 30 2.4.3 Impact of Interconnect Load . 31 2.4.4 Impact of Benchmarks on Evaluation SOI vs. TFET . 32 2.4.5 Impact of Activity Factor SOI vs. TFET . 34 2.4.6 Power Management Modeling . 35 2.4.7 Variation-Aware Evaluation . 35 2.4.8 Heterogeneous Integration Evaluation . 36 2.5 Chapter Conclusion . 38 3 Evaluation of Digital Circuit-Level Variability in Inversion-Mode and Junctionless FinFET Technologies :::::::::::::::::::::::: 40 3.1 Chapter Introduction . 40 3.2 Overview of Evaluation Framework . 41 3.3 Variability and Device Modeling . 42 3.3.1 LER and RDF Modeling . 42 3.3.2 Device-Level Variability . 44 3.3.3 Device and Variability Model Fitting . 45 3.4 Variability Impact on 6T SRAM Memory . 47 3.4.1 Baseline Nominal Static Noise Margin . 47 3.4.2 Minimum Working Vcc (Vccmin)................... 48 3.4.3 SNM Versus Technology . 51 vii 3.5 LER Impact on Logic Circuit Variability . 52 3.5.1 Overview . 52 3.5.2 Circuit Statistical Timing and Power Analysis . 52 3.5.3 Circuit Simulation Results . 53 3.6 Chapter Conclusion . 55 4 MEMRES: A Fast Memory System Reliability Simulator ::::::: 57 4.1 Chapter Introduction . 57 4.2 MEMRES Software Framework . 60 4.2.1 Pre-sim Processing . 60 4.2.2 Monte-Carlo Simulator . 61 4.2.3 Fault-map and Access-map . 63 4.2.4 Basic Operations . 66 4.2.5 Modeling . 68 4.2.6 Trade-off between Accuracy and Speed . 76 4.3 Framework Validation . 77 4.4 A Study of STT-RAM using MEMRES . 82 4.5 Chapter conclusion . 88 5 Comparative Evaluation of Spin-Transfer-Torque and Magnetoelectric Random Access Memory :::::::::::::::::::::::::::::: 89 5.1 Chapter Introduction . 89 5.2 Modeling and Simulation . 90 5.3 Scalability . 95 5.4 MRAM Cell Design and Variation . 96 5.5 Write Error Rate of MRAM . 98 5.5.1 Write Error Rate of MTJs without Variation . 98 5.5.2 Write Error Rate of MRAM Array . 99 viii 5.6 Circuit-level Evaluation . 103 5.6.1 MRAM Write/Read with PWSA Multi-write Design . 103 5.6.2 Failure Analysis and Error Correction . 108 5.6.3 Latency, Energy, and Area of a 16-MB MRAM Bank . 111 5.7 Chapter Conclusion . 112 6 MTJ Variation Monitor for Adaptive MRAM Write and Read :::: 113 6.1 Chapter Introduction . 113 6.2 Write Error and Read Disturbance Rates under Variation . 114 6.3 MTJ based Variation Monitor . 116 6.3.1 Sensing Principle . 116 6.3.2 Circuit Implementation and Simulation . 117 6.4 Adaptive Write . 121 6.4.1 Adaptive Write Scheme . 121 6.4.2 Adaptive Write using Variation Monitor . 122 6.5 Adaptive Read . 125 6.5.1 Adaptive Sensing Circuit using Multiple Reference Resistance . 126 6.6 Chapter Conclusion . 129 7 Negative Differential Resistance-Assisted Resistive NVM for Efficient Read and Write Operations :::::::::::::::::::::::::::: 130 7.1 Chapter Introduction . 130 7.2 Issues of MRAM Write and Read . 131 7.2.1 Wasted Power During Write Cycles . 131 7.2.2 Read Margin and Read Disturbance Limits . 132 7.3 NDR Device Characteristics . 132 7.3.1 Tunneling-Based V-NDR Devices . 132 7.3.2 CMOS Circuit for V-NDR Generation . 133 ix 7.3.3 CMOS Circuit for C-NDR Generation . 134 7.4 Behavior of Series-Connected MTJ and V-NDR Devices . 135 7.5 Modeling of V-NDR Devices . 138 7.5.1 Tunneling V-NDR Modeling . 138 7.5.2 Analytical Model of CMOS V-NDR Behavior . 139 7.6 V-NDR-assisted MRAM Write and Read . 141 7.6.1 STT-RAM Write Energy Reduction . 141 7.6.2 STT-RAM Read Assistance using NDR . 145 7.6.3 Experimental Validation . 148 7.6.4 Array-level Reliability and Performance . 151 7.7 V-NDR and C-NDR for MLC ReRAM Programming . 158 7.8 Chapter Conclusion . 160 8 Hybrid VC-MTJ/CMOS Non-volatile Stochastic Logic for Efficient Com- puting ::::::::::::::::::::::::::::::::::::::::: 162 8.1 Chapter Introduction . 162 8.2 Overview of SC . 163 8.3 VC-MTJ and V-NDR in SC . 164 8.3.1 Non-destructive VC-MTJ Read with NDR . 165 8.3.2 Deterministic VC-MTJ Write with NDR . 166 8.4 VC-MTJ based Operations in Stochastic Computing . 167 8.5 Stochastic Bit Stream Generator . 170 8.6 Evaluation . 171 8.7 Chapter Conclusion . 173 9 Conclusion ::::::::::::::::::::::::::::::::::::: 174 References ::::::::::::::::::::::::::::::::::::::: 176 x List of Figures 1.1 STT-MTJ and VC-MTJ are switched through current and voltage respec- tively. .3 1.2 Density and write time of memories. .6 1.3 (a) Original stack of interconnect layers on top of device layers in SOI process (b) New stack with M−1 and V−1..................6 1.4 (a) Load line for V-NDR-MTJ series circuit (illustrated in inset). Blue and red line correspond to the MTJ HRS and LRS respectively. The stable operating points when the MTJ is in HRS and LRS are indicated by 1 and 2 , respectively. (b) Diagram of proposed 3T CMOS circuit for generating V-NDR between IN and OUT terminals. 10 1.5 (a) One example of C-NDR comprising of a Schmitt trigger and an NMOS. The Schmitt trigger has two threshold.
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